The invention relates to a solder material for use in electronic assembly.

There are two major challenges associates with the packaging and assembly of high-power electronic devices, such as IGBTs, MOSFETs, High-power LEDs, high power microprocessors and other large area devices generating a lot of heat during normal operation. The first is how to ensure efficient dissipation of the heat generated to maintain normal operating temperature. The second is how to reduce the shear stress due to coefficient of thermal expansion (CTE) mismatch between materials of the adjacent layers attached by a solder or other adhesive material.

Figure 1 shows the assembly of a typical electronic device 1 , which includes a device 2 connected via an interconnect 3 (Level I) to a substrate 4. The substrate 4 is connected via an interconnect 5 (Level II) to a printed circuit board (PCB) 6. The PCB 6 is connected via an interconnect 7 (Level III) to a heat sink 8. The most important interconnects for a high-power electronic device are those connecting device/die to substrate, substrate to printed circuit board (PCB) and PCB to heatsink, i.e. 3, 5 and 7 of Figure 1. Such interconnects are in the path of heat dissipation. Accordingly, high thermal conductivity of the interconnect material is desired. Semiconductor die, substrate and PCB materials have different CTEs, thereby resulting in a stress at the interface during high temperature operation. To minimize that stress, designers usually increase the interface thickness of the interconnect, but this in turn increases the thermal resistance of the interface.

Solders are one the most common interconnect materials used in electronic industry. Thermal conductivity of most of the solders is below 65 W/m.K. It would be advantageous to be able to use an interconnect material with higher thermal conductivity so as to aid heat dissipation. Another problem with thick solder interconnects is that during the reflow process, when solder is in the liquid phase, the die or substrate is floating on a liquid material before it is cooled down to below the solder’s freezing temperature. This results in movement of the die/substrate in all directions (so-called “tilt”), which is another concern for the device performance and reliability. Controlling this die movement is a challenge.

The present invention seeks to tackle at least some of the problems associated with the prior art or at least to provide a commercially acceptable alternative solution thereto.

In a first aspect, the present invention provides a solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

Each aspect or embodiment as defined herein may be combined with any other aspect(s) or embodiment(s) unless clearly indicated to the contrary. In particular, any features indicated as being preferred or advantageous may be combined with any other feature indicated as being preferred or advantageous.

The inventors have surprisingly found that when used to connect components of an electronic device operated at elevated temperatures, such a solder material may be capable of reducing stress caused by a mismatch in CTE values of the connected components. Without being bound by theory, it is considered that the presence of the core material serves to “thicken” the joint between the connected components, thereby decreasing the stress. Advantageously, such a reduction in stress may be provided without significantly reducing heat dissipation from the connected parts. Without being bound by theory, it is considered that this is because the thermal conductivity of the core material is greater than the thermal conductivity of the solder. In other words, by using a core material having a greater thermal conductivity than that of the solder, it is possible to thicken the joint to reduce thermal stress without reducing heat dissipation. As a result, a high-power electronic device, such as an IGBT, MOSFET, high-power LEDs, high-power microprocessor or other large area device generating a lot of heat during normal operation, in which components are connected using the solder material, may exhibit improved performance and/or reliability. Such performance and reliability may be improved at elevated temperatures and/or during switching on and off.

A joint or interconnect formed using the solder material may better thermo mechanical reliability as compared to typical Pb-free solders, such as SnCu, SAC, SnAg and SnBi.

The term “electronic assembly” used herein encompasses, for example, the assembly of electronic packages and devices and may include, for example, the attachment of a device or die to a substrate, a substrate to a printed circuit board, or a printed circuit board to a heat sink.

The term “solder” used herein encompasses a fusible metal or metal alloy with a melting point in the range of from 90 to 400 °C.

The solder material comprises solder layers and a core layer. The solder material may consist essentially of, or consist of, the solder layers and core layer. By “consisting essentially of”, it is meant that the solder material may comprise other non-specified components provided that they do not materially affect the properties of the solder material.

The solder material typically comprises two solder layers, but may comprise more than two solder layers. The solder layers may be formed of the same solder or different solders. Typically, the solder layers are formed of the same solder, or at least solders having similar reflow temperatures, i.e. liquidus temperatures differing by no more than 20 °C, typically no more than 10 °C, more typically no more than 5 °C.

The solder and core are in the form of layers. Such layers will typically be in the form of a sheet, with two opposing surfaces (major surfaces) having a significantly greater surface area than the other surfaces. The solder layers may be the same size and shape or may be different sizes and/or shapes. The core layer may have a similar size and shape to one or more of the solder layers, or may have a different size and/or shape.

The core layer comprises a core material. The core layer may consist essentially of, or consist of, the core material.

The core layer is sandwiched between the solder layers. Typically, the solder layers will cover substantially the entirety of at least two opposing surfaces of the core layer, typically the major (i.e. greatest surface area) surfaces. The core layer may be entirely encapsulated within the solder so that no core material is exposed. In such a situation, a first solder sheet is considered to cover a major surface of the sheet, and a second solder layer is considered to cover the opposing major surface of the sheet, with the two solder layers “over hanging” the major surfaces so as to cover the remaining surfaces of the core layer. Alternatively, the core layer may be covered by solder layers on only some of the surfaces, typically only two opposing surfaces, more typically the major surfaces.

The solder layers are typically in direct contact with the core layer. The solders layers are typically outer layers.

The thermal conductivity of the core material is greater than the thermal conductivity of the solder. Typically, such thermal conductivity is measured by a nano-flash transient measurement technique.

The core material preferably has a thermal conductivity of greater than or equal to 65 W/m.K, preferably greater than 65 w/m.K, more preferably greater than 70 W/m.k, even more preferably greater than 75 W/m.K. The core material may have a thermal conductivity of less than 600 W/m.K. Such thermal conductivity may be measured by a nano-flash transient measurement technique. Since typical solders employed in electronic assembly have a thermal conductivity of less than 65 w/m.K, the presence of the core material having a higher thermal conductivity increases the overall thermal conductivity of the solder material.

The melting point of the core material is preferably greater than the reflow temperature of the solder. For example, the core material may have a melting temperature that is at least 50 °C higher than the reflow temperature of the solder, typically at least 75 °C higher, more typically at least 100 °C higher. The term "reflow temperature" is used herein to refer to the temperature above which a solid mass of solder is certain to melt (as opposed to merely soften). If cooled below this temperature, the solder will not flow. Warmed above it once more, the solder will flow again, i.e. "re-flow". By having a core material with a melting temperature higher than the reflow temperature of the solder, the thickness of the joint / interconnect may be increased without a substantial increase in the die/package movement and/or tilt, which results from the die/package floating on top of the liquid solder when the solder is in the liquid state. This may improve the performance or reliability of an electronic device having components connected using the solder material.

The thickness of the core layer is preferably from 100 to 500 pm, more preferably from 200 to 400 pm, even more preferably from 150 to 300 pm. Such thicknesses may be particularly suitable for reducing stress caused by CTE mismatch of components without unduly increasing the size of the electronic device. Larger thicknesses may increase the thermal resistance. Relatively higher thickness may result in higher resistance but lower lateral stress.

The thickness of each solder layer is preferably from 25 to 150 pm, more preferably from 50 to 100 pm, even more preferably from greater than 50 to 99 pm, even more preferably from 55 to 95 pm, still even more preferably from 60 to 90 pm. In a preferred embodiment, the thickness of each solder layer is from greater than 50 pm to 150 pm. In another preferred embodiment, the thickness of each solder layer is from 55 pm to 150 pm. Such thicknesses may be particularly suitable for providing adequate adhesion between components without significantly decreasing the overall thermal conductivity of the solder material or unduly increasing the size of the device. Lower thicknesses may result in higher lateral stress during high temperature operation of temperature cycling.

Thickness of the core and the solder layers may be selected as desired by the package design and to achieve the desired thickness of the interconnect.

The core material preferably comprises (or consists of, or consists essentially of) a metal and/or an alloy. Metal and metal alloy may provide sufficient electrical conductivity to provide a high level electrical connection between components joined by the soldering material.

The core material preferably comprises (or consists of, or consists essentially of) one or more of: copper, silver, nickel, molybdenum, beryllium, cobalt, iron, copper- tungsten alloy, nickel-silver alloy, copper-zinc alloy and copper-nickel-zinc alloy, more preferably one or more of copper and silver. Such materials may provide a favourable combination of high electrical conductivity and high thermal conductivity.

The CTE of the core material will have an impact on the stress at the interfaces. This stress can be reduced by selecting an appropriate core material. For example, CTE of Nickel is 13 ppm/K while that of Copper in 17 ppm/K and CTE of CuW alloy depends on the composition and can be tailored to meet the device design needs.

The core material preferably has an electrical conductivity at 20 °C of at least 1 x 10 ⁵ S/m, more preferably at least 1 x 10 ⁶ S/m, more preferably at least 1 x 10 ⁷ S/m, even more preferably at least 4 x 10 ⁷ S/m, still even more preferably at least 5 x 10 ⁷ S/m. Such electrical conductivities may provide a high level of electrical connection between components joined by the soldering material.

The solder is preferably lead-free. This means that no lead is added intentionally. Thus, the lead content is zero or at no more than accidental impurity levels. Lead- free solder may be favourable in view of health concerns and regulatory requirements. The solder preferably comprises one or more of: In, Snln alloy (e.g. 5-58% Sn, 42- 95% In), SnBi alloy (e.g. 42-60% Sn, 40-58% Bi), Biln alloy (e.g. 5-67% Bi, 33-95% In), Agin alloy (e.g.1-5%Ag, 95-99% In, e.g. 3% Ag, 97% In), SnAg alloy (e.g. 90- 97.5% Sn, 2.5-10% Ag), SnCu alloy (e.g. 99.3-99.6% Sn, 0.4-0.7% Cu), InGa alloy (e.g. 99.3-99.5% In, 0.5-0.7% Ga), SnBiAgCu alloy (e.g. 50% Sn, 47% Bi, 1% Ag,

2% Cu), SnBiZn alloy (e.g. 65.5% Sn, 31.5% Bi, 3% Zn), SnlnAg alloy (e.g. 77.2% Sn, 20% In, 2.8% Ag), SnBiAgCuln alloy (e.g. 82.3% Sn, 2.2% Bi, 3% Ag, 0.5% Cu, 12% In), SnZn alloy (e.g. 91% Sn, 9% Zn), SnCulnGa alloy (e.g. 92.8% Sn, 0.7%Cu, 6% In, 0.5% Ga), SnCuAg alloy (e.g. 95.5% Sn, 3.8% Ag, 0.7% Cu), SnAgSb alloy (e.g. 95% Sn, 3.5% Ag, 1.5% Sb), SnSb alloy (e.g. 95% Sn, 5% Sb), Innolot alloy (Sn-Ag3.7Cu0.65Bi3.0Sb1 43Ni0.15) and SnCuSb alloy (e.g. 4-95% Sn, 1-2% Cu, 4% Sb). % values refer to % by weight. The alloys may comprise the recited elements together with any unavoidable impurities. Such alloys may be particularly suitable for connecting components of an electrical device.

In a preferred example, the core material comprises copper and the solder comprises Sn-20ln-2Ag alloy.

In a preferred embodiment, the thickness of the core layer is from 150 to 300 pm, the thickness of each solder layer is from greater than 50 to 100 pm, and the core material comprises one or more of copper and silver. In such an embodiment, the thickness of each solder layer is preferably from 55 to 100 pm. Such a solder material may be particularly capable of reducing stress caused by a mismatch in CTE values of the connected components without significantly reducing heat dissipation from the connected parts.

The core layer preferably comprises two or more core sublayers separated by one or more further solder layers, the two or more core sublayers formed of core material, the core material of one sublayer having a different coefficient of thermal expansion to the core material of another sublayer. This may result in the solder material having a different coefficient of thermal expansion at one side than the other. This may be beneficial when connecting components having different coefficients of thermal expansion, and may reduce the stress caused by the different coefficients of thermal expansion at high temperature. In such a case, the component with the higher coefficient of thermal expansion may be connected to the side of the solder material with the core sublayer having the higher coefficient of thermal expansion, and the component with the lower coefficient of thermal expansion connected to the side of the solder material with the core sublayer having the lower coefficient of thermal expansion.

The further solder layers comprise solder material. The solder material of the further solder layers may be the same as the solder material of the solder layers. Alternatively, the solder material of the further solder layers may be different from the solder material of the solder layers.

The core material of one core sublayer is preferably different from the core material of another core sublayer.

The solder material preferably comprises two sublayers. In a preferred embodiment of such an arrangement, the core material of one core sublayer preferably comprises copper and the core material of the other core sublayer preferably comprises nickel. Such metals may result in the solder material exhibiting a favourable change in coefficient of thermal expansion across its thickness.

The solder material preferably comprises three sublayers. In such a case, preferably the coefficients of thermal expansion of the core materials of the core sublayers increase across the thickness of the solder material, i.e. the direction perpendicular to the plane of the core layer. In a preferred embodiment of such an arrangement, the three sublayers comprise an inner sublayer and two outer sublayers, core material of one core sublayer comprises copper, the core material of another core sublayer comprises nickel and the core material of another core sublayer comprises copper-tungsten alloy. In another preferred embodiment, the core material of one core sublayer comprises silver, the core material of another core sublayer comprises nickel and the core material of another core sublayer comprises molybdenum. Such metals may result in the solder material exhibiting a favourable change in coefficient of thermal expansion across its thickness. The core sublayers may have different thicknesses or the core sublayers may have the same thicknesses. The core sublayers preferably have thicknesses of from 10 to 80 pm, more preferably from 20 to 60 pm, even more preferably from 25 to 50 pm.

The further solder layers may have the same thickness as the solder layers described above or may have different thicknesses from the solder layers described above.

In a preferred embodiment, the solder material is not in the form of a cuboid having a length, a width and a thickness, the thickness being perpendicular to the plane of the core layer, the length being 10 mm and the width being 10 mm; and/or the thickness of the core layer is not 0.2 mm, 0.3 mm or 0.4 mm; and/or the solder layers do not each have a thickness of 0.05 or 0.1 mm; and/or the solder material does not comprise Sn20%ln2%Ag; and/or the core material does not comprise copper.

In a more preferred embodiment, the solder material is not in the form of a cuboid having a length, a width and a thickness, the thickness being perpendicular to the plane of the core layer, the length being 10 mm and the width being 10 mm; the thickness of the core layer is not 0.2 mm, 0.3 mm or 0.4 mm; the solder layers do not each have a thickness of 0.05 or 0.1 mm; the solder material does not comprise Sn20%ln2%Ag; and the core material does not comprise copper.

The solder material is preferably in the form of a foil, a strip, a film, a ribbon or a preform, more preferably a preform. Such forms may be particularly suitable for connecting components of an electronic device and/or may exhibit favourable handling properties. In a preferred embodiment, the core is completely coated with the solder. In other words, the core is completely surrounded by solder and no portion of the core is exposed. In this case, no part of the core material is exposed to air or other operating environments. This design may be preferred for core materials that tend get oxidized when exposed to oxygen and/or humidity such as, for example, Cu or Ni.

In an alternative preferred embodiment, the core is coated with solder on only two opposing surfaces, typically the two largest opposing surfaces (major surfaces). This design may be relatively easy for high volume manufacturing as large size sheets or ribbons can be coated with the solder from which preform can cut by a high-speed stamping process.

The solder material preferably has an effective thermal conductivity of greater than 65 W/m.K, more preferably greater than 80 W/m.K, even more preferably greater than 100 W/m.K, still even more preferably greater than 130 W/m.K. By “effective thermal conductivity” it is meant the total thermal conductivity of the solder material, i.e. including both the solder (with lower thermal conductivity) and the core (with higher thermal conductivity). Such an effective thermal conductivity may improve the heat dissipation from the solder material.

The first aspect of the present invention relates to a solder material. The term “solder material” may be synonymous with the term “multilayered structure”. In addition, the term “solder layers” is synonymous with the term “two or more solder layers”. In addition, for the avoidance of doubt, the solder layers comprise solder material. The solder layers are typically outer layers.

Accordingly, the first aspect of the present invention is alternatively worded as a multilayered material for use in electronic assembly, the multilayered material comprising: two or more (e.g. outer) solder layers, each solder later comprising solder material; and a core layer comprising a core material, the core layer being sandwiched between the two or more solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder material.

In a further aspect, the present invention provides a multilayered structure for use in electronic assembly, the multilayered structure comprising: two outer solder layers, each outer solder later comprising solder material; and a core layer sandwiched between the two outer solder layers, wherein: the core layer comprises two outer core sublayers and optionally one or more central core sublayers: the two core sublayers, and central core layers if present, being separated from each other by one or more solder layers: the outer core sublayers and inner core sublayers comprise core material: the core material of one outer core sublayer has a different coefficient of thermal expansion than the core material of the other outer core sublayer: and the thermal conductivity of the core materials is greater than the thermal conductivity of the solder materials.

The advantages and preferable features of the first aspect apply equally to this aspect.

The core preferably comprises at least one central core sublayer and the coefficient of thermal expansion of the core materials of the outer and inner core sublayers increases across the thickness of the core. As discussed above in relation to the first aspect, this may be beneficial when connecting components having different coefficients of thermal expansion, and may reduce the stress caused by the different coefficients of thermal expansion at high temperature. In a further aspect, the present invention provides a solder joint comprising the solder material described herein or the multilayered structure described herein. For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. Such a joint may exhibit a favourable combination of low stress caused by CTE mismatch of the joined components and high heat dissipation. Accordingly, an electronic device containing such a joint may exhibit improved performance and reliability in comparison to conventional electronic devices. The thickness of the solder joint corresponds to the sum of the thickness of the core layer and the solder layers. Typically, the thickness does not change during reflow.

In a further aspect, the present invention provides an interconnect comprising the solder material described herein or the multilayered structure described herein. For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. Such an interconnection may exhibit a favourable combination of low stress caused by CTE mismatch of the joined components and high heat dissipation. Accordingly, an electronic device containing such an interconnection may exhibit improved performance and reliability in comparison to conventional electronic devices.

In a further aspect, the present invention provides an electronic device comprising the solder material, the multilayered structure, the solder joint or the interconnect described herein. For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. Such a device may exhibit improved performance and reliability in comparison to conventional electronic devices.

In a further aspect, the present invention provides an IGBT, MOSFET, LED or microprocessor comprising the solder material, or the multilayered structure, the solder joint or the interconnect described herein. For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. Such a device may exhibit improved performance and reliability in comparison to conventional electronic devices. In a further aspect, the present invention provides the use of the solder material described herein or the multilayered structure described herein in a soldering method selected from Surface Mount Technology (SMT) soldering, die attach soldering, thermal interface soldering, hand soldering, laser and RF induction soldering, and thermos-sonic soldering. For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. The solder materials and multilayered structures described herein are particularly suitable for such uses.

In a further aspect, the present invention provides the use of the solder material described herein or the multilayered structure described herein for die-attach (Level I), substrate attach (Level II) or package to heatsink attach (Level III). For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. The solder materials and multilayered structures described herein are particularly suitable for such uses.

In a further aspect, the present invention provides a method of forming a solder joint comprising: providing the solder material described herein or the multilayered structure described herein in the vicinity of two or more work pieces to be joined, and heating the solder material to form a soldered joint.

For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. The resulting joint may exhibit a favourable combination of low stress caused by CTE mismatch of the joined components and high heat dissipation. Accordingly, an electronic device containing such a joint may exhibit improved performance and reliability in comparison to conventional electronic devices.

The two or more work pieces to be joined preferably comprise: a device or die and a substrate, or a substrate and a printed circuit board (PCB), or a printed circuit board and a heatsink. Such work pieces are particularly suitable to be joined by the solder material, since they are required to have a high heat dissipation and it is beneficial for them to exhibit low stress resulting from CTE mismatch.

In a further aspect, the present invention provides a method of manufacturing the solder material described herein or the multilayered structure described herein, the method comprising: providing two of more layers of solder, providing a layer of core material, and laminating the layers of solder on either side of the layer of core material.

For the avoidance of doubt, the advantages and preferable features of the first aspect apply equally to this aspect. Depending on the solder and the core material, as well as the processing conditions, there is a reduction in the thickness of the structure after lamination. That reduction factor must be accounted for to achieve the target dimensions.

The layer of core material is preferably in the form of a ribbon and/or the layer of solder is in the form of a ribbon.

The ribbons are preferably provided by casting, extrusion or drawing.

The layers are preferably laminated in a co-drawing process, preferably a high- pressure co-drawing process.

The laminated layers are preferably diced and/or stamped.

In a further aspect, the present invention provides a method of manufacturing the solder material described herein or the multilayered structure described herein, the method comprising: providing a layer of core material, and coating the core material with solder. The surface of the layer of core material is preferably cleaned prior to it being coated with the solder. This may result in a stronger adhesion between the core and solder, thereby reducing the occurrence of delamination and the resulting loss of reliability of a device containing a joint formed using the solder material.

Coating the core material with solder preferably comprises contacting the core material with a molten solder bath, e.g. by immersing the core material in a molten solder bath.

Various process parameters, such as the solder bath temperature, ribbon speed though the bath etc. may be a varied to control the solder coating thickness.

The invention will now be described in relation to the following non-limiting drawings in which:

Figure 1 shows a schematic of the assembly of a typical electronic device.

Figure 2 shows cross-sectional schematics of alternative arrangements of the solder material according to the present invention.

Figure 3 shows a cross-sectional schematic of a solder material according to the present invention.

Figure 4 shows a cross-sectional schematic of a solder material according to the present invention.

Figure 5 shows a microscopy image of a cross section of a solder material according to the present invention.

Figure 2 shows cross-sectional views of two types of solder material according to the present invention. The solder materials comprise a core layer 9 sandwiched between solder layers 10. The solder material shown in the top picture has solder only at the top and at the bottom side. There is no solder on the sides. The other solder material has solder on all sides of the core.

Figures 3 and 4 shows cross-sectional views of two types of solder material according to the present invention. In the solder material of Figure 3, the core layer 9 comprises two core sublayers 11 separated by a further solder layer 12. The two core sublayers 11 are formed of core material. The core material of the top sublayer has a different coefficient of thermal expansion to the core material of the bottom sublayer. In a preferred embodiment, the core material of the top core sublayer is nickel and the core material of the bottom core sublayer is nickel. As a result, the CTE decreases from top to bottom. In the solder material of Figure 4, the core layer 9 comprises three core sublayers 11 separated by a further solder layer 12. The three core sublayers 11 are formed of core material. The core material of the top sublayer has a different coefficient of thermal expansion to the core material of the middle sublayer and the bottom sublayer. The coefficients of thermal expansion of the core materials of the core sublayers may increase or decrease across the thickness of the solder material. In a preferred embodiment, the core material of the top core sublayer is molybdenum, the core material of the middle core sublayer is nickel and the core material of the bottom core sublayer is silver. As a result, the CTE decreases from top to bottom. In another preferred embodiment, the core material of the top core sublayer is copper-tungsten alloy, the core material of the middle core sublayer is nickel and the core material of the bottom core sublayer is copper. As a result, the CTE increases from top to bottom.

The invention will now be described in relation to the following non-limiting examples.

Example 1

A solder material (preform) was prepared by a high-pressure lamination process. Figure 5 shows a microscopy image of a cross section of the preform. The central core is 300 pm thick and formed of copper. The solder on both sides is Sn20%ln2%Ag. The solder thickness varies from 50 to 100 pm. The effective thermal conductivity of this sample is about 130 W/m.K, measured by a nano-flash transient measurement technique. Example 2

A number of preforms were prepared in a similar manner to Example 1 but with varying thicknesses of the core (Keff = 400 W/m.K) and solder layers (Keff = 54 W/m.K). The thermal performance of the preforms was evaluated. Table 1 shows estimated thermal resistances and equivalent thermal conductivities. The thermal resistance of the hick interfaces is much lower (equivalent Keff is much higher) as compared to solder alone.

Table 2: Selected examples of Cu-core preforms with their estimated thermal resistance and equivalent thermal conductivity.

The invention will now be further described with reference to the following numbered clauses:

1. A solder material comprising: a core comprising a core material; and solder at least partially coating the core.

2. The solder material of clause 1 for use in electronic assembly. 3. The solder material of clause 1 or clause 2, wherein the core is in the form of a layer.

4. The solder material of clause 3, wherein the thickness of the core layer is from 100 to 500 pm, preferably from 200 to 400 pm, more preferably from 150 to 300 pm.

5. The solder material of clause 3 or clause 4, wherein solder is in the form of layers, and wherein the core is sandwiched between two solder layers.

6. The solder material of clause 6, wherein the thickness of the solder layer is from 25 to 150 pm, preferably from 50 to 100 pm.

7. The solder material of any preceding clause in the form of a foil, a strip, a film, a ribbon or a preform.

8. The solder material of any preceding clause, wherein the melting point of the core material is greater than the reflow temperature of the solder.

9. The solder material of any preceding clause, wherein the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

10. The solder material of clause 9, wherein the core material has a thermal conductivity of greater than or equal to 65 W/m.K, preferably greater than 65 w/m.K, more preferably greater than 70 W/m.k, even more preferably greater than 75 W/m.K.

11. The solder material of any preceding clause, wherein the core material comprises a metal and/or an alloy.

12. The solder material of any preceding clause, wherein the core material comprises one or more of: copper, silver, nickel, molybdenum, beryllium, cobalt, iron, copper-tungsten alloy, nickel-silver alloy, copper-zinc alloy and copper-nickel-zinc alloy. 13. The solder material of any preceding clause, wherein the solder is lead-free.

14. The solder material of any preceding clause, wherein the solder comprises one or more of: In, Snln alloy (e.g. 5-58% Sn, 42-95% In), SnBi alloy (e.g. 42-60% Sn, 40-58% Bi), Biln alloy (e.g. 5-67% Bi, 33-95% In), Agin alloy (e.g. 3% Ag, 97% In), SnAg alloy (e.g. 90-97.5% Sn, 2.5-10% Ag), SnCu alloy (e.g. 99.3-99.6% Sn, 0.4-0.7% Cu), InGa alloy (e.g. 99.3-99.5% In, 0.5-0.7% Ga), SnBiAgCu alloy (e.g. 50% Sn, 47% Bi, 1% Ag, 2% Cu), SnBiZn alloy (e.g. 65.5% Sn, 31.5% Bi, 3% Zn), SnlnAg alloy (e.g. 77.2% Sn, 20% In, 2.8% Ag), SnBiAgCuln alloy (e.g. 82.3% Sn, 2.2% Bi, 3% Ag, 0.5% Cu, 12% In), SnZn alloy (e.g. 91% Sn, 9% Zn), SnCulnGa alloy (e.g. 92.8% Sn, 0.7%Cu, 6% In, 0.5% Ga), SnCuAg alloy (e.g. 95.5% Sn, 3.8% Ag, 0.7% Cu), SnAgSb alloy (e.g. 95% Sn, 3.5% Ag, 1.5% Sb) and SnCuSb alloy (e.g. 4-95% Sn, 1-2% Cu, 4% Sb).

15. The solder material of any preceding clause, wherein the core material comprises copper and the solder comprises Sn-20ln-2Ag alloy.

16. The solder material of any preceding clause, wherein the core and the solder are in the form of layers, and wherein the solder layers are coated on either side of the core layer.

17. The solder material of clause 16, wherein the thickness of the core layer is from 100 to 500 pm, preferably from 200 to 400 pm, more preferably from 150 to 300 pm.

18. The solder material of clause 16 or clause 17, wherein the thickness of the solder layer is from 25 to 150 pm, preferably from 50 to 100 pm.

19. The solder material of any preceding clause, wherein the core is completely coated with the solder. 20. The solder material of any preceding clause having an effective thermal conductivity of greater than 65 W/m.K, preferably greater than 80 W/m.K, more preferably greater than 100 W/m.K, even more preferably greater than 130 W/m.K.

21. Use of the solder material of any preceding clause in a soldering method selected from Surface Mount Technology (SMT) soldering, die attach soldering, thermal interface soldering, hand soldering, laser and RF induction soldering, and thermos-sonic soldering.

22. Use of the solder material of any of clauses 1 to 20 for die-attach (Level I), substrate attach (Level II) or package to heatsink attach (Level III).

23. An interconnect comprising the solder material of any of clauses 1 to 20.

24. An IGBT, MOSFET, LED or microprocessor comprising the solder material of any of clauses 1 to 20, or the interconnect of clause 23.

25. A method of forming a solder joint comprising: providing the solder material of any of clauses 1 to 20 in the vicinity of two or more work pieces to be joined, and heating the solder material to form a soldered joint.

26. A method of manufacturing the solder material of any of clauses 1 to 20, the method comprising: providing two of more layers of solder, providing a layer of core material, and laminating the layers of solder on either side of the layer of core material.

27. The method of clause 26, wherein the layer of core material is in the form of a ribbon and/or the layer of solder is in the form of a ribbon.

28. The method of clause 27, wherein the ribbons are provided by casting, extrusion or drawing. 29. The method of any of clauses 26 to 28, wherein the layers are laminated in a co-drawing process, preferably a high-pressure co-drawing process.

30. The method of any of clauses 26 to 29, wherein the laminated layers are diced and/or stamped.

31. A method of manufacturing the solder material of any of clauses 1 to 20, the method comprising: providing a layer of core material, and coating the core material with solder.

32. The method of clause 31 , wherein surface of the layer of core material is cleaned prior to it being coated with the solder.

33. The method of clause 31 or clause 33, wherein coating the core material with solder comprises passing the core material through a molten solder bath.

34. The solder material of any of clauses 1 to 20 in the form of a preform.

35. The solder material of clause 34 wherein the preform provides increasing CTE from top to bottom to reduce the stresses at the interfaces of the adjoining materials with solder.

36. The solder material of clause 34 wherein the preform provides decreasing CTE from top to bottom to reduce the stresses at the interfaces of the adjoining materials with solder.

37. The solder material of any of clauses 34 to 36, wherein the preform can be used for level I, Level II or Level III interconnects. 38. The solder material of any of clauses 34 to 37, wherein the preform can be used for packaging and assembly of IGBT, MOSFET, LED, Microprocessor and other electronic devices.

39. The solder material of any of clauses 34 to 38, wherein the preform can be used in assembly of multi-chip modules with difference size of components and components with different heat generation rates.

40. The solder material of any of clauses 34 to 39, wherein the preforms can be used in assembly of multi-chip modules with difference thickness of components and preform thickness is selected to adjust for component thickness.

The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations in the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art and remain within the scope of the appended claims and their equivalents.