Title:
ENHANCED INSTRUCTION DECODING
Document Type and Number:
WIPO Patent Application WO1999028818
Kind Code:
A3
Abstract:
When decoding instructions of a program to be executed in a central processing unit (9) comprising pipelining facilities for fast instruction decoding, part of the decoding is executed or the decoding in pipelining units is prepared in a remapping unit (5) during loading a program into a program or primary memory (7) used by the central processor, the remapping or predecoding operation resulting in operation codes which can be very rapidly interpreted by the pipelining units of the central processor. Thus, the operation code field of an instruction is changed to include information on e.g. instruction length, jumps, parameters, etc., this information indicating the instruction length, whether it is a jump instruction or has a parameter etc. respectively, in a direct way that allows the use of simple combinatorial circuits in the pipelining units. This makes it possible to obtain a decoding of complex instructions using few clock cycles, and also that old type instructions can be used as input to the system without degrading the time performance of the instruction decoding. Also, accesses of the program memory (7) and a data memory (11) can be made earlier during execution of a program, which saves execution time.
Inventors:
HALVARSSON DAN (SE)
JONSSON TOMAS (SE)
HOLMBERG PER (SE)
JONSSON TOMAS (SE)
HOLMBERG PER (SE)
Application Number:
PCT/SE1998/002210
Publication Date:
September 16, 1999
Filing Date:
December 02, 1998
Export Citation:
Assignee:
ERICSSON TELEFON AB L M (SE)
HALVARSSON DAN (SE)
JONSSON TOMAS (SE)
HOLMBERG PER (SE)
HALVARSSON DAN (SE)
JONSSON TOMAS (SE)
HOLMBERG PER (SE)
International Classes:
G06F9/38; (IPC1-7): G06F9/30
Domestic Patent References:
| WO1997024659A1 | 1997-07-10 | |||
| WO1997048041A1 | 1997-12-18 |
Other References:
THE 14TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, June 1987, (Pittsburgh, Pennsylvania), DAVID R. DITZEL et al., "The Hardware Architecture of the CRISP Microprocessor", pages 309-319.
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