BACKGROUND OF THE INVENTION

1. Field of the Invention:

[0001] The present invention relates to gate drivers and, more particularly, to an integrated circuit for driving low-side enhancement mode Gallium Nitride (GaN) FETs.

2. Description of the Related Art:

[0002] High power GaN transistors have recently been introduced as a replacement for silicon based transistors. GaN offers superior performance over silicon-based devices due to the high electron mobility and high breakdown field of gallium nitride, resulting in low on-resi stance, fast switching and higher operating temperatures. Normally-off enhancement mode GaN transistors are preferred as they are fast (majority carriers, unlike depletion mode), have no reverse recovery (QRR) and consume less power than depletion mode devices.

[0003] Gate drivers for enhancement mode GaN transistors are available from Texas Instruments, such as the LM5114 Low-Side Gate Driver. However, the LM5114 itself is made on a silicon process that is not compatible with GaN. This prevents monolithic integration of the enhancement mode GaN transistor to be driven. The two chip solution does not allow the lowest possible gate loop circuit inductance, and therefore cannot compete with the performance of a fully monolithically integrated solution. A gate driver integrated with the enhancement mode GaN transistor will necessarily have a much lower propagation delay, will consume less power, and will allow a very short on-time duration.

[0004] U.S. Patent No. 9,525,413 proposes an integrated solution, i.e., an enhancement mode GaN transistor with a monolithically integrated GaN driver comprising two smaller enhancement mode GaN transistors in a half bridge configuration. The high side GaN transistor of the half bridge provides the gate drive voltage to the gate of the GaN transistor, and the low side GaN transistor clamps the gate of the GaN switch to the source. This solution requires a discrete dual voltage pre-driver. For the reasons mentioned above, it would be advantageous to integrate the enhancement mode GaN transistor with a complete gate driver in a single integrated package.

[0005] In particular, it would be desirable to provide a fully integrated GaN driver that can operate from a single 5 V supply, has low power consumption, with no severe limitations on duty cycle and frequency, has fast transitions, low propagation time, and has a pull-up and pulldown resistance matched to the FET it drives, and includes UVLO circuitry.

SUMMARY OF THE INVENTION

[0006] The present invention achieves the above-noted goals by providing a fully integrated GaN driver with the above-noted features that can support pulses down to 10 ns. Such a low pulse capability opens the door to very high frequency converters >10 MHz and also high step down ratio converters such as 48 V to 1 V or less.

[0007] More specifically, the present invention provides a fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package or chip.

[0008] The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.

[0009] The fully integrated GaN gate driver of the present invention also includes a novel low voltage "level shifter" and "current amplifier." The input is a ground reference 0-5 V digital signal, and the output is a 0-10 V digital signal. This signal is useful for the inverted output drive stage discussed above.

[0010] Other features and advantages of the present invention will become apparent to those skilled in the art when the following description is read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a schematic of a preferred embodiment of the digital logic signal inverter of the present invention.

[0012] FIG. 2 is a schematic diagram of a preferred embodiment of the level shifter of the present invention.

[0013] FIG. 3 is the output buffer stage of the gate driver.

[0014] FIG. 4 is an implementation of a two input NA D logic.

[0015] FIG. 5 is an implementation of a two input NOR logic.

[0016] FIG. 6 is an implementation of a two input OR Logic.

[0017] FIG. 7 is an implementation of a two input AND logic.

[0018] FIG. 8 is the circuit of the complete standalone gate driver.

[0019] FIG. 9 is the circuit of the complete gate driver in which the main FET to be driven is integrated with the driver.

[0020] FIG. 10 shows a basic voltage reference circuit which incorporates only N-type, enhancement-mode GaN FETs.

[0021] FIG. 11 shows the basic Under Voltage LockOut (UVLO) circuit of the present invention.

[0022] FIG. 12 shows the gate driver of the present invention including the above- described ULVO circuity, integrated with the main FET.

[0023] FIG. 13 shows the main gate driver of the present invention (without UVLO) including synchronous bootstrap supply FET circuitry. [0024] FIG. 14 shows the complete gate driver of the present invention, incorporating all of the previously described features, including UVLO, integrated synchronous bootstrap FET, the main driver, and the main FET.

[0025] FIG. 15 shows an alternate embodiment of the comparator/UVLO circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMB ODFMENT S

[0026] In the following detailed description, reference is made to exemplary

embodiments of the present invention. The exemplary embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other

embodiments may be employed and that various structural, logical, and electrical changes may be made.

[0027] The basic building blocks of a gate driver are a logic inverter, a signal level shifter, and an output drive stage. An undervoltage lockout (UVLO) circuit is also desirable to shut down the gate driver if the source voltage drops below a predetermined threshold value.

[0028] FIG. 1 is a schematic of a preferred embodiment of the digital logic signal inverter of the present invention. In GaN, the supply voltage is 5 V, so a logic high is 5 V and a logic low is 0 V. The inverter of the present invention is similar to standard NMOS logic inverters with some notable exceptions: (a) transistor 4 (Q2; WG = 10 μπι) is an enhancement mode GaN transistor, not a depletion mode device as is typical in NMOS, (b) because no depletion mode device is used, transistor 2 (Ql; WG = 20 μπι), also an enhancement mode GaN transistor, is added to charge the gate of transistor 4 (Q2), thereby keeping it on. Transistor 6 (Q3; WG = 120 μπι) is also an enhancement mode GaN transistor - the on-resistance of transistor 6 (Q3) is six times lower than the on-resistance of Q2. [0029] The logic inverter of the present invention works by using transistor 2 (Ql) as a bootstrap diode (gate shorted to source) with CGS of transistor 4 (Q2), which makes for faster transitions. The diode charges the gate of transistor 4 (Q2) (CGS) and capacitor 8 (C4 = 0.2 pF) to nearly 5 V when transistor 6 (Q3) is on, i.e. input (Ain) logic of 1 (5V), and thus transistor 4 (Q2) is always on and conducting current. This allows fast voltage rise. Transistor 4 (Q2) dissipates most of the power on the IC. Since the drain of transistor 6 (Q3) is also connected to the output ( Y ), the output will be near 0 V thus inverting the input. In this mode, transistor 6 (Q3), being a large FET, pulls transistor 4 (Q2) out of saturation and thus has a current flowing through it. This current is needed when the input signal changes to 0 V to pull the output high, again inverting the logic input. The capacitor 8 (C4) is used for extra storage above that provided by CGS of transistor 4 (Q2), thus increasing the time the circuit can "hold" a logic high output. The primary advantage of the logic inverter of the present invention is that only N-type, enhancement-mode only FETs are used.

[0030] FIG. 2 is a schematic diagram of a preferred embodiment of the level shifter of the present invention. The main function of the level shifter to increase the voltage magnitude of the input (Ain) by a factor of two for the logic high only. A logic low input of 0 V remains 0 V. This circuit uses two inputs where the second is simply an inverted version of Ain. This can be done using the inverter described previously.

[0031] The level shifter of the present invention works in essentially the same manner as the inverter circuit plus a few modifications. It comprises two stages: (1) a supply voltage level shifter transistors 10 (Q4) and 12 (Q5); and (2) an inverter and high voltage buffer stage made up of transistors 14 (Q6), 16 (Q7) and 18 (Q8). The second stage works in the same manner as the logic inverter except its supply voltage is 10 V, not 5 V (drain of transistor 16 (Q7)) when the output is high (Yout) and 5 V when the output is low (where it operates exactly the same as the inverter). The first stage works as a bootstrap supply where the voltage across capacitor 20 (CI = 5 pF) level shifts the inverted input signal from between 0 V and 5 V to between 5 V and 10 V. Transistor 10 (Q4) acts as diode in this case allowing transistor 12 (Q5) to switch with 0 V (off) and 5 V (on) across its gate. Capacitor 22 (C2 = 50 pF) is charged when Ain is low, which is also when transistor 12 (Q5) is turned on through CI . Transistors 10 (Q4; WG = 10 μιη), 12 (Q5; WG = 50 μιη), 14 (Q6; WG = 10 μιη), 16 (Q7; WG = 10 μιη) and 18 (Q8; WG = 60 μιη) are each preferably enhancement mode GaN transistors. The gate widths provided herein are exemplary only - it is the ratios between them that are important. Capacitor 24 (C5) is 2 pF.

[0032] FIG. 3 is the output buffer stage of the gate driver. It uses two complimentary inputs (Ain and A _jn ). Note that the output drive circuitry includes a high side enhancement mode

GaN FET 26 (Q9) (WG = 1.2 mm), Q5, that is inverted compared to the low side enhancement mode GaN FET 28 (Q10) (WG = 1.2 mm). The inverted high side GaN FET 26 (Q9) allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.

[0033] More specifically, when the logic input Ain is low (0 V) and A _jn i _s high (5 V), transistor 28 (Q10) is turned on thus making the output (Yout) low (0 V). Also, the upper FET gate of transistor 26 (Q9) becomes highly reverse biased (a unique feature of GaN FETs that increases the "body diode" voltage), such that it cannot conduct despite being installed in reverse (drain and source). When the logic input A _in is high (10 V) from the level shifter stage and T is low, transistor 26 (Q9) is turned on and transistor 28 (Q10) is off. This stage significantly increases the current sink or source capability of the driver.

[0034] FIG. 4 is an implementation of a two input NAND logic. It is based on the logic inverter described earlier, with one minor exception. The input FET is divided into two for the two inputs and their connections cascaded. This requires both FETs 6 and 32 (Q3 and Q4) to be ON before it can conduct and change the state of transistor 4 (Q2) and hence the output, thus yielding a NAND gate. Transistors 2 (Ql; WG = 10 μιη), 4 (Q2; WG = 20 μιη), 6 (Q3; WG = 120 μιη) and 32 (Q4; WG = 120 μπι) are all enhancement mode GaN transistors. Transistor 2 (Ql) is used as a diode to charge capacitor 8 (C4) when both transistors 6 and 32 (Q3 and Q4) are turned on. This prevents capacitor 8 (C4) from properly charging when either of transistors 6 and 32 (Q3 and Q4) is held off and would severely degrade the performance of the output. Transistors 31 (Q8; WG = 10 μπι), 33 (Q9) and capacitor 35 (C7) correct this problem. The circuit works by allowing capacitor 35 (C7) to charge when transistor 32 (Q4) is on and transistor 8 (Q3) is off. When transistor 32 (Q3) is turned on, capacitor 35 (C7) can charge capacitor 8 (C4) via transistor 33 (Q9; WG = 10 μιη), thus restoring operation to the circuit.

[0035] FIG. 5 is an implementation of a two input NOR logic. It is based on the logic inverter of FIG. 1 described earlier with one minor exception. The input FET is divided into two for the two inputs and their connections are paralleled. This requires either of the two FETs 6 and 32 (Q3 & Q4) to be ON to change the state of Q2 and hence the output, thus yielding a NOR gate.

[0036] FIG. 6 is an implementation of a two input OR Logic. It is based on the NOR logic of FIG. 5, with an inverter stage added on the end to change the polarity. Transistors 34 (Q5; WG = 10 μιη), 36 (Q6; WG = 20 μιη), and 38 (Q7; WG = 120 μιη) are analogous to transistors 2 (Ql), 4 (Q2) and 6 (Q3), and are all enhancement GaN transistors.

[0037] FIG. 7 is an implementation of a two input AND logic. It is based on the NAND logic of FIG. 4, with an inverter stage added on the end to change the polarity.

[0038] FIG. 8 is the circuit of the complete gate driver. It comprises the three stages described earlier: (1) Inverter (FIG. 1), (2) Level shifter (FIG. 2), and (3) output buffer (FIG. 3).

Also, the output stage is opened to yield YoutH and YoutL. This allows external programming of gate resistors for the driver to independently change the turn on and off characteristics of the FET being driven, thus improving matching for smaller FETs (being driven).

[0039] FIG. 9 is the circuit of the complete gate driver in which the main FET to be driven is integrated with the driver. It is the same design as the complete driver of FIG. 8, except that the output stage is connected to the main FET (Q100; WG = 300 mm). This eliminates external programming of the FET voltage as the driver has already been optimized to the FET it drives.

[0040] As mentioned previously, it is desirable to provide the gate driver with an undervoltage lockout (UVLO) circuit. The UVLO circuit of the present invention comprises two voltage reference circuits and a comparator. One of the voltage reference circuits compares a predetermined voltage against the measured supply voltage, and the other voltage reference circuit is used for the constant current source of the comparator.

[0041] FIG. 10 shows the basic voltage reference circuit, which incorporates only N- type, enhancement-mode GaN FETs. The reference comprises transistor 46 (Q27; WG = 10 μιη), resistor 44 (R27 = 160 kQ, the current set resistance) and transistor 48 (Q28 WG = 10 μιη). With the gate of transistor 48 (Q28) connected to its drain, transistor 48 (Q28) becomes a limited voltage reference when sinking a current. Any attempt to increase the voltage above the threshold of the FET results in an increase in sink current by transistor 48 (Q28). Transistors 46 (Q27) and 48 (Q28) are preferably EPC25V Scalable enhancement mode GaN transistors with a gate width of 10 μιη.

[0042] FIG. 11 shows the basic Under Voltage LockOut (UVLO) circuit of the present invention. The purpose of the UVLO circuit is to lockout/prevent operation of another circuit if the supply voltage is below a pre-determined value. Once the pre-determined supply voltage is reached, the UVLO circuit releases the other circuit (in this case, the gate driver circuit) for operation. This prevents the GaN FETs of the gate driver from being operated below their threshold voltage in many power switching applications. The UVLO circuit comprises three parts: (1) a voltage reference (pre-determined voltage) to be compared against the measured supply voltage, (2) a voltage reference used for the constant current source of the comparator, (3) a comparator stage. The two voltage reference circuits are the same as discussed previously and shown in FIG. 10. One reference is used as a fixed reference for comparison to the supply voltage by the comparator and the second reference is used as a fixed reference to generate the current mirror in the comparator. The comparator is the classic current mirror type. Transistor 58 (Q26) in the comparator is used to add hysteresis to the circuit that prevents oscillation. The UVLO output is set by transistor 52 (Q25) as a digital logic signal. Transistors 50 (Q22), 52 (Q25), 54 (Q24), 56 (Q23) and 58 (Q26) are all preferably EPC25V Scalable enhancement mode GaN transistors with gate width of 10 μπι.

[0043] FIG. 12 shows the complete standalone gate driver of the present invention including the above-described ULVO circuity, integrated with the main FET. The main FET in FIG. 12 is an EPC2019 enhancement mode GaN FET or equivalent - the circuit described herein has been optimized to drive this type of FET. However, the gate drive circuit of the present invention can obviously be integrated with (and optimized for driving) other main FETs.

[0044] FIG. 13 shows a version of the basic gate driver (without UVLO) that includes a gate driver and an FET 60 (Q19) for a synchronous bootstrap supply. The synchronous bootstrap supply FET voltage rating should be at least 5 V higher than the main FET as the HB node includes a charge voltage for the bootstrap supply of 5 V.

[0045] The synchronous bootstrap FET supply gate driver circuit 62 of FIG. 13 is nearly identical to the main FET gate driver circuit 64, except it does not require the final output buffer stage. The main reasons for this are: (1) The synchronous bootstrap FET requires a +5 V and -5 V across the gate which is produced by the +10 V and 0 V output of the low voltage level shifter; and (2) the synchronous bootstrap FET is very small so it does not require significant current o drive. The 5 V offset is provided by the source of the synchronous bootstrap FET source being connected to the 5 V supply. This solution does not require an external circuit typical of the classic

enhancement mode GaN FET synchronous bootstrap supply (see, e.g., U.S. Patent Application Publication No. 2016/0105173), as the timing and level shifting are taken care of internally.

[0046] Timing for the gate driver of FIG. 13 is achieved in two stages: (1) Turn on must be delayed from the main FET being turned on to allow the main FET to fully enhance. This is achieved using the main FET gate signal as the signal source for the synchronous bootstrap FET gate driver; and (2) Turn off must be together or sooner that the main FET. This is achieved by using the initial inverted signal of the main gate driver to drive transistor Q18 directly, thus bypassing the synchronous bootstrap FET driver. This signal effectively arrives on the synchronous bootstrap FET before it reaches the main FET.

[0047] FIG. 14 shows the complete gate driver of the present invention, incorporating all of the previously described features, including UVLO, integrated synchronous bootstrap FET, the main driver, and the main FET. [0048] FIG. 15 shows an alternate embodiment of the comparator/UVLO circuit. In the embodiment of FIG. 11, resistors are used for loads. In the GaN process, resistors occupy a lot a room physically on the die and come with large tolerance variations (-20%), all undesirable characteristics. In the embodiment of FIG. 15, many of the resistors are replaced with enhancement mode GaN FETs, where the gate is tied to the drain, making the enhancement mode GaN FETs nonlinear resistors. The tolerances between the GaN FETs are significantly tighter and they also take up significantly less area on the die. In FIG. 15, the FET loads are used for the voltage sense for the UVLO as well as loads for the current mirror circuit.

[0049] The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.