[0001] This application claims benefit of priority to U.S. Provisional Patent Application No. 62/368,930, filed July 29, 2016, and U.S. Patent Application No. 15/643,124, filed July 6, 2017, both of which are expressly incorporated herein by reference in their entirety.

TECHNICAL FIELD

[0002] Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to amplification systems.

BACKGROUND

[0003] Wireless communication networks are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. Such networks, which are usually multiple access networks, support communications for multiple users by sharing the available network resources. For example, one network may be a 3G (the third generation of mobile phone standards and technology), 4G, 5G, or later system, which may provide network service via any one of various radio access technologies (RATs) including EVDO (Evolution-Data Optimized), lxRTT (1 times Radio Transmission Technology, or simply lx), W-CDMA (Wideband Code Division Multiple Access), UMTS-TDD (Universal Mobile Telecommunications System - Time Division Duplexing), HSPA (High Speed Packet Access), GPRS (General Packet Radio Service), or EDGE (Enhanced Data rates for Global Evolution). Such multiple access networks may also include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier FDMA (SC-FDMA) networks, 3 ^rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) networks, and Long Term Evolution Advanced (LTE-A) networks. Other examples of wireless communication networks may include WiFi (in accordance with IEEE 802 11), WiMAX (in accordance with IEEE 802.16), and Bluetooth® networks. [0004] A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station.

[0005] Amplifiers (e.g., transimpedance amplifiers, inverting amplifiers, etc.) may be used in a variety of systems (which may be referred to as amplification systems) to increase the power of an input signal, including for wireless communication systems. For example, amplifiers may be used in radio frequency (RF) systems, to increase the power of a signal for transmission, or increase the power of a received signal.

[0006] Such RF systems may implement envelope tracking, in which the power supply voltage to the amplifier is adjusted so as to roughly track the envelope of a signal for transmission.

SUMMARY

[0007] Certain aspects of the present disclosure provide an envelope tracking power supply. The envelope tracking power supply may include a linear amplifier having an output coupled to a voltage supply node of an amplifier, wherein a power supply node of the linear amplifier is coupled to a first voltage supply node, a switch mode power supply (SMPS) having an output coupled to the voltage supply node of the amplifier, and a circuit having a first switch coupled to the first voltage supply node and a second switch coupled to a second voltage supply node, wherein the power supply node of the SMPS is coupled to the first switch and the second switch.

[0008] Certain aspects of the present disclosure provide a method for generating a power supply voltage. The method generally includes generating, via a linear amplifier the power supply voltage at a power supply node of an amplifier based on an envelope of an input signal to the amplifier and a voltage at a first voltage supply node, selecting the first voltage supply node or a second voltage supply node based on the envelop of the input signal, and supplying, via a switch mode power supply (SMPS), a current to the power supply node from the first voltage supply node or the second voltage supply node based on the selection.

[0009] Certain aspects of the present disclosure generally includes an apparatus for generating a power supply voltage. The apparatus generally includes a linear regulator configured to generate the power supply voltage at a power supply node of a means for amplifying based on an envelope of an input signal to the means for amplifying and a voltage at a first voltage supply node, means for selecting the first voltage supply node or a second voltage supply node based on the envelop of the input signal, and a switch mode power supply configured to supply a current to the power supply node from the first voltage supply node or the second voltage supply node based on the selection.

[0010] Certain aspects of the present disclosure provide an envelope tracking power supply. The envelope tracking power supply generally includes one or more switches coupled to a battery voltage and a boosted voltage, a switching mode power supply coupled to the switches and to an amplifier, and a linear amplifier coupled to the boosted voltage and the amplifier.

[0011] Certain aspects of the present disclosure provide an apparatus The apparatus generally includes a selection circuit configured to selectively output a battery voltage and a boosted voltage, a switch mode power supply coupled to the output of the selection circuit and to a power amplifier, and a linear amplifier coupled to the boosted voltage and to the power amplifier The apparatus may further include an inductor coupled between the switch mode power supply and the power amplifier. The switch mode power supply may be configured as a buck converter The apparatus may further include an envelope detector coupled to an input of the linear amplifier. The selection circuit may include a first switch coupled between the battery voltage and an output of the selection circuit, and a second switch coupled between the boosted voltage and the output of the selection circuit. The selection circuit may further include a demultiplexer coupled between gates of the first switch and the second switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

[0013] FIG. 1 is a diagram of an example wireless communications network, in accordance with certain aspects of the present disclosure.

[0014] FIG. 2 is a block diagram of an example access point (AP) and example user terminals, in accordance with certain aspects of the present disclosure.

[0015] FIG. 3 is a block diagram of an example transceiver front end, in accordance with certain aspects of the present disclosure.

[0016] FIG. 4 illustrates an example envelope tracking amplification system.

[0017] FIG. 5 illustrates an example envelope tracking power supply.

[0018] FIG. 6 illustrates a graph of currents generated by the envelope tracking power supply of FIG. 5.

[0019] FIG. 7 illustrates an example envelope tracking power supply, in accordance with certain aspects of the present disclosure.

[0020] FIG. 8 illustrates a graph of currents generated by the envelope tracking power supply of FIG. 7, in accordance with certain aspects of the present disclosure.

[0021] FIG. 9 illustrates example operations for generating a power supply voltage, in accordance with certain aspects of the present disclosure.

DETAILED DESCRIPTION

[0022] Various aspects of the present disclosure are described below. It should be apparent that the teachings herein may be embodied in a wide variety of forms and that any specific structure, function, or both being disclosed herein is merely representative. Based on the teachings herein, one skilled in the art should appreciate that an aspect disclosed herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, such an apparatus may be implemented or such a method may be practiced using other structure, functionality, or structure and functionality in addition to or other than one or more of the aspects set forth herein. Furthermore, an aspect may comprise at least one element of a claim.

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] The techniques described herein may be used in combination with various wireless technologies such as Code Division Multiple Access (CDMA), Orthogonal Frequency Division Multiplexing (OFDM), Time Division Multiple Access (TDMA), Spatial Division Multiple Access (SDMA), Single Carrier Frequency Division Multiple Access (SC-FDMA), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), and so on. Multiple user terminals can concurrently transmit/receive data via different (1) orthogonal code channels for CDMA, (2) time slots for TDMA, or (3) sub-bands for OFDM. A CDMA system may implement IS-2000, IS-95, IS-856, Wideband-CDMA (W-CDMA), or some other standards. An OFDM system may implement Institute of Electrical and Electronics Engineers (IEEE) 802.11, IEEE 802.16, Long Term Evolution (LTE) (e.g., in TDD and/or FDD modes), or some other standards A TDMA system may implement Global System for Mobile Communications (GSM) or some other standards. These various standards are known in the art.

AN EXAMPLE WIRELESS SYSTEM

[0025] FIG. 1 illustrates a wireless communications system 100 with access points 110 and user terminals 120. For simplicity, only one access point 110 is shown in FIG. 1. An access point (AP) is generally a fixed station that communicates with the user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, user equipment (UE), a station (STA), a client, a wireless device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0026] Access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access point to the user terminals, and the uplink (i.e., reverse link) is the communication link from the user terminals to the access point. A user terminal may also communicate peer-to-peer with another user terminal. A system controller 130 couples to and provides coordination and control for the access points.

[0027] System 100 employs multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. Access point 110 may be equipped with a number N^ of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set N _u of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., N _ut ≥ 1). The N _u selected user terminals can have the same or different number of antennas.

[0028] Wireless system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. System 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., in order to keep costs down) or multiple antennas (e.g., where the additional cost can be supported). [0029] The access point 110 and/or user terminal 120 may include one or more amplifiers to amplify signals. At least one of the amplifiers may be designed in accordance with certain aspects of the present disclosure.

[0030] FIG. 2 shows a block diagram of access point 110 and two user terminals 120m and 120x in wireless system 100. In some embodiments, the access point 1 10 is instead implemented as a base station and/or one or more of the user terminals 120 are instead implemented as a mobile station. Access point 1 10 is equipped with N _ap antennas 224a through 224ap. User terminal 120m is equipped with N _ut antennas 252ma through 252mu, and user terminal 120x is equipped with N _{ut X} antennas 252xa through 2 2xu. Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operated apparatus or device capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript "dn" denotes the downlink, the subscript "up" denotes the uplink, N _up user terminals may be selected for simultaneous transmission on the uplink, N _¾ user terminals may be selected for simultaneous transmission on the downlink, N _up may or may not be equal to N _< j _¾ , and N _up and N _<¾ may be static values or can change for each scheduling interval. Beam-steering or some other spatial processing technique may be used at the access point, base station, mobile station, and/or user terminal.

[0031] On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 processes (e.g., encodes, interleaves, and modulates) the traffic data {d _up } for the user terminal based on the coding and modulation schemes associated with the rate selected for the user terminal and provides a data symbol stream {s _up }fox one of the N _ut<m antennas. A transceiver/front end (TX RX) 254 (also known as a radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) a respective symbol stream to generate an uplink signal. The transceiver/front end 254 may also route the uplink signal to one of the N _ut<m antennas for transmit diversity via an RF switch, for example. The controller 280 may control the routing within the transceiver/front end 254. Memory 282 may store data and program codes for the user terminal 120 and may interface with the controller 280.

[0032] A number N _up of user terminals 120 may be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.

[0033] At access point 110, N _ap antennas 224a through 224ap receive the uplink signals from all N _up user terminals transmitting on the uplink. For receive diversity, a transceiver/front end 222 may select signals received from one of the antennas 224 for processing. The signals received from multiple antennas 224 may be combined for enhanced receive diversity. The access point' s transceiver/front end 222 also performs processing complementary to that performed by the user terminal' s transceiver/front end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimate of a data symbol stream {s _up } transmitted by a user terminal. An RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and/or a controller 230 for further processing.

[0034] The transceiver front end (TX/RX) 222 of access point 110 and/or transceiver/front end 254 of user terminal 120 may include one or more amplifiers to amplify signals. At least one of the amplifiers may be designed in accordance with certain aspects of the present disclosure. While FIG. 2 illustrates the transceiver/front end 254 in a single box, those of skill in the art will appreciate that elements of the transceiver/front end 254 may be implemented across various elements, chips, modules, etc. For example, down and/or upconversion elements may be included in a transceiver chip within the transceiver/front end 254, while a power amplifier and/or envelope tracking elements may be implemented in a module separate from the transceiver chip within the transceiver/front end 254.

[0035] On the downlink, at access point 110, a TX data processor 210 receives traffic data from a data source 208 for N^ _n user terminals scheduled for downlink transmission, control data from a controller 230 and possibly other data from a scheduler 234. The various types of data may be sent on different transport channels. TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal TX data processor 210 may provide a downlink data symbol stream for one of more of the Ν^ _η user terminals to be transmitted from one of the N _ap antennas. The transceiver/front end 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver/front end 222 may also route the downlink signal to one or more of the N _ap antennas 224 for transmit diversity via an RF switch, for example. The controller 230 may control the routing within the transceiver/front end 222. Memory 232 may store data and program codes for the access point 110 and may interface with the controller 230.

[0036] At each user terminal 120, N _ut:tn antennas 252 receive the downlink signals from access point 110. For receive diversity at the user terminal 120, the transceiver/front end 254 may select signals received from one of the antennas 252 for processing. The signals received from multiple antennas 252 may be combined for enhanced receive diversity. The user terminal's transceiver/front end 254 also performs processing complementary to that performed by the access point's transceiver/front end 222 and provides a recovered downlink data symbol stream. An RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0037] Those skilled in the art will recognize the techniques described herein may be generally applied in systems utilizing any type of multiple access schemes, such as TDMA, SDMA, Orthogonal Frequency Division Multiple Access (OFDMA), CDMA, SC-FDMA, TD-SCDMA, and combinations thereof, among other systems/schemes.

[0038] FIG. 3 is a block diagram of an example transceiver/front end 300, such as transceiver/front ends 222, 254 in FIG. 2, in accordance with certain aspects of the present disclosure. The transceiver/front end 300 includes a transmit (TX) path 302 (also known as a transmit chain) for transmitting signals via one or more antennas and a receive (RX) path 304 (also known as a receive chain) for receiving signals via the antennas. When the TX path 302 and the RX path 304 share an antenna 303, the paths may be connected with the antenna via an interface 306, which may include any of various suitable RF devices, such as a duplexer, a switch, a diplexer, and the like.

[0039] Receiving in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, the mixer 312, and the DA 314 may be included in a radio frequency integrated circuit (RFIC), while the PA 316 may be external to the RFIC. The BBF 310 filters the baseband signals received from the DAC 308, and the mixer 312 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process produces the sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as the beat frequencies. The beat frequencies are typically in the RF range, such that the signals output by the mixer 312 are typically RF signals, which are amplified by the DA 314 and by the PA 316 before transmission by the antenna 303.

[0040] The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF 326 may be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signals output by the mixer 324 may be filtered by the BBF 326 before being converted by an analog-to- digital converter (ADC) 328 to digital I or Q signals for digital signal processing.

[0041] While it is desirable for the output of an LO to remain stable in frequency, tuning to different frequencies indicates using a variable-frequency oscillator, which may involve compromises between stability and tunability. Contemporary systems may employ frequency synthesizers with a VCO to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be produced by a TX frequency synthesizer 3 18, which may be buffered or amplified by amplifier 320 before being mixed with the baseband signals in the mixer 312. Similarly, the receive LO may be produced by an RX frequency synthesizer 330, which may be buffered or amplified by amplifier 332 before being mixed with the RF signals in the mixer 324. The transceiver/front end 300 may, for example, be configured for operation in quadrature or polar.

[0042] The PA 316 may be designed in accordance with certain aspects described herein. For example, the power supply to the PA 316 may comprise an envelope tracking supply modulator in accordance with certain aspects described herein. The envelope tracking supply modulator may be configured to adjust the power supply of the PA 316, such that the power supplied to the PA 316 is based on or substantially tracks the envelope (e.g., envelope waveform) of the signal to be amplified by the PA 316.

[0043] FIG. 4 illustrates an example envelope tracking amplification system 400. The envelope tracking amplification system 400 may include a power amplifier 316, an up-converter 404, an envelope detector 406, and an envelope tracking power supply 410. As illustrated, the amplifier 316 may be configured to amplify an input signal 412. The input signal 412 may represent an in-phase (I) or quadrature-phase (Q) signal. In some cases, the input signal may form an input to the up-converter 404, which generates an RF input signal 422 for the amplifier 316.

[0044] The input signal 412 also forms an input to the envelope detector 406, which generates an envelope signal 416 representing the envelope of the input signal 412 (e.g., provides a signal representing the magnitude of the input signal 412). The envelope signal 416 of the envelope detector 406 provides an input to the envelope tracking power supply 410, which in dependence thereon provides a supply voltage at the power supply node 420 to the amplifier 316. Therefore, the supply voltage at the power supply node 420 of the amplifier is adjusted based on (e.g., tracks) the envelope of the input signal 412. The amplifier 316 generates an amplified output signal 414 based on the input signal 412 (and RF input signal 422). The amplifier 316 may be implemented as a single stage or multi-stage amplifier. AN EXAMPLE ENVELOPE TRACKING POWER SUPPLY

[0045] Certain aspects of the present disclosure generally relate to an envelope tracking power supply. Envelope tracking integrated circuits (ETICs) may be designed with high output fidelity (low error vector magnitude (EVM)) and low output noise, in addition to high conversion efficiency. For example, envelope tracking power supplies may be designed with a switching mode power supply (SMPS) in order to take advantage of their high power efficiency. For example, the SMPS may be coupled in parallel with a linear regulator such that both the SMPS and the linear regulator provide current to the power supply node 420 of the amplifier 316.

[0046] FIG. 5 illustrates an example envelope tracking power supply 410 for generating a voltage supply Vamp for amplifier 316. The envelope tracking power supply 410 includes a linear regulator 502 (e.g., linear amplifier) which may be configured to generate the power supply voltage Vamp which tracks the envelope signal 416 of FIG. 4. The envelope tracking power supply 410 also includes a regulator 504 (e.g., a SMPS) which may have a higher power efficiency as compared to the regulator 502. The regulator 502 may be supplied a voltage (Vboost) which may be a higher voltage than a voltage (e.g., battery voltage Vbat) supplied to the regulator 504. For example, the voltage Vboost may be generated by a boost converter (not shown). As illustrated, the regulator 502 provides a current lamp, which may be combined with a current Iind from the regulator 504, and flows to the power supply node 420 of the amplifier 316. Therefore, the current lamp may be represented by the following equation:

lamp = Iload - Iind .

[0047] In certain aspects, the regulator 504 may be implemented using a buck converter. The buck converter may be configured to efficiently supply a current to node 420, for example when the supply voltage (e.g., the battery voltage Vbat) provided to the buck converter is higher than the voltage at node 420 (e.g., Vamp). Therefore, when the voltage of Vamp, which is generated based on the envelope of the input signal 412, is greater than the battery voltage (Vbat), the regulator 504 (e.g., SMPS) may be unable to supply power (current) to the power supply node 420, reducing the ETIC s overall efficiency since more current may be supplied by the regulator 502. Moreover, if Vamp increases above Vbat, current may back flow to Vbat from the boost converter generating Vboost. In otherwords, current from the boost converter may flow through the regulator 502 and the regulator 504, and back flow to the battery providing Vbat, further reducing ETIC's overall efficiency.

[0048] FIG. 6 is a graph illustrating the current Iind supplied by the regulator 504 and the load current Iload supplied to the amplifier 316 in certain implementations of the envelope tracking power supply 410 illustrated in FIG. 5. The line 602 represents the current Iind when Vbat is adequately above Vamp and the dotted line 604 represents the current Iind when the Vamp is closer to or higher than Vbat. As illustrated, the difference between the current Iload and the current Iind increases when Vamp is close to or exceeds Vbat. Since, the difference in the currents Iload and Iind is supplied by the regulator 502 (e.g., linear regulator) which is less efficient that the regulator 504, the overall efficiency of the ETIC is reduced.

[0049] FIG. 7 illustrates an example envelope tracking power supply 410, in accordance with certain aspects of the present disclosure. The voltage supply node 706 of the regulator 504 may be coupled to a circuit 702 for selecting between two voltages Vbat and Vboost. For example, the circuit 702 may provide either one of Vbat or Vboost to the voltage supply node 706 based on a voltage of Vamp (e.g,. the envelope of the input signal 412 from FIG. 4). The circuit 702 may include a first switch 704 coupled between node 708 (Vbat) and the voltage supply node 706 and a second switch 710 coupled between node 712 (Vboost) and the voltage supply node 706. In certain aspects, the switches 704 and 710 may be implemented using transistors such as p- channel metal oxide semiconductor (PMOS) transistors.

[0050] In certain aspects, the switches 704 and 710 may be controlled via a demultiplexer 714 that may be configured to close switch 704 when Vamp (e.g,. the envelope of the input signal 412) is below Vbat and close switch 710 when Vamp is close to or above Vbat In certain aspects, the demultiplexer 714 may be controlled by baseband circuitry based on the envelope of the input signal 412.

[0051] In certain aspects, the demultiplexer 714 may be controlled by a controller 716. In certain aspects, the controller 716 may be a comparator for comparing Vamp and Vbat and the switches 704 and 710 may be controlled based on the output of the comparator. That is, if the comparator output indicates that the Vamp is greater than Vbat, the switch 710 may be closed, and the switch 704 may be open. If the comparator output indicates that Vamp is less than Vbat, the switch 704 may be closed, and the switch 710 may be open. In certain aspects, the selection of Vboost and Vbat may be performed statically based on the peak value of Vamp, instead of switching real time when Vamp crosses Vbat. In some cases, the controller 716 may be implemented in a baseband module including baseband circuitry as described with respect to FIG 2, and the baseband module may control the demultiplexer 714. Those of skill in the art will appreciate that the selection circuit 702 may be implemented in any number of ways or with any number of different elements such that either Vboost or Vbat is selectively provided to the voltage supply node 706. While FIG. 7 illustrates an example configuration of the circuit 702, other configurations may be implemented according to the teachings herein.

[0052] Certain of the apparatus and techniques provided herein may increase the efficiency of the envelope tracking power supply 410. For example, power loss of the regulator 504 may be a function of the difference between the power supply voltage of the regulator 504 and the regulated output (Vamp). By supplying a relatively lower voltage Vbat (e.g., as compared Vboost) to the regulator 504 when Vbat is greater than Vamp, the power loss of the regulator 504 may be reduced, improving ETIC power efficiency. A higher voltage (Vboost) may be provided when Vamp exceeds (or gets close to) Vbat such that the regulator 504 can continue to provide current Iind to the power supply node 420. Moreover, supplying Vbat to the regulator 504 may also reduce the receive-band noise (RxBN) caused by the ETIC. Such implementations may be more cost effective than certain implementations in which the regulator 504 is replaced by a buck/boost converter which receives only the voltage Vbat, for example because circuitry required to implement the boost may be omitted and the Vboost supplied to the regulator 502 may be additionally supplied to the regulator 504.

[0053] FIG. 8 is a graph illustrating the current Iind supplied by the regulator 504 and the load current Iload, in accordance with certain implementations of the envelope tracking power supply 410 illustrated in FIG. 7. The line 802 represents the current Iind when the regulator 504 is being supplied with Vbat and Vamp is close to or exceeds Vbat. The line 804 represents the current Iind when the circuit 702 has switched the supply voltage of the regulator 504 from Vbat to Vboost, increasing the current Iind. As illustrated, the difference between the currents Hoad and Iind is reduced when the circuit 702 has switched the supply voltage of the regulator 504 from Vbat to Vboost, reducing the amount of current lamp to be supplied by regulator 502, improving overall ETIC efficiency.

[0054] FIG. 9 illustrates example operations 900 for generating a power supply voltage (e.g., Vamp), in accordance with certain aspects of the present disclosure. The operations 900 may be performed, for example, by a circuit such as the circuit of FIG. 7.

[0055] The operations 900 begin at 902, by generating, via a linear amplifier (e.g., regulator 502), the power supply voltage (e.g., Vamp) at a power supply node (e.g., node 420) of an amplifier (e.g., amplifier 316) or amplifying means based on an envelope of an input signal (e.g., input signal 412) to the amplifier or amplifying means and a voltage at a first voltage supply node. At 904, the operations 900 continue by selecting the first voltage supply node (e.g., Vboost) or a second voltage supply node (e.g., Vbat) based on the envelope of the input signal, and at 906, supplying, via a switch mode power supply (e.g., regulator 504) a current (e.g., Iind) to the power supply node (e.g., node 420) from the first voltage supply node or the second voltage supply node based on the selection. In certain aspects, the selecting the first voltage supply node or the second voltage supply node comprises coupling the first voltage supply node or the second voltage supply node to a power supply node of the SMPS. The selection may be performed by a controller (e.g., the controller 716), a baseband module, the selection circuit 702, and/or other means for selecting.

[0056] In some cases, the operations 900 also include comparing the envelope of the input signal to a voltage at the second voltage supply node, wherein the selecting is based on the comparison. In some cases, the selecting is based on a control signal received from a baseband module. In some cases, the voltage at the first voltage supply node is higher than a voltage at the second voltage supply node. In this case, the voltage at the second voltage supply node comprises a battery voltage.

[0057] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

[0058] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0059] As used herein, a phrase referring to "at least one of a list of items refers to any combination of those items, including single members. As an example, "at least one of: a, b, or c" is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0060] The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0061] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims. [0062] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the physical (PHY) layer. In the case of a user terminal, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

[0063] The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may be implemented with an ASIC with the processor, the bus interface, the user interface in the case of an access terminal), supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more FPGAs, PLDs, controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

[0064] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.