Title:
EQUALIZATION CIRCUIT, RECEPTION CIRCUIT AND INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/221427
Kind Code:
A1
Abstract:
The present invention comprises: a first addition circuit (31-1) that adds input signals (Vin, Vin-p, Vin-n); a comparison circuit (32) that compares the outputs of the first addition circuit; a latch circuit 61 that holds output data of the comparison circuit; a first digital/analog conversion circuit 62 that, when an equalization coefficient (K1-Kn) is a positive value, outputs a first signal corresponding to the absolute value of the equalization coefficient; a second digital/analog conversion circuit 63 that, when the equalization coefficient is a negative value, outputs a second signal corresponding to the absolute value of the equalization coefficient; and a switch circuit 64 that, on the basis of the data held by the latch circuit, performs switching of the connections between the output of the first digital/analog conversion circuit and the output of the second digital/analog conversion circuit, and an addition terminal and a subtraction terminal of the first addition circuit. Consequently, it becomes possible to increase a data rate while reducing the influence of inter symbol interference.
Inventors:
KUDO MASAHIRO (JP)
SUZUKI DAISUKE (JP)
SUZUKI DAISUKE (JP)
Application Number:
PCT/JP2016/068926
Publication Date:
December 28, 2017
Filing Date:
June 24, 2016
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H04B3/06
Domestic Patent References:
| WO2015125282A1 | 2015-08-27 |
Foreign References:
| US7564900B1 | 2009-07-21 | |||
| JP2009225018A | 2009-10-01 | |||
| JP2007515130A | 2007-06-07 | |||
| JP2015192200A | 2015-11-02 | |||
| US20110121867A1 | 2011-05-26 | |||
| JP2015192200A | 2015-11-02 | |||
| JP2001044895A | 2001-02-16 |
Other References:
See also references of EP 3477869A4
Attorney, Agent or Firm:
AOKI, Atsushi et al. (JP)
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