Related Applications

[0001] This application claims the benefit of provisional patent application serial number 63/245,139, filed September 16, 2021 , provisional patent application serial number 63/303,531 , filed January 27, 2022, and U.S. patent application serial number 17/737,300, filed May 5, 2022, the disclosures of which are hereby incorporated herein by reference in their entireties.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to a transmission circuit that transmits a radio frequency (RF) signal modulated in a wide modulation bandwidth.

Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capability in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience relies on a higher data rate offered by advanced fifth generation (5G) and 5G new radio (5G-NR) technologies, which typically transmit and receive radio frequency (RF) signals in millimeter wave spectrums. Given that the RF signals are more susceptible to attenuation and interference in the millimeter wave spectrums, the RF signals are typically amplified by state-of-the-art power amplifiers to help boost the RF signals to higher power before transmission.

[0005] Envelope tracking (ET) is a power management technology designed to improve operating efficiency and/or linearity performance of the power amplifiers. In an ET power management circuit, a power management integrated circuit (PMIC) is configured to generate a time-variant ET voltage based on a time-variant voltage envelope of the RF signals, and the power amplifiers are configured to amplify the RF signals based on the time-variant ET voltage. Understandably, the better the time-variant ET voltage is aligned with the timevariant voltage envelope in time and amplitude, the better the performance (e.g., efficiency and/or linearity) that can be achieved at the power amplifiers. However, the time-variant ET voltage can become misaligned from the timevariant voltage envelope in time and/or amplitude due to a range of factors (e.g., group delay, impedance mismatch, etc.). As such, it is desirable to always maintain good alignment between the time-variant voltage and the time-variant voltage envelope and across a wide modulation bandwidth.

[0006] Embodiments of the disclosure relate to equalization filter calibration in a transceiver circuit. The transceiver circuit generates a radio frequency (RF) signal(s) from a time-variant modulation vector and a power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit (e.g., filter/multiplexer circuit). Notably, when the power amplifier circuit(s) is coupled to the RF frontend circuit, an output reflection coefficient (e.g., S22) of the power amplifier circuit(s) can interact with an input reflection coefficient (e.g., S11) of the RF frontend circuit to create a voltage distortion filter on an output stage of the power amplifier circuit(s), which can cause unwanted distortion in the RF signal(s). In this regard, the transceiver circuit is configured to apply an equalization filter to the time-variant modulation vector to thereby compensate for the voltage distortion filter at the output stage of the power amplifier circuit(s). In embodiments disclosed herein, a calibration circuit can be configured to calibrate the equalization filter across multiple frequencies within a modulation bandwidth of the power amplifier circuit to generate a gain offset lookup table (LUT) and a delay LUT. As a result, the equalization filter can be dynamically adapted to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter across the modulation bandwidth of the power amplifier circuit.

[0007] In one aspect, a transceiver circuit is provided. The transceiver circuit includes a memory circuit. The transceiver circuit also includes a calibration circuit. The calibration circuit is coupled to a power amplifier circuit. The calibration circuit is configured to determine and store a gain offset LUT in the memory circuit to correlate multiple calibrated frequencies within a modulation bandwidth of the power amplifier circuit with multiple gain offsets, respectively. The calibration circuit is also configured to determine and store a delay offset LUT in the memory circuit to correlate the multiple calibrated frequencies with multiple delay factors, respectively.

[0008] In another aspect, a method for calibrating an equalization filter in a transceiver circuit is provided. The method includes determining and storing a gain offset LUT to correlate a plurality of calibrated frequencies within a modulation bandwidth with a plurality of gain offsets, respectively. The method also includes determining and storing a delay offset LUT to correlate the plurality of calibrated frequencies with a plurality of delay factors, respectively.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] Figure 1 A is a schematic diagram of an exemplary existing transmission circuit, wherein an unwanted voltage distortion filter may be created on a power amplifier circuit when the power amplifier circuit is coupled to a radio frequency (RF) front-end circuit; [0012] Figure 1 B is a schematic diagram providing an exemplary illustration of an output stage of the power amplifier circuit in Figure 1 A;

[0013] Figure 2 is a schematic diagram of an exemplary equivalent model providing an exemplary illustration of the unwanted voltage distortion filter created by a coupling between the power amplifier circuit and the RF front-end circuit 14 in Figure 1 A;

[0014] Figure 3 is a schematic diagram of an exemplary transmission circuit configured to compensate for the unwanted voltage distortion filter in the existing transmission circuit of Figure 1 A based on an equalization filter;

[0015] Figures 4A-4C are graphic diagrams providing exemplary illustrations as to why the equalization filter in Figure 3 must be calibrated across a modulation bandwidth of the transmission circuit;

[0016] Figure 5 is a schematic diagram of an exemplary transceiver circuit that can be configured according to embodiments of the present disclosure to calibrate the equalization filter across a modulation bandwidth of the transmission circuit of Figure 3;

[0017] Figure 6 is a flowchart of an exemplary calibration process that can be employed by the transceiver circuit of Figure 5 to calibrate the equalization filter;

[0018] Figure 7 is a flowchart of an exemplary process that can be employed by the transceiver circuit of Figure 5 to determine a gain offset lookup table (LUT) as part of the calibration process of Figure 6;

[0019] Figures 8A-8B are graphic diagrams illustrating impacts of the equalization filter calibration as performed based on the processes of Figures 6 and 7;

[0020] Figure 9 is a flowchart of an exemplary process that can be employed by the transceiver circuit of Figure 5 to determine a gain offset LUT according to an alternative embodiment of the present disclosure; and

[0021] Figure 10 is a flowchart of an exemplary process that can be employed by the transceiver circuit of Figure 5 to determine a delay LUT as part of the calibration process of Figure 6. Detailed Description

[0022] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0023] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0024] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0025] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] Embodiments of the disclosure relate to equalization filter calibration in a transceiver circuit. The transceiver circuit generates a radio frequency (RF) signal(s) based on a time-variant modulation vector and a power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit (e.g., filter/multiplexer circuit). Notably, when the power amplifier circuit(s) is coupled to the RF frontend circuit, an output reflection coefficient (e.g., S22) of the power amplifier circuit(s) can interact with an input reflection coefficient (e.g., S11) of the RF frontend circuit to create a voltage distortion filter on an output stage of the power amplifier circuit(s), which can cause unwanted distortion in the RF signal(s). In this regard, the transceiver circuit is configured to apply an equalization filter to the time-variant modulation vector to thereby compensate for the voltage distortion filter at the output stage of the power amplifier circuit(s). In embodiments disclosed herein, a calibration circuit can be configured to calibrate the equalization filter across multiple frequencies within a modulation bandwidth of the power amplifier circuit to generate a gain offset lookup table (LUT) and a delay LUT. As a result, the equalization filter can be dynamically adapted to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter across the modulation bandwidth of the power amplifier circuit.

[0029] Before discussing the transceiver circuit and the calibration process according to the present disclosure, starting at Figure 5, a brief discussion is first provided to help explain why there is a need to calibrate an equalization filter used in an existing transmission circuit for suppressing an unwanted voltage distortion filter.

[0030] Figure 1 A is a schematic diagram of an exemplary existing transmission circuit 10, wherein an unwanted voltage distortion filter Hiv(s) presented to a power amplifier circuit 12 can cause a memory distortion in the power amplifier circuit 12 when the power amplifier circuit 12 is coupled to an RF front-end circuit 14. Notably, in the unwanted voltage distortion filter Hiv(s), “s” is a notation of Laplace transform.

[0031] The existing transmission circuit 10 includes a transceiver circuit 16, an ETIC 18, and a transmitter circuit 20, which can include an antenna(s) (not shown) as an example. The transceiver circuit 16 is configured to generate an RF signal 22 having a time-variant input power PIN and provide the RF signal 22 to the power amplifier circuit 12. The transceiver circuit 16 is also configured to generate a time-variant target voltage VTGT, which tracks the time-variant input power PIN of the RF signal 22. The ETIC 18 is configured to generate a modulated voltage Vcc that tracks the time-variant target voltage VTGT and provides the modulated voltage Vcc to the power amplifier circuit 12.

Accordingly, the power amplifier circuit 12 can amplify the RF signal 22 to a timevariant output power POUT as a function of a time-variant output voltage VOUT.

The power amplifier circuit 12 then provides the amplified RF signal 22 to the RF front-end circuit 14. The RF front-end circuit 14 may be a filter circuit that performs further frequency filtering on the amplified RF signal 22 before providing the amplified RF signal 22 to the transmitter circuit 20 for transmission.

[0032] Figure 1 B is a schematic diagram providing an exemplary illustration of an output stage 24 of the power amplifier circuit 12 in Figure 1 A. Common elements between Figures 1 A and 1 B are shown therein with common element numbers and will not be re-described herein.

[0033] The output stage 24 can include at least one transistor 26, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor 26 can include a base electrode B, a collector electrode C, and an emitter electrode E. The base electrode B is configured to receive a bias voltage VBIAS and the collector electrode C is configured to receive the modulated voltage Vcc. The collector electrode C is also coupled to the RF front-end circuit 14 and configured to output the amplified RF signal 22 at the output voltage VOUT. In this regard, the output voltage VOUT can be a function of the modulated voltage Vcc. Understandably, the power amplifier circuit 12 will operate with good efficiency and linearity when the time-variant modulated voltage Vcc is aligned with the time-variant input power PIN.

[0034] Figure 2 is a schematic diagram of an exemplary equivalent model 28 providing an exemplary illustration of the voltage distortion filter Hiv(s) created by a coupling between the power amplifier circuit 12 and the RF front-end circuit 14 in the existing transmission circuit 10 of Figure 1 A. Elements in Figures 1 A and 1 B are referenced in Figure 2 without being re-described herein.

[0035] In the equivalent model 28, VPA and ZPA represent the output stage 24 of the power amplifier circuit 12 and an inherent impedance of the power amplifier circuit 12, respectively, and Zu represents an inherent impedance associated with an input port of the RF front-end circuit 14. Herein, VOUT represents an output voltage associated with the RF signal 22 before the power amplifier circuit 12 is coupled to the RF front-end circuit 14, and V’OUT represents an output voltage associated with the RF signal 22 after the power amplifier circuit 12 is coupled to the RF front-end circuit 14. Hereinafter, the output voltages VOUT and V’OUT are referred to as “non-coupled output voltage” and “coupled output voltage,” respectively, for distinction.

[0036] A Laplace transform representative of the coupled output voltage V’OUT can be expressed in equation (Eq. 1 ) below.

[0037] In the equation (Eq. 1 ) above, TPA(S) represents a reflection coefficient looking back into the output stage 24 of the power amplifier circuit 12 and Ti(s) represents a reflection coefficient looking into the RF front-end circuit 14.

Notably, TPA(S) and Ti(s) are complex filters containing amplitude and phase information. In this regard, the TPA(S), the 7i(s), and, therefore, the voltage distortion filter Hiv(s) are dependents of such factors as modulation bandwidth, RF spectrum, and/or voltage standing wave ratio (VSWR).

[0038] The equation (Eq. 1 ) shows that the coupled output voltage V’OUT will be altered from the non-coupled output voltage VOUT by the voltage distortion filter Hiv(s) when the power amplifier circuit 12 is coupled to the RF front-end circuit 14. As a result, the coupled output voltage V’OUT may become misaligned from the modulated voltage Vcc, thus causing unwanted distortion in the RF signal 22.

[0039] Notably, it is possible to modify the modulated voltage Vcc to compensate for the voltage distortion filter Hiv(s) to thereby reduce or eliminate the difference between the non-coupled output voltage VOUT and the coupled output voltage V’OUT. AS a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter Hiv(s).

[0040] In this regard, Figure 3 is a schematic diagram of an exemplary transmission circuit 30 configured to compensate for the unwanted voltage distortion filter Hiv(s) in the existing transmission circuit 10 of Figure 1 A based on an equalization filter HET(S). The transmission circuit 30 is configured to transmit an RF signal 32 modulated in a wide range of modulation bandwidths. In a nonlimiting example, the RF signal 32 can be modulated in a modulation bandwidth of 200 MHz or higher and transmitted in a millimeter wave RF spectrum.

[0041] The transmission circuit 30 includes a transceiver circuit 34, a power amplifier circuit 36, and an ETIC 38. The power amplifier circuit 36 is coupled to a transmitter circuit 40 via an RF front-end circuit 42. In a non-limiting example, the RF front-end circuit 42 can include one or more of a filter circuit and a multiplexer circuit (not shown). The filter circuit may be configured to include a filter network, such as an acoustic filter network with a sharp cutoff frequency. The power amplifier circuit 36 may be identical to or functionally equivalent to the power amplifier circuit 12 in Figure 1 B. As such, the power amplifier circuit 36 may also include the output stage 24 as in the power amplifier circuit 12.

[0042] The transceiver circuit 34 includes a signal processing circuit 44 and a target voltage circuit 46. The signal processing circuit 44 is configured to generate the RF signal 32 from a time-variant modulation vector bMOD^. The time-variant modulation vector bMOD^ may be generated by a digital baseband circuit (not shown) in the transceiver circuit 34 and includes both in-phase (I) and quadrature (Q) components. The target voltage circuit 46 is configured to detect a time-variant amplitude envelope l ² +Q ² of the RF signal 32 from the timevariant modulation vector bMOD^. Accordingly, the target voltage circuit 46 can generate a modulated target voltage VTGT based on the detected time-variant amplitude envelope l ² +Q ² . [0043] The ETIC 38 is configured to generate a modulated voltage Vcc based on the modulated target voltage VTGT and provide the modulated voltage Vcc to the power amplifier circuit 36. The power amplifier circuit 36, in turn, amplifies the RF signal 32 to an output voltage VOUT based on the modulated voltage Vcc for transmission via the RF front-end circuit 42 and the transmitter circuit 40. [0044] As previously described, the output voltage VOUT is a function of the modulated voltage Vcc. In this regard, it is possible to reduce or even eliminate the difference between the non-coupled output voltage VOUT and the coupled output voltage V’OUT by generating the modulated voltage Vcc to compensate for the voltage distortion filter Hiv(s). Given that the ETIC 38 is configured to generate the modulated voltage Vcc based on the modulated target voltage VTGT, it is thus possible to reduce or even eliminate the difference between the noncoupled output voltage VOUT and the coupled output voltage V’OUT by generating the modulated target voltage VTGT to compensate for the voltage distortion filter Hiv(s).

[0045] In this regard, the transceiver circuit 34 further includes an equalizer circuit 48. The equalizer circuit 48 is configured to apply the equalization filter HET(S) to the time-variant modulation vector bMOD^ prior to the target voltage circuit 46 generating the modulated target voltage VTGT. In an embodiment, the equalization filter HET(S) can be described by equation (Eq. 2) below.

HET(S) = HIQ(S) * HPA(S) * Hiv(s) (Eq. 2)

[0046] In the equation (Eq.2) above, HIQ(S) represents a transfer function of the signal processing circuit 44 and HPA(S) represents a voltage gain transfer function of the power amplifier circuit 36. In this regard, the equalization filter HET(S) is configured to match a combined signal path filter that includes the transfer function HIQ(S), the voltage gain transfer function HPA(S), and the voltage distortion filter Hiv(s).

[0047] In an embodiment, the equalizer circuit 48 applies the equalization filter HET(S) to the time-variant modulation vector bMOD^ to generate an equalized time- variant modulation vector IOMOD-E^ and provides the equalized time-variant modulation vector IOMOD-E^ to the target voltage circuit 46. The target voltage circuit 46, in turn, detects the time-variant amplitude envelope Vl ² +Q ² from the equalized time-variant modulation vector ICMOD-E^ and generates the modulated target voltage VTGT based on the detected time-variant amplitude envelope Vl ² +Q ² . Since the modulated target voltage VTGT is generated from the equalized time-variant modulation vector bMOD-E^, the modulated target voltage VTGT, and therefore the modulated voltage Vcc, will be able to compensate for the voltage distortion filter Hiv(s), which is created on the output stage 24 of the power amplifier circuit 36 by coupling the power amplifier circuit 36 with the RF frontend circuit 42.

[0048] In an embodiment, the target voltage circuit 46 includes an amplitude detector circuit 50, an ET LUT circuit 52, and a digital-to-analog converter (DAC) 54. The amplitude detector circuit 50 is configured to detect the time-variant amplitude envelope l ² +Q ² from the equalized time-variant modulation vector bMOD-E^. The ET LUT circuit 52, which can include an isogain LUT (not shown) correlating the time-variant amplitude envelope l ² +Q ² with various level of voltages, is configured to generate a time-variant digital target voltage VDTGT based on the detected time-variant amplitude envelope Vl ² +Q ² . The DAC 54 is configured to convert the time-variant digital target voltage VDTGT into the modulated target voltage VTGT and provide the modulated target voltage VTGT to the ETIC 38.

[0049] In an embodiment, the signal processing circuit 44 can include a memory digital predistortion (mDPD) circuit 56 and a modulator circuit 58. The mDPD circuit 56 is configured to receive the time-variant modulation vector bMOD- and digitally pre-distort the time-variant modulation vector bMOD-E^ to generate a pre-distorted time-variant modulation vector bMOD-DPD^. The modulator circuit 58 is configured to generate the RF signal 32 from the pre-distorted time-variant modulation vector bMOD-DPD^ and provide the RF signal 32 to the power amplifier circuit 36. [0050] As mentioned earlier, the RF signal 32 may be modulated in a wide range of modulation bandwidth. Herein, a modulation bandwidth refers to a range of RF frequencies that the RF signal 32 may be modulated onto and/or the transmission circuit 30 is configured to handle. For example, if the RF signal 32 can be modulated between 2554 MHz and 2654 MHz, the modulation bandwidth will then be 100 MHz and a center frequency (Fc) of the modulation bandwidth will be at 2604 MHz. Accordingly, any other frequencies within the modulation bandwidth will be regarded as non-center frequencies (FNC) (2554 MHz FNC < 2604 MHz and 2604 MHz < FNC 2654 MHz). Hereinafter, the modulation bandwidth of the RF signal 32 is referred to interchangeably as the modulation bandwidth of the transmission circuit 30.

[0051] In this regard, the equalization filter HET(S) needs to suppress the voltage distortion filter Hiv(s) across the entire modulation bandwidth. However, as the isogain LUT in the ET LUT circuit 52 is typically determined based on a center frequency within the modulation bandwidth, the isogain LUT in the ET LUT circuit 52 may not be able provide a constant isogain for all other frequencies within the modulation bandwidth. Accordingly, the equalization filter HET(S) must be calibrated to ensure that the isogain LUT determined based on the center frequency can provide a constant isogain across all the frequencies within the modulation bandwidth.

[0052] Figures 4A-4C are graphic diagrams providing exemplary illustrations as to why the equalization filter HET(S) in Figure 3 must be calibrated across a modulation bandwidth of the transmission circuit 30. Common elements between Figures 4A-4C are shown therein with common element numbers and will not be re-described herein.

[0053] Figure 4A illustrates a center-frequency LUT 60 corresponding to a center frequency Fc within the modulation bandwidth of the transmission circuit 30 and a non-center-frequency LUT 62 corresponding to a non-center frequency FNC within the modulation bandwidth of the transmission circuit 30.

[0054] Figure 4B illustrates a center-frequency gain 64 provided by the center-frequency LUT 60 and a non-center-frequency gain 66 provided by the non-center-frequency LUT 62. As illustrated, the center-frequency LUT 60 can provide a 30 dB constant gain when the RF signal 32 is modulated at the center frequency Fc and has the input power PIN between -25 dBm and 3 dBm for the center frequency Fc. The non-center-frequency LUT 62, on the other hand, can provide a 29 dB constant gain when the RF signal 32 is modulated at the noncenter frequency FNC and has the input power PIN between -25 dBm and 4 dBm. In this regard, if the ET LUT circuit 52 employs both the center-frequency LUT 60 and the non-center-frequency LUT 62, it will be possible to achieve constant gains when the RF signal 32 is modulated at both the center frequency Fc and the non-center frequency FNC.

[0055] However, when the ET LUT circuit 52 employs only the centerfrequency LUT 60, the non-center-frequency LUT 62 would not be able to maintain the 29 dB constant gain at the non-center-frequency FNC. AS illustrated in Figure 4C, the center-frequency LUT 60 in Figure 4A provides a varying gain from 29.4 dB to 30.5 dB between -25 dBm and +2 dBm but does not provide 29 dB constant gain when the RF signal 32 is modulated at the non-center- frequency FNC. Hence, it is desirable to calibrate the equalization filter HET(S) to ensure that the center-frequency LUT 60 can provide a constant gain across center and non-center frequencies within the modulation bandwidth of the RF signal 32.

[0056] In this regard, Figure 5 is a schematic diagram of an exemplary transceiver circuit 68 that can be configured according to embodiments of the present disclosure to calibrate the equalization filter HET(S) across a modulation bandwidth of the transmission circuit of Figure 3. Common elements between Figures 3 and 5 are shown therein with common element numbers and will not be re-described herein. In an embodiment, the transceiver circuit 68 may be employed in the transmission circuit 30 to replace the transceiver circuit 34. [0057] In an embodiment, the transceiver circuit 68 includes a memory circuit 70. The memory circuit 70, which can include such storage circuits as randomaccess memory (RAM), flash storage, solid-state disk (SSD), as an example, is configured to store a gain offset LUT 72 and a delay LUT 74. In a non-limiting example, the gain offset LUT 72 includes multiple gain offset entries 76(1)-76(N), each configured to correct a respective one of multiple calibrated frequencies Fi- FN within the modulation bandwidth with a respective one of multiple gain offsets AGI-AGN. Herein, the calibrated frequencies FI-FN include all the non-center frequencies (FNC) and the center frequency (Fc) within the modulation bandwidth. In another non-limiting example, the delay LUT 74 includes multiple delay entries 78(1)-78(N), each configured to correlate a respective one of the calibrated frequencies FI-FN with a respective one of multiple delay factors T-I-TN.

[0058] In an embodiment, the transceiver circuit 68 can be configured to include a calibration circuit 80, which can be a field-programmable gate array (FPGA), as an example. Although the calibration circuit 80, as illustrated herein, is provided inside the transceiver circuit 68, it should be appreciated that the calibration circuit 80 can be separated from the transceiver circuit 68 but coupled to the transceiver circuit 68 via, for example, a general-purpose input/output (GPIO) interface. As discussed below, the calibration circuit 80 can be configured to determine and populate the gain offset LUT 72 and the delay LUT 74 such that the equalization filter HET(S) can be calibrated to cause the ET LUT circuit 52 to provide a constant gain across all the calibrated frequencies FI-FN based on, for example, the center-frequency LUT 60 in Figure 4A.

[0059] The calibration circuit 80 may be configured to calibrate the equalization filter HET(S) based on a process. In this regard, Figure 6 is a flowchart of an exemplary calibration process 200 that can be employed by the calibration circuit 80 in the transceiver circuit 68 of Figure 5 to calibrate the equalization filter HET(S).

[0060] Herein, the calibration circuit 80 is first configured to determine and store the gain offset LUT 72 that includes the gain offset entries 76(1)-76(N), with each of the gain offset entries 76(1)-76(N) configured to correlate a respective one of the calibrated frequencies FI-FN within the modulation bandwidth with a respective one of the gain offsets AGI-AGN (step 202). Next, the calibration circuit 80 is configured to determine and store the delay LUT 74 that includes the delay entries 78(1 )-78(N), with each of the delay entries 78(1 )-78(N) configured to correlate a respective one of the calibrated frequencies FI-FN with a respective one of the delay factors T-I-TN (step 204).

[0061] In an embodiment, the calibration circuit 80 may determine and store the gain offset LUT 72 (step 202) in the memory circuit 70 based on a process. In this regard, Figure 7 is a flowchart of an exemplary process 206 that can be employed by the calibration circuit 80 in the transceiver circuit 68 of Figure 5 to determine the gain offset LUT 72 as part of the calibration process 200 of Figure 6. Elements in Figure 5 are referenced in conjunction with the discussion of Figure 7 and will not be re-described herein.

[0062] Herein, the calibration circuit 80 is configured to determine a minimum reference voltage VCC-REF and a minimum reference input power PIN-REF based on an efficiency target, a noise target, and/or a linearity target of the power amplifier circuit 36 (step 208). In other words, the minimum reference voltage VCC-REF and the minimum reference input power PIN-REF can be determined empirically to achieve a desired trade-off between the efficiency target, the noise target, and/or the linearity target of the power amplifier circuit 36. Although the calibration circuit 80 is configured herein to determine a minimum reference input power PIN- REF, it should be appreciated that it is also possible to replace the input power PIN- REF with a corresponding output power.

[0063] The calibration circuit 80 then determines a reference frequency FREF among the calibrated frequencies FI-FN within the modulation bandwidth of the power amplifier circuit 36 (step 210). In a non-limiting example, the reference frequency FREF can be the center frequency Fc among the calibrated frequencies FI-FN.

[0064] Next, the calibration circuit 80 determines a reference target voltage (VTGT-REF) based on an expected root-mean-square (RMS) of the modulated voltage Vcc (e.g., 2.5 V) to be provided to the power amplifier circuit 36 for amplifying the RF signal 32 in the transmission circuit 30 of Figure 3 (step 212). [0065] Next, the calibration circuit 80 selects a calibrated frequency Fi among the calibrated frequencies FI-FN within the modulation bandwidth (step 214). The calibration circuit 80 then determines a respective gain Gi of the power amplifier circuit 36 when the power amplifier circuit 36 amplifies a test signal 82 that is generated at the selected calibrated frequency Fi and in the minimum reference input power PIN-REF based on the minimum reference voltage VCC- EF (step 216). Notably, the test signal 82 may be generated by the calibration circuit 80 or a separate signal generator (not shown). In a non-limiting example, the calibration circuit 80 can measure an output power POUT of the power amplifier circuit 36 and determine the respective reference gain G EF based on the measured output power POUT and the determined minimum reference input power PIN-REF. Subsequently, the calibration circuit 80 can determined a respective modulated voltage Vccj (1 = j = M) and a respective input power PINJ (1 = j = M) that can cause the power amplifier circuit 36 to have the respective gain Gi when amplifying the RF signal 32 at the selected calibrated frequency Fi (step 218). Herein, M may be identical to or different from N. Accordingly, the calibration circuit 80 can store the respective modulated voltage Vccj and the respective input power PINJ in a temporary voltage LUT (not shown) in the memory circuit 70 (step 220). The calibration circuit 80 is configured to repeat steps 214-220 for each of the calibrated frequencies FI-FN.

[0066] With continuing reference to Figure 7, the calibration circuit 80 again selects a calibrated frequency Fi (1 = i = N) among the calibrated frequencies FI-FN within the modulation bandwidth (step 222). The calibration circuit 80 then determines a respective adjusted input power PIN-ADJI (1 = i = N) relative to an input power PINJ (1 = j = M) in the temporary voltage LUT associated with a modulated voltage Vccj that is equal to the reference target voltage VTGT-REF (step 224). Subsequently, the calibration circuit 80 determines a respective gain offset Gi (1 = i = N) between a respective adjusted input power at the reference frequency FREF and the respective adjusted input power PIN-ADJI at the selected calibrated frequency Fi (step 226). The calibration circuit 80 then stores the selected calibrated frequency Fi in association with the respective gain offset AGi in the gain offset LUT 72 (step 228). Notably, the calibration circuit 80 is configured to repeat steps 222-228 for each of the calibrated frequencies FI-FN. [0067] With reference back to Figure 5, for each of the calibrated frequencies FI-FN, the equalizer circuit 48 is configured to generate the equalization filter HET(s) based on the gain offset LUT 72 and apply the equalization filter HET(S) to the time-variant modulation vector bMOD^ to generate the equalized time-variant modulation vector bMOD-E^. Figures 8A-8B are graphic diagrams illustrating an impact of the equalization filter calibration as performed based on the process 200 of Figure 6 and the process 206 of Figure 7.

[0068] Figure 8A illustrates a center-frequency LUT 84 corresponding to a center frequency Fc among the calibrated frequencies FI-FN and a non-center- frequency LUT 86 corresponding to a non-center frequency FNC among the calibrated frequencies FI-FN. Notably, both the center-frequency LUT 84 and the non-center-frequency LUT 86 are both based on the same minimum reference voltage VCC-REF and the same minimum reference input power PIN-REF. The center-frequency LUT 84 will be stored in the ET LUT circuit 52 in the transmission circuit 30 for generating the time-variant digital target voltage VDTGT from the detected time-variant amplitude envelope l ² +Q ² . The non-center- frequency LUT 86, on the other hand, is not stored in the ET LUT circuit 52 and can be seen as a “virtual” LUT. The equalization filter HET(S) can use a corresponding gain offset AGi (1 = i = N) of the non-center frequency FNC to superimpose the non-center-frequency LUT 86 on the center-frequency LUT 84. As can be visualized in Figure 8A, it is equivalent to left-shifting the non-center- frequency LUT 86 to overlap with the center-frequency LUT 84. As a result, as illustrated in Figure 8B, a center-frequency gain 88 and a non-center-frequency gain 90 are both relatively constant.

[0069] In an embodiment, the calibration circuit 80 may determine and store the gain offset LUT 72 (step 202) in the memory circuit 70 based on an alternative process. In this regard, Figure 9 is a flowchart of an exemplary process 230 that can be employed by the calibration circuit 80 in the transceiver circuit 68 of Figure 5 to determine the gain offset LUT 72 according to another embodiment of the present disclosure. Elements in Figure 5 are referenced in conjunction with the discussion of Figure 9 and will not be re-described herein. [0070] Herein, the calibration circuit 80 is configured to determine a reference voltage VCC-REF and a reference input power PIN-REF based on an efficiency target and/or a noise target of the power amplifier circuit 36 (step 232). In other words, the reference voltage VCC-REF and the reference input power PIN-REF can be determined empirically to achieve a desired trade-off between the efficiency target and the noise target of the power amplifier circuit 36. Although the calibration circuit 80 is configured herein to determine a reference input power PIN-REF, it should be appreciated that it is also possible to replace the reference input power PIN-REF with a corresponding reference output power.

[0071] The calibration circuit 80 then determines a reference frequency FREF among the calibrated frequencies FI-FN within the modulation bandwidth of the power amplifier circuit 36 (step 234). In a non-limiting example, the reference frequency FREF can be the center frequency Fc among the calibrated frequencies FI-FN.

[0072] Next, the calibration circuit 80 determines a reference target voltage (VTGT-REF) based on an expected RMS of the modulated voltage Vcc (e.g., 2.5 V) to be provided to the power amplifier circuit 36 for amplifying the RF signal 32 in the transmission circuit 30 of Figure 3 (step 236).

[0073] Next, the calibration circuit 80 selects a calibrated frequency Fi among the calibrated frequencies FI-FN within the modulation bandwidth (step 238). The calibration circuit 80 determines a respective gain Gi (1 = i = N) of the power amplifier circuit 36 when the power amplifier circuit 36 amplifies the test signal 82 that is generated at the selected calibrated frequency Fi and in the reference input power PIN-REF based on the reference voltage VCC-REF (step 240).

[0074] The calibration circuit 80 then adjusts the respective gain Gi based on a determined compression gain GCMP to determine a compressed reference gain GREF-CMP (step 242). Notably, the calibration circuit 80 may determine compression gain GCMP empirically to achieve a desired linearity target of the power amplifier circuit 36.

[0075] The calibration circuit 80 then determines a respective modulated voltage Vccj (1 = j = M) and a respective input power PINJ (1 = j = M) that will cause the power amplifier circuit 36 to have the compressed reference gain GREF- CMP when amplifying the test signal 82 at the selected calibrated frequency Fi (step 244). Herein, M may be identical to or different from N. Accordingly, the calibration circuit 80 can store the respective modulated voltage Vccj and the respective input power PINJ in a temporary voltage LUT (not shown) in the memory circuit 70 (step 246). The calibration circuit 80 is configured to repeat steps 238-246 for each of the calibrated frequencies FI-FN.

[0076] With continuing reference to Figure 9, the calibration circuit 80 selects a calibrated frequency Fi (1 = i = N) among the calibrated frequencies FI-FN within the modulation bandwidth (step 248). The calibration circuit 80 then determines a respective adjusted input power PIN-ADJI (1 = i = N) relative to an input power PINJ (1 = j = M) in the temporary voltage LUT associated with a modulated voltage Vccj (1 = j = M) that is equal to the reference target voltage VTGT- EF (step 250).

[0077] Subsequently, the calibration circuit 80 determines a respective gain offset AGi (1 = i = N) between a respective adjusted input power at the reference frequency F EF and the respective adjusted input power PIN-ADJI at the selected calibrated frequency Fi (step 252). The calibration circuit 80 then stores the selected calibrated frequency Fi in association with the respective gain offset AGi in the gain offset LUT 72 (step 254). Notably, the calibration circuit 80 is configured to repeat steps 248-254 for each of the calibrated frequencies FI-FN. [0078] In an embodiment, the calibration circuit 80 may determine and store the delay LUT 74 (step 204) in the memory circuit 70 based on a process. In this regard, Figure 10 is a flowchart of an exemplary process 256 that can be employed by the transceiver circuit 68 of Figure 5 to determine the delay LUT 74 as part of the calibration process 200 of Figure 6. Elements in Figure 5 are referenced in conjunction with the discussion of Figure 10 and will not be redescribed herein.

[0079] Herein, the calibration circuit 80 first determines an arbitrary delay offset At (step 258). Next, the calibration circuit 80 selects a calibrated frequency Fi (1 N) among the calibrated frequencies FI-FN within the modulation bandwidth (step 260). The calibration circuit 80 then determines an arbitrary delay factor T (step 264). The calibration circuit 80 then measures a pair of output powers POUTI , POUT2 of the power amplifier circuit 36 when the power amplifier circuit 36 amplifies the test signal 82 that is generated at the selected calibrated frequency Fi and delayed by T ± At, respectively (step 264).

[0080] The calibration circuit 80 checks whether the pair of output powers POUTI and POUT2 are equal (step 266). In an embodiment, the calibration circuit 80 may treat the pair of output powers POUTI and POUT2 as being equal if a difference between the pair of output powers POUTI and POUT2 is smaller than a predefined threshold.

[0081] If the pair of output powers POUTI and POUT2 are equal, the calibration circuit 80 stores the selected calibrated frequency Fi in association with arbitrary delay factor T in the delay LUT 74 (step 268). Otherwise, the calibration circuit 80 will return to step 262 and determine a new arbitrary delay factor T. The calibration circuit 80 may adjust (e.g., increase) the predefined threshold in case the pair of output powers POUTI and POUT2 remain unequal after several iterations. Notably, the calibration circuit 80 is configured to repeat steps 260-268 for each of the calibrated frequencies FI-FN.

[0082] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.