Title:
EQUALIZATION FILTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2008/029643
Kind Code:
A1
Abstract:
An equalization filter circuit includes: a first transmission line having an
input terminal (101) dependently connected to a plurality of first delay devices (104a);
a second transmission line having an output terminal (102) dependently connected
to a plurality of second delay devices (107a); a plurality of weighting circuits
(105a) connected in parallel between the first transmission line and the second
transmission line and having a gain which can be adjusted by a coefficient setting;
and a variable adjusting circuit (108a) arranged at the output side of at least
one weighting circuit (105a) for correcting fluctuation of output characteristics
of the weighting circuits (105a).
Inventors:
WADA, Shigeki (7-1 Shiba 5-chom, Minato-ku Tokyo 01, 1088001, JP)
Application Number:
JP2007/066460
Publication Date:
March 13, 2008
Filing Date:
August 24, 2007
Export Citation:
Assignee:
NEC CORPORATION (7-1 Shiba 5-chome, Minato-ku, Tokyo 01, 1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目７番１号 Tokyo, 1088001, JP)
International Classes:
H03H15/00; H03H21/00; H04B3/06; H03H15/00; H03H21/00; H04B3/06
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (8th Floor, 16th Kowa Bldg.9-20, Akasaka 1-chom, Minato-ku Tokyo 52, 1070052, JP)