Title:
EQUALIZING CIRCUIT, RECEPTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/003057
Kind Code:
A1
Abstract:
The present invention has: an addition circuit (101) that adds together an input signal and a compensation signal; a comparison circuit (102) that compares the outputs of the addition circuit; first latch circuits (103) that hold the outputs of the comparison circuit, and the number of which is smaller by 1 than that of the taps of an equalizing circuit; a selection circuit (104) that selects and outputs one of the outputs of the comparison circuit and the first latch circuits; a second latch circuit (105) that holds the output of the selection circuit; and a digital analog conversion circuit (106) that generates a compensation signal on the basis of the output of the second latch circuit, wherein the output of the selection circuit is supplied to the digital analog conversion circuit via the second latch circuit, and thereby the delay of the compensation signal is shortened and a feedback timing to the addition circuit is relaxed.
Inventors:
SUZUKI DAISUKE (JP)
KUDO MASAHIRO (JP)
KUDO MASAHIRO (JP)
Application Number:
PCT/JP2016/069441
Publication Date:
January 04, 2018
Filing Date:
June 30, 2016
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H04L25/03; H04B3/06
Foreign References:
| JP2007525061A | 2007-08-30 | |||
| JPH11261461A | 1999-09-24 | |||
| JPH01258511A | 1989-10-16 | |||
| JPH04230112A | 1992-08-19 | |||
| JPH09326728A | 1997-12-16 | |||
| JP2015192200A | 2015-11-02 | |||
| JP2000049664A | 2000-02-18 |
Other References:
See also references of EP 3480962A4
Attorney, Agent or Firm:
KOKUBUN, Takayoshi (JP)
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