Title:
EQUALIZING FILTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO2006028288
Kind Code:
B1
Abstract:
An equalizing filter circuit comprising an input terminal (101); an output terminal (102); multistage delay elements (104) connected to the input terminal (101); and a plurality of weighting circuits (105) branching from the multiple delay elements; wherein output signals from the weighting circuits (105) are combined. The equalizing filter circuit is arranged such that the gain adjustment of the weighting circuits that decides the coefficient of the equalizing filter circuit can be set independently of a load connected to the output terminal, thereby increasing the amount of waveform distortion compensation. For this purpose, an impedance converting circuit (108) is connected between at least one of the weighting circuits (105) and the output terminal (102).
Inventors:
WADA SHIGEKI (JP)
SUZUKI YASUYUKI (JP)
SUZUKI YASUYUKI (JP)
Application Number:
PCT/JP2005/017077
Publication Date:
May 04, 2006
Filing Date:
September 09, 2005
Export Citation:
Assignee:
NEC CORP (JP)
WADA SHIGEKI (JP)
SUZUKI YASUYUKI (JP)
WADA SHIGEKI (JP)
SUZUKI YASUYUKI (JP)
International Classes:
H04B3/04; H03H15/00
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