Title:
REDUCED‐PASS ERASE VERIFY FOR NONVOLATILE STORAGE MEDIA
Document Type and Number:
WIPO Patent Application WO/2020/132848
Kind Code:
A1
Abstract:
A storage array includes multiple wordlines of storage cells that can be selectively charged to an erase voltage or an inhibit voltage. Control logic associated with the storage array can perform erase verify in stages. On a first erase verify pass, the control logic can set wordlines of an erase block or subblock to a first erase voltage. On a second erase verify pass, the control logic can trigger a second erase verify pulse and set passing wordlines to an inhibit voltage, and failing wordlines to a second erase voltage higher than the first voltage. Inhibiting the already passing wordlines can reduce threshold voltage differences among the wordlines.
Inventors:
HOU CHUNYUAN (CN)
LIANG KE (CN)
XU JUN (CN)
LI SI (CN)
LIANG KE (CN)
XU JUN (CN)
LI SI (CN)
Application Number:
PCT/CN2018/123344
Publication Date:
July 02, 2020
Filing Date:
December 25, 2018
Export Citation:
Assignee:
INTEL CORP (US)
HOU CHUNYUAN (CN)
LIANG KE (CN)
XU JUN (CN)
LI SI (CN)
HOU CHUNYUAN (CN)
LIANG KE (CN)
XU JUN (CN)
LI SI (CN)
International Classes:
G11C16/14
Foreign References:
| CN104051012A | 2014-09-17 | |||
| CN105551524A | 2016-05-04 | |||
| CN102428520A | 2012-04-25 | |||
| US20150262686A1 | 2015-09-17 | |||
| KR20090120678A | 2009-11-25 |
Attorney, Agent or Firm:
SHANGHAI PATENT & TRADEMARK LAW OFFICE, LLC (CN)
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