Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ERROR CORRECTING CODE DECODING DEVICE, ERROR CORRECTING CODE DECODING METHOD AND ERROR CORRECTING CODE DECODING PROGRAM
Document Type and Number:
WIPO Patent Application WO/2011/111654
Kind Code:
A1
Abstract:
Disclosed is an error correcting code decoding device capable of efficiently performing decoding processing for a variety of interleaver sizes while suppressing increase in the size of the device. The error correcting code decoding device is provided with a simultaneous decoding selection unit for selecting whether or not to simultaneously decode component codes 1 and 2 according to the size of an interleaver; a received information storage unit for storing received information at a position corresponding to the selection result of the simultaneous decoding selection unit; an external information storage unit for storing external information corresponding to each of component codes 1 and 2 at positions corresponding to the selection result of the simultaneous decoding selection unit; and a soft-in soft-output decoding unit comprising a plurality of soft-in soft-output decoders for executing in parallel soft-in soft-output decoding for each block into which the component codes 1 and 2 have been partitioned, wherein if simultaneous decoding has not been selected, decoding of the component code 1 and decoding of the component code 2 are sequentially executed and repeated, and if the simultaneous decoding has been selected, the component codes 1 and 2 are simultaneously decoded and the process is repeated.

Inventors:
OKAMURA Toshihiko (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Application Number:
JP2011/055224
Publication Date:
September 15, 2011
Filing Date:
March 07, 2011
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORPORATION (7-1 Shiba 5-chome, Minato-ku Tokyo, 01, 〒1088001, JP)
日本電気株式会社 (〒01 東京都港区芝五丁目7番1号 Tokyo, 〒1088001, JP)
International Classes:
H03M13/29; H03M13/27; H03M13/45
Foreign References:
JP2010050634A2010-03-04
JP2009095008A2009-04-30
Other References:
CHENG-CHI WONG ET AL.: "Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 45, no. 2, February 2010 (2010-02-01), pages 422 - 432, XP011301268, DOI: doi:10.1109/JSSC.2009.2038428
Attorney, Agent or Firm:
NAGAI Michio et al. (LOGOS Patent Attorneys Office, Landic Toranomon Bldg. 7-10, Toranomon 3-chome, Minato-k, Tokyo 01, 〒1050001, JP)
Download PDF:
Claims: