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Title:
ERROR CORRECTION HARDWARE WITH FAULT DETECTION
Document Type and Number:
WIPO Patent Application WO/2018/039156
Kind Code:
A1
Abstract:
In described examples, error correction code (ECC) hardware includes write generation (Gen) ECC logic (115b) and a check ECC block (120b) coupled to an ECC output of a memory circuit (130) with read Gen ECC logic (120b1) coupled to an XOR circuit (120b2) that outputs a syndrome signal to a syndrome decode block (120c) coupled to a single bit error correction block (120d). A first MUX (115a) receives the write data and is in series with an input to the write Gen ECC logic (115b), or a second MUX (120e) receives the read data from the memory circuit (130) in series with an input of the read Gen ECC logic (120b1). A cross-coupling connector (150, 150') couples the read data from the memory circuit (130) to a second input of the first MUX (115a), or couples the write data to a second input of the second MUX (120e). An ECC bit comparator (135) compares an output of the write Gen ECC logic (115b) to the read Gen ECC logic output (120b1).

Inventors:
JALAN, Saket (B-413, Aristocrat Appartment Kasturi Nagar, Bangalore 3, 560043, IN)
PRATHAPAN, Indu (Shriram Samrudhhi, Varthur Main RoadThubrahalli, Bangalore 6, 560066, IN)
KARKISAVAL, Abhishek, Ganapati (C-201, Samhita Sarovar Horamavu Agara Road,Horamavu, Bangalore 3, 560043, IN)
Application Number:
US2017/047890
Publication Date:
March 01, 2018
Filing Date:
August 22, 2017
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INCORPORATED (P.O. Box 655474, Mail Station 3999Dallas, TX, 75265-5474, US)
TEXAS INSTRUMENTS JAPAN LIMITED (24-1, Nishi-shinjuku 6-chomeShinjuku-ku, 160-8366, JP)
International Classes:
G06F11/16; B60W30/00; G11C29/42
Domestic Patent References:
WO2015160859A12015-10-22
Foreign References:
US20030009721A12003-01-09
US9081568B12015-07-14
US5488691A1996-01-30
US20030088805A12003-05-08
US20090055602A12009-02-26
Attorney, Agent or Firm:
TEXAS INSTRUMENTS INCORPORATED et al. (DAVIS, Michael A. Jr.,P.O. Box 655474, Mail Station 399, Dallas TX, 75265-5474, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. Error correction code (ECC) hardware for a single port memory circuit, comprising: write path circuitry including write generation (Gen) ECC logic for generating first ECC bits from write data and for writing the first ECC bits and the write data to the memory circuit; read path circuitry including a check ECC block for coupling read data from the memory circuit comprising read Gen ECC logic coupled to an XOR circuit that has an input for coupling to an ECC output of the memory circuit, wherein an output of the XOR circuit provides a syndrome signal to a syndrome decode block coupled to a single bit error correction (SEC) block and for generating a multi-bit error detection (MED) interrupt signal;

a first multiplexer (MUX) having a first input for receiving the write data in series with an input to the write ECC generation logic or a second MUX having a first input for receiving the read data from the memory circuit in series with an input of the read Gen ECC logic;

a cross-coupling connector for coupling the read data from the memory circuit to a second input of the first MUX or a cross-coupling connector for coupling the write data to a second input of the second MUX, and

an ECC bit comparator for comparing an output of the write Gen ECC logic to an output of the read Gen ECC logic.

2. The ECC hardware of claim 1, wherein an output of the comparator is coupled as an enable input to the syndrome decode block and as an enable input to the SEC block.

3. The ECC hardware of claim 1, wherein the ECC hardware and the single port memory circuit are formed on a common substrate having at least a semiconductor surface.

4. The ECC hardware of claim 1, wherein the ECC hardware includes the first MUX and the second MUX.

5. Error correction code (ECC) hardware for a single port memory circuit, comprising: write path circuitry including write generation (Gen) ECC logic for generating first ECC bits from write data and for writing the first ECC bits and the write data to the memory circuit; read path circuitry including a check ECC block for coupling read data from the memory circuit comprising read Gen ECC logic coupled to an XOR circuit that has an input for coupling to an ECC output of the memory circuit, wherein an output of the XOR circuit provides a syndrome signal to a syndrome decode block coupled to a single bit error correction (SEC) block and for generating a multi-bit error detection (MED) interrupt signal;

a first multiplexer (MUX) having a first input for receiving the write data in series with an input to the write ECC generation logic and a second MUX having a first input for receiving the read data from the memory circuit in series with an input of the read Gen ECC logic;

a cross-coupling connector for coupling the read data from the memory circuit to a second input of the first MUX and a cross-coupling connector for coupling the write data to a second input of the second MUX;

an ECC bit comparator for comparing an output of the write Gen ECC logic received to an output of the read Gen ECC logic.

6. The ECC hardware of claim 5, wherein an output of the comparator is coupled as an enable input to the syndrome decode block and as an enable input to the SEC block.

7. The ECC hardware of claim 5, wherein the ECC hardware and the single port memory circuit are formed on a common substrate having at least a semiconductor surface.

8. A method of fault detection for error correction code (ECC) hardware for a single port memory circuit having write generation (Gen) ECC logic in a write path circuitry and check ECC logic including read Gen ECC logic in read path circuitry, comprising:

comparing an output of the read Gen ECC logic to an output of the write Gen ECC logic; detecting a fault in the write Gen ECC logic or in the read Gen ECC logic when a comparison output from the comparing determines a value of the output of the write Gen ECC logic does not equal a value of the output of the read Gen ECC logic, and

wherein when the fault is a single-bit error correcting the single-bit error, and when the fault is a multi-bit error sending a multi-bit error interrupt signal.

9. The method of claim 8, wherein the read path circuitry further comprises an XOR circuit coupled to an output of the read Gen ECC logic that has another input coupled to an ECC output of the memory circuit, and wherein an output of the XOR circuit provides a syndrome output to a syndrome decode block coupled to a single bit error correction (SEC) block and multi-bit error generation circuitry,

further comprising coupling the comparison output as an enable input of multiple bit error detection (MED) circuitry and as an enable input of SEC block.

10. The method of claim 8, wherein the comparing and the detecting is performed continuously for every clock cycle.

11. The method of claim 8, wherein the single port memory circuit comprises a static random access memory (SRAM), read only memory (ROM), or a flash memory.

12. The method of claim 8, wherein the single port memory circuit is a memory for a processor of an advanced driver assistance system (ADAS).

13. An advanced driver assistance system (ADAS) system, comprising:

an image sensor for generating image data from a scene;

an image recognition system coupled to receive the image data from the image sensor including a video recognition processor and a transceiver; and

a processor block including a processor core coupled to the image recognition system, the processor core coupled to use at least one ECC memory circuit that includes ECC memory hardware and single port processor memory;

the ECC memory hardware comprising: write path circuitry including write generation (Gen) ECC logic for generating first ECC bits from write data and for writing the first ECC bits and the write data to the processor memory; read path circuitry including a check ECC block for coupling read data from the processor memory comprising read Gen ECC logic coupled to an XOR circuit that has an input for coupling to an ECC output of the processor memory, wherein an output of the XOR circuit provides a syndrome signal to a syndrome decode block coupled to a single bit error correction (SEC) block and for generating a multi-bit error detection (MED) interrupt signal; a first multiplexer (MUX) having a first input for receiving the write data in series with an input to the write ECC generation logic or a second MUX having a first input for receiving the read data from the processor memory in series with an input of the read Gen ECC logic; a cross-coupling connector for coupling the read data from the memory circuit to a second input of the first MUX or a cross-coupling connector for coupling the write data to a second input of the second MUX, and an ECC bit comparator for comparing an output of the write Gen ECC logic to an output of the read Gen ECC logic.

14. The ADAS system of claim 13, wherein an output of the comparator is coupled as an enable input to the syndrome decode block and as an enable input to the SEC block.

15. The ADAS system of claim 13, wherein the ECC memory hardware and the processor memory are formed on a common substrate having at least a semiconductor surface.

16. The ADAS system of claim 13, wherein the ECC memory hardware includes the first MUX and the second MUX.

17. The ADAS system of claim 13, wherein the processor memory comprises a static random access memory (SRAM), read only memory (ROM), or a flash memory.

18. The ADAS system of claim 13, wherein the ECC memory hardware and the processor memory are formed on a common substrate having at least a semiconductor surface.

19. The ADAS system of claim 18, wherein common substrate and the semiconductor surface both comprise silicon.

20. The ADAS system of claim 13, wherein the image sensor comprises a color camera.

Description:
ERROR CORRECTION HARDWARE WITH FAULT DETECTION

[0001] This relates generally to error correction codes (ECCs), and more particularly to hardware for fault detection of ECC logic circuitry.

BACKGROUND

[0002] Error correction code (ECC) memory is a type of computer data storage that can detect and correct most conventional types of internal data corruption. ECC memory circuits may be used in computers where data corruption cannot generally be tolerated, such as for scientific or for automotive memories for safety critical advanced driver assistance systems (ADAS) which need to comply with functional safety requirements.

[0003] Implementing ECC on memories (e.g., static random access memory (SRAM), read only memory (ROM), or flash memory) is a standard safety mechanism used in safety critical applications to ensure data integrity within the memories. Conventionally, ECC redundant bits (e.g., in a Hamming code) are added to the memory data contents by write path ECC logic circuitry and written together in the same cycle to the memory in order to provide checking of the data stored in the memory when the memory is read out by read path ECC logic circuitry. The ECC as used herein is for single bit error correction for single bit errors and a multi-bit error detection for multi-bit errors (e.g., double bit errors), generally using redundant bits in a Hamming code.

[0004] Conventionally, generate ECC hardware units are provided in the write path and in the read path, with a generate ECC unit in the write path, and with a check ECC block including another generate ECC unit in the read path. The write path circuitry and read path circuitry have no cross coupling connections and thus operate independently from one another. During a memory read operation, the ECC is re-recomputed by the check ECC block which is compared with the stored ECC by an XOR circuit. The result (output) of this XOR circuit is called the syndrome. If the syndrome is zero, no error has occurred. If the syndrome is non-zero, it can be used to index a table to a "Syndrome decode" to determine which bits are in error in case of a single bit error correction (SEC), or that the error is uncorrectable in case of a double bit error detection (DED). Accordingly, conventional ECC memory can generally maintain a memory system effectively free from most bit errors.

SUMMARY

[0005] In described examples, lockstep ECC circuit hardware comprises an error correction circuit that uses cross-coupled connections between the write path circuitry and read path circuitry, which enables the reuse of ECC generation logic on one side of the memory circuit to check for errors on the other side, thus reducing the ECC logic requirement and saving significant semiconductor chip area. Described examples include a method of fault detection for ECC circuitry for a memory circuit having write generation (Gen) ECC logic in a write path circuitry and check ECC logic including read Gen ECC logic in read path circuitry. An output of the read Gen ECC logic and an output of the write Gen ECC logic are compared by a digital comparator to check whether the respective bits strings match. A fault in the write Gen ECC logic or in the read Gen ECC logic is detected when the bits strings do not match. In case of a lockstep error (mismatch in comparator output) during the write operation, the write operation can be repeated. In case of a lockstep error during the read operation, the single bit errors can be corrected, and a multi-bit error interrupt signal can be sent.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a block diagram of an example ECC memory circuit having described lockstep ECC circuit hardware for fault detection in the read side ECC logic having a multiplexer with a first input for receiving write data in series with an input to the ECC generation logic, according to an example embodiment. Write data is selected during a normal write operation, and read data is selected during the read operation.

[0010] FIG. 2 is a block diagram of another example ECC memory circuit having described lockstep ECC circuit hardware for fault detection in write side ECC logic having a multiplexer with a first input for receiving the read data from the memory circuit in series with an input of the Gen ECC logic for fault detection in the ECC logic, according to an example embodiment.

[0011] FIG. 3 is a flow chart that shows steps in an example method of fault detection for ECC circuitry, according to an example embodiment.

[0012] FIG. 4 is example ECC memory circuit including described ECC hardware for fault detection in its read path and write path that essentially combines the read side and write side error checking embodiments described hereinabove relative to FIG. 1 and FIG. 2, according to an example embodiment. [0013] FIG. 5 is a system diagram of an example ADAS system including two instances of the described ECC memory circuit shown in FIG. 4 as processor memory having described lockstep ECC circuit hardware for fault detection in the ECC logic in its read path and write path, according to an example embodiment.

DETAILED DESCRIPTION OF EXAMPLE EMB ODFMENT S

[0014] The drawings are not necessarily drawn to scale. In the drawings, like reference numerals designate similar or equivalent elements. Some illustrated acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events are optional to implement a methodology in accordance with this description.

[0015] As used herein without further qualification, the terms "coupled to" or "couples with" (and the like) describe either an indirect or direct electrical connection. Thus, if a first device "couples" to a second device, that connection can be through a direct electrical connection where only parasitics are in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal, but may adjust its current level, voltage level and/or power level.

[0016] In ECC logic hardware of ECC memory circuits, transient or permanent errors can exist in the write side, which can result in wrong ECC bits being written into the memory during the write operation. Transient or permanent errors in the ECC logic hardware in the read side of ECC memory circuits can result in corruption of memory read data or in the wrong flagging of memory read data as corrupted when the read data is in fact not corrupted. If write path circuitry and read path circuitry operate independently, then detection of transient/permanent errors in the ECC logic of ECC memory circuits may be possible, but implementation of such detection would require significant additional logic, including extra ECC generation logic on both sides of the ECC memory circuit.

[0017] FIG. 1 shows an ECC memory circuit 100 including a memory circuit 130 (e.g., SRAM, ROM, or a flash memory chip) and described "lockstep" ECC hardware 110 having fault detection in its ECC logic circuitry configured for verifying the bit output of the read path Gen ECC 120bi in the read path circuitry 120. The memory circuit 130 comprises a single port memory where only one operation (read or write) can be performed for a given clock pulse. This single port memory feature enables the bit output from one of the ECC GEN logics (the side that is not active at the particular time/clock, write not being active as shown in FIG. 1, and read not being active as shown in FIG. 2) to be available as a reference to enable described lockstep error detection.

[0018] The memory circuit 130 includes a common substrate 105 having at least a semiconductor surface. For example, the substrate 105 can comprise a bulk silicon substrate, or an epitaxial layer on a bulk silicon substrate.

[0019] The memory circuit 130 has a separate data output and a separate ECC output. Data shown as k bits is stored along with ECC bits shown as r bits. For example, if a non-ECC memory stores 64 bits of data, then an ECC memory will store the same 64 bits of data with an extra 8 bits of ECC. Hence 64+8 bits are written and 64+8 bits are read out. The ECC 8 bits are used to validate the 64 data bits, and goes to the XOR logic in the Check ECC.

[0020] Write path circuitry 115 includes write Generation (Gen) ECC logic 115b, and check ECC logic 120b includes read Gen ECC logic 120bi in the read path circuitry 120. While operating in the write mode (write mode is active in FIG. 2 described hereinbelow), data bits (shown as WR data, such as 64 bits) and the corresponding computed ECC bits (such as 8 bits) from the write ECC Gen logic 115b are each written into the memory circuit 100 in the same clock cycle. In FIGs. 1 and 2 the data width for the memory circuit 130 can in one example be 72 bits (72 bit wide memory) including 64 bits (data) +8 bits (ECC), which can be realized as two separate memories of width 64 and width 8, or be a single 72 bit wide memory.

[0021] As described hereinabove, 64 information/data bits and 8 ECC bits are only examples. The actual number of ECC bits can be based on the corresponding bit width for data (information), such as given in the following example:

[0022] A multiplexer (Mux) 115a is provided at the input of write GEN ECC logic 115b to multiplex in cross-coupled read data provided by cross-coupled connection 150 shown as k bits from the memory circuit 130 with the write (wr) data generally from a processor. The processor can comprise a microprocessor, digital signal processor (DSP), or a microcontroller unit (MCU). The Mux 115a is shown having a select line that is shown based on the memory circuit 130 being in the read mode from a processor which is used to select which of the input lines comprising the rd data from the memory on one line and the wr data on the other line to send to the Mux's 115a output. When in the read mode, the rd data is selected by Mux 115a, while when in the write mode, the wr data is selected.

[0023] A digital comparator 135 is coupled to receive at one input the output from write Gen ECC logic 115b (as a reference as it is inactive during reading) and at its other output the output of the read path Gen ECC 120bi. Digital comparator 135 thus reuses the output from write Gen ECC logic 115b for verifying the bit output of the read path Gen ECC 120bl, both shown only as an example as being 8 bits. Read Gen ECC 120b 1 together with an XOR circuit 120b2 constitute the check ECC block 120b. The output of the XOR circuit 120b2 provides "syndrome" signal to the syndrome decode block 120c. If the syndrome is zero, no error has occurred. If the syndrome is non-zero, the syndrome decode block 120c determines which bits are in error (SEC), or that the error is uncorrectable (e.g., the error is a double bit error). Single bit errors are provided to the SEC block 120d, which outputs corrected read data shown as rd data.

[0024] For ECC hardware 110, the output of the digital comparator 135 is connected as an enable to the multi-bit (2 or more) error interrupt generation and as an enable to the SEC block 120d. Thus SEC of memory read data by SEC block 120d and multi-bit error flagging using the syndrome computation provided by syndrome decode 120c are both enabled by the enable signal from the digital comparator 135 if and only if the ECC computations in the write path and the ECC computations in the read path match one another (shown in FIG. 1 as the same r bits). If the ECC computations in the write path and the ECC computations in the read path do not match one another so that a lockstep error exists during read operation, and single bit errors can be corrected and in the case of a multi-bit errors such as double bit errors, a bit error interrupt (disable) signal can be sent.

[0025] FIG. 2 shows an example ECC memory circuit 200 including described ECC hardware 110' for fault detection in its write path including write Gen ECC logic 115b, where a MUX 120e is added in the read path circuitry 120' and a cross-coupled connection 150' is added from the write path circuitry 115' to the MUX 120e in the read path circuitry 120' to mux the write data to data read from the memory circuitl30. Here, the described lockstep ECC hardware 110 having fault detection in its ECC logic circuitry is configured for verifying the bit output of the write Gen ECC logic 115b while the write mode is active. A control input shown as a "memory write" is the control signal which controls the MUX's 120e input selection node. When in the write mode, the wr data is selected by MUX 120e, while when in the read mode, the rd data is selected.

[0026] ECC bits output by the read Gen ECC logic 120b 1 is used to verify operation of the write Gen ECC logic 115b by digital comparator 135 which compares the ECC bits generated by the respective Gen ECC logics 115b and 120bi. The output of the digital comparator 135 that is generated is used as an interrupt to a processor (e.g., a microprocessor, digital signal processor (DSP), or a microcontroller unit (MCU)) to repeat the write transaction. In case of an error being flagged by the digital comparator 135 during a write operation, the write operation can be repeated to ensure that the data written into the memory circuit 130 is not in error. Repeating the write will generally fix the hardware error problem if the error is a transient fault. In case of a permanent fault, the digital comparator 135 will again keep generating an error in which case the processor can take appropriate action such as indicating to the application software that a permanent fault has occurred in the system. This same fault response is true in case of a read operation also.

[0027] FIG. 3 is a flow chart that shows steps in an example method 300 of fault detection for ECC circuitry associated with a single port memory circuit, according to an example embodiment. Step 301 comprises comparing an output of read Gen ECC logic (120bi in FIG. 1 and FIG. 2) to an output of a write Gen ECC logic (115b in FIG. 1 and FIG. 2). Step 302 comprises detecting a fault in the write Gen ECC logic or in the read Gen ECC logic when a comparison output from the comparing determines a value of the output of the write Gen ECC logic does not equal a value of the output of the read Gen ECC logic 120bi.

[0028] Step 103 comprises when the fault is a single-bit error during a read operation, correcting the single-bit error, and when the fault is a multi-bit error during a read operation, sending a multi-bit error interrupt signal. When the fault is an error during a write operation, repeating the writing. As described hereinabove for memory circuit 100 of FIG. 1 implementing fault detection in the read side, single bit errors are provided to the SEC block 120d, which outputs corrected read data shown as rd data. As described hereinabove for memory circuit 200 of FIG. 2 implementing fault detection in the write side, the write operation can be repeated to ensure that the data written into the memory chip is not in error.

[0029] The embodiments described hereinabove relative to FIG. 1 (write side error checking) and FIG. 2 (read side error checking) may be independently practiced (one without the other) to detect errors on one side of the memory circuit 130. Alternatively, the read side and write side error checking embodiments described hereinabove relative to FIG. 1 and FIG. 2 may be combined together to enable error checking on both sides of the memory circuit 130.

[0030] FIG. 4 is example ECC memory circuit 400 including described ECC hardware 110" for fault detection in both its read path and write path that essentially combines the read side and write side error checking embodiments described hereinabove relative to FIG. 1 and FIG. 2. Besides Mux 115a ECC memory circuit 400 includes a second Mux 120e having a first input for receiving read data from the memory circuit 400 in series with an input of the read Gen ECC logic 120b 1 and a cross-coupled connection 150' for coupling the write data to the second input of the second MUX 120e. Here the digital comparator 135 is involved in both read side error checking and write side error checking.

[0031] In contrast to ECC memory circuits described herein, conventional ECC logic is used only to detect and correct internal memory (e.g., RAM) errors. For ECC memory circuits having ECC logic described herein, fault detection in the ECC logic is achieved in addition to detection and correction of internal memory errors, where any transient/permanent errors in the ECC computation and generation logic are also detected, which enables corrective action to be taken. As described hereinabove, in the case of a lockstep error of the read Gen ECC 120bi (see FIG. 1), the single bit error can be corrected and a multi-bit error interrupt signal can be generated. In case of a lockstep logic in error in the write Gen ECC logic 115b (see FIG. 2), the write operation is repeated. Moreover, described lockstep ECC circuit hardware is non-intrusive and can operate continuously (on every clock cycle, on-the fly) for checking memory ECC logic with only a limited area penalty in terms of additional Muxs and comparators.

[0032] Described embodiments are further illustrated by the following examples. FIG. 5 is a system diagram of an example ADAS system 500 including two instances of the described ECC memory circuit shown in FIG. 4 shown as 400 1 and 400 2 including processor memory 130i (shown as processor memory 1) and 130 2 (shown as processor memory N). The ECC memory circuits have described lockstep ECC circuit hardware shown as ECC logic l lOi and 110 2 for fault detection in the read path and write path of the processor memory. An image sensor 505 (e.g. a CMOS color camera) generates image data from a scene (e.g., from a rear-view from an automobile). The image data is coupled to an image recognition system 515 by a camera interface 510. Image recognition system 515 is shown including a video recognition processor 515a, flash memory 515b, external DDR memory 515c, and a controller area network (CAN) bus Tx/Rx (transceiver) 515d.

[0033] The image recognition system 515 is coupled by a CAN bus 520 to the processor block 530 that includes a processor core 530a. Processor core 530a is shown coupled by a bus interface 535 to use the processor memory 130i and 130 2 of ECC memory circuits 4001 and 400 2 . As described hereinabove, during operation of ADAS system 500, ECC memory circuits 400i and 400 2 use described lockstep ECC circuit hardware with cross-coupled connections between the write path circuitry and read path circuitry, which enables the reuse of ECC generation logic on one side of the processor memory to check for errors on the other side, and which reduces the ECC logic requirement and saves significant semiconductor chip area.

[0034] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.