Title:
ERROR CORRECTION PROTECTION ARCHITECTURE AND METHOD APPLIED TO RESISTIVE RANDOM ACCESS MEMORY CACHE OF SOLID STATE DISK
Document Type and Number:
WIPO Patent Application WO/2017/000517
Kind Code:
A1
Abstract:
An error correction protection architecture and method applied to a resistive random access memory cache of a solid state disk. A mapping table under coarse granularity management has the same code length as that of page cache data, and during the procedure of data processing, mapping table address information having an access frequency greater than a preset value, in the mapping table under coarse granularity management, is stored into a mapping table cache under fine granularity management; exchange data between the mapping table cache under fine granularity management and the mapping table under coarse granularity management is in units of pages; a page of mapping table information read out from the mapping table under coarse granularity management is completely put into the mapping table cache under fine granularity management, the posterior ten bits in an input logic address request are taken as offset bits, and the remaining bits in the input logic address are taken as index bits. With the error correction protection architecture, the mapping table address information can be obtained and read out efficiently and reliably, and the consumed redundant space is limited.
Inventors:
SUN HONGBIN (CN)
YANG YANG (CN)
ZHANG RUIZHI (CN)
ZHENG NANNING (CN)
YANG YANG (CN)
ZHANG RUIZHI (CN)
ZHENG NANNING (CN)
Application Number:
PCT/CN2015/098137
Publication Date:
January 05, 2017
Filing Date:
December 21, 2015
Export Citation:
Assignee:
UNIV XIAN JIAOTONG (CN)
International Classes:
G06F12/10
Foreign References:
| CN105005510A | 2015-10-28 | |||
| CN103176916A | 2013-06-26 | |||
| CN104166634A | 2014-11-26 | |||
| CN104268094A | 2015-01-07 | |||
| US20090106486A1 | 2009-04-23 |
Attorney, Agent or Firm:
XI'AN TONG DA PATENT AGENCY CO., LTD. (CN)
Download PDF: