Title:
ERROR CORRECTION SYSTEM
Document Type and Number:
WIPO Patent Application WO/1981/000641
Kind Code:
A1
Abstract:
Error correction system in which a (n + 1) bit error including software and hardware errors is shifted down in level to a n-bit error. The error correction system (12), which is disposed between a memory (11) and a CPU (13), comprises an alternate bit memory (121), an ECC (error correction code) logic circuit (122), a switching circuit (123), and a correction control circuit (124). The ECC logic circuit (122) is adapted to detect the occurrence of software and hardware errors. If a hardware error occurs in the memory (11), the defective memory cell located in the memory (11) is switched over to the alternate bit memory (12) by the switching circuit (123). Data to be stored in the alternate bit memory (121) is validated by the circuits (122), (123) and (124). The above arrangement allows a reduction in level with respect to a multi-bit error.
Inventors:
TAKAHASHI M (JP)
NAGANO G (JP)
NAGANO G (JP)
Application Number:
PCT/JP1980/000199
Publication Date:
March 05, 1981
Filing Date:
August 29, 1980
Export Citation:
Assignee:
FUJITSU LTD (JP)
TAKAHASHI M (JP)
NAGANO G (JP)
TAKAHASHI M (JP)
NAGANO G (JP)
International Classes:
G06F11/08; G06F11/10; G06F11/16; G06F12/16; G11C29/00; (IPC1-7): G06F11/16; G06F11/08; G11C29/00
Foreign References:
| JPS51137335A | 1976-11-27 | |||
| US3949208A | 1976-04-06 |
Other References:
JOHO SHORI, Vol. 16, No. 4 FUJIWARA EIJI, AOKI KATSUHIKO "Main Memory no Shinraisei" P.296-301
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