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Patent Searching and Data


Title:
ERROR EXTRACTION METHOD FOR FOREGROUND DIGITAL CORRECTION OF PIPELINE ANALOG-TO-DIGITAL CONVERTER
Document Type and Number:
WIPO Patent Application WO/2020/211480
Kind Code:
A1
Abstract:
An error extraction method for foreground digital correction of a pipeline analog-to-digital converter comprising: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of the i-th pipeline stage, configuring a magnitude of the input signal according to formula (I); locking the outputs of all previous-stage comparators before the i-th stage of the pipeline analog-to-digital converter; and completing, according to raw output code of the pipeline analog-to-digital converter, error extraction by means of sequential adaptive iteration, stage-by-stage, from a last stage to a first stage of a pipeline. During error quantization, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error of each stage of the pipeline, a gain bandwidth error, and a kickback error without any additional circuit, thereby saving on resources, realizing accurate error quantization, and accordingly facilitating digital correction of pipeline analog-to-digital converters.

Inventors:
ZHANG YONG (CN)
LI TING (CN)
HUANG ZHENGBO (CN)
NI YABO (CN)
FU DONGBING (CN)
Application Number:
PCT/CN2020/070599
Publication Date:
October 22, 2020
Filing Date:
January 07, 2020
Export Citation:
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Assignee:
NO 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECH GROUP CORPORATION (CN)
CHONGQING GIGACHIP TECH CO LTD (CN)
International Classes:
H03M1/10
Foreign References:
CN110061743A2019-07-26
CN107453756A2017-12-08
CN107359878A2017-11-17
US6838937B22005-01-04
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (GENERAL PARTNERSHIP) (CN)
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