Cross-Reference to Related Applications

[0001] The present application claims priority from Australian Provisional Patent Application 2022900597 filed on 11 March 2022, the contents of which are incorporated herein by reference in their entirety.

Technical Field

[0002] This disclose relates to compiling a quantum algorithm onto a quantum hardware using error correction.

Background

[0003] Quantum computers offer immense opportunities for solving problems that are intractable by existing classical hardware based on binary bits. Quantum computers use quantum bits (“qubits”), which can hold a superposition of states and can be entangled.

[0004] However, one major roadblock in the path to widespread use of quantum computers is that the qubits are relatively unstable, which means their quantum state is lost too quickly for most practical computations. Quantum error correction codes, such as the surface code, consume additional resources to provide protection against errors, and use more qubits than are currently available making them difficult to implement.

[0005] Dynamic error suppression is another approach to stabilise the quantum state on a qubit. This involves individual operations that effectively correct errors without requiring additional qubits. It may be called dynamic decoupling when referring to idling qubits (memory), or dynamically corrected gates when applied to the active manipulation of one or more qubits. Dynamic error suppression is deterministic in that it does not require additional resources such as multiple measurement runs which must be combined in order to gain a benefit. While dynamic error suppression can be performed successfully on a single qubit, or an isolated pair of qubits it is difficult to apply dynamic error suppression on an entire quantum circuit having multiple qubits that implement a quantum algorithm.

[0006] Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present disclosure as it existed before the priority date of each of the appended claims.

[0007] Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.

Summary

[0008] Provided herein are methods for generating, from a quantum algorithm, a quantum circuit that is error robust. The methods determine a characteristic of a quantum hardware that is used to implement the quantum algorithm and informs the deterministic dynamic error suppression routine to be implemented. The methods also consider the compiled quantum circuit because that provides the information about the context of the operations performed on the qubits, which is an important factor in the fidelity of the quantum gates and ultimately the success of the algorithm. The methods then use the characteristic and the context to apply deterministic error correction.

[0009] A method for generating an error-corrected quantum circuit comprises: compiling a quantum algorithm onto a quantum hardware using multiple qubits to generate a quantum circuit; determining a quantum relationship between the multiple qubits and between the multiple qubits and an external environment as a result of implementing the quantum circuit on the quantum hardware; and using the quantum relationship between the multiple qubits and between the multiple qubits and an external environment to determine a deterministic error correction protocol, specific to the quantum circuit and specific to the quantum hardware, for each of the multiple qubits and for interactions between the multiple qubits.

[0010] In some embodiments, the method further comprises performing multiple measurements on qubits of the quantum hardware to determine an error characterisation of the quantum hardware based on a topology of the quantum hardware.

[0011] In some embodiments, the error characterisation comprising one or more of individual gate errors, decoherence processes, measurement errors, and cross-talk between qubits based on a topology of the quantum hardware.

[0012] In some embodiments, compiling comprises, for each of the multiple logical quantum operations in the quantum algorithm, selecting one or more quantum blocks to realise the quantum algorithm on the quantum hardware, wherein each of the quantum blocks realises the logical function of that logical quantum operation.

[0013] In some embodiments, the method further comprises determining an error correction protocol for each of the quantum blocks, the error correction protocol comprising error correction against errors identified in an error characterisation and being specific for selected one or more quantum blocks to realise the quantum algorithm.

[0014] In some embodiments, the method further comprises executing the quantum algorithm on the quantum hardware using selected quantum blocks and the deterministic error correction protocol to obtain qubit measurements.

[0015] In some embodiments, the method further comprises reducing measurement errors in the qubit measurements by applying an error reduction operation that is based on the error characterisation. [0016] A method for characterising errors in quantum hardware comprising multiple qubits comprises determining groups of qubits to minimize inter-group correlations based on a topology of the quantum hardware; performing multiple measurements to approximate a confusion matrix for individual qubit readouts; and repeating the multiple measurements for the qubit groups to determine the error characterisation of the hardware.

[0017] In some embodiments, the groups of qubits includes qubit pairs with low cross-coupling between pairs.

[0018] In some embodiments, the error characterisation comprises one or more of individual gate fidelities, noise spectra, and crosstalk strengths.

[0019] In some embodiments, the method further comprises using machine learning to automate the determining of the error characterisation.

[0020] In some embodiments, the method further comprises optimizing parameters of quantum gates using the qubits to maximise fidelity of the quantum gates.

[0021] In some embodiments, fidelity is maximized for gates with qubits in the groups in parallel.

[0022] A method for compiling a quantum algorithm onto a quantum hardware having a native gate set comprises repeatedly performing the steps of: performing a first compilation process to map the quantum algorithm onto the quantum hardware and the native gate set; and using the output of the first compilation process as an input for performing a second compilation process, different from the first compilation process, to maximize the use of low-error qubits as identified by an error characterisation process.

[0023] A method for quantum error correction of a quantum hardware comprises: dividing qubits of the quantum hardware into groups based on a topology of the quantum hardware; dividing the qubits into blocks based on a quantum circuit compiled onto the quantum hardware; applying driven single-qubit operations to correct quantum errors arising during identity operations dependent on the quantum circuit compiled onto the quantum hardware; and determining a time shift of the driven single-qubit operations to correct cross coupling for each of the groups during identity operations and the blocks and suppress decoherence.

[0024] In some embodiments, the method further comprises redefining non-identity operations to correct for error processes identified through error characterisation through time-domain modulation of the control signals used to implement the nonidentity operations.

[0025] In some embodiments, the method further comprises modulating control signals in multiple qubits in time in a continuous or discontinuous manner.

[0026] In some embodiments, the method further comprises assembling the blocks from a library of error-corrected quantum gates based on an error characterisation.

[0027] A method for error-correcting compilation to correct error sources identified in an error characterisation process comprises: receiving a compiled circuit compatible with a hardware device topology and gate set; replacing quantum logic gates in the compiled circuit having uncorrected errors over an acceptable threshold with error-corrected alternatives, derived using the error characterisation process; and outputting a definition of the circuit with all replacement gate definitions in a format for hardware execution, including identity and non-identity operations. [0028] In some embodiments, the method further comprises: identifying error-prone non-identity gates; replacing error-prone non-identity gates with auto-calibrated gates; replacing identity gates in the compiled quantum circuit with error-corrected identity gates including an error correction protocol; assembling the output error-robust circuit comprising the auto-calibrated gates and the error-corrected identity gates into a circuit representation for execution on the quantum hardware.

[0029] A method for correcting errors in quantum measurements of a quantum circuit on a quantum hardware comprises: receiving measurement results; using an approximated confusion matrix from an error characterisation to contract a tensor based on the groups of qubits; converting the tensor to a probability distribution; and correcting the errors in the quantum measurements as indicated by the probability distribution; and outputting a measurement-error-corrected result.

[0030] In some embodiments, the method further comprises dividing the quantum circuit into groups of qubits to minimize inter-group correlations based on a topology of the quantum hardware; and permuting an ordering of the tensor based on the groups of qubits.

[0031] In some embodiments, the method further comprises adding dimensions to the tensor for unmeasured qubits.

[0032] In some embodiments, the method further comprises applying a neural network to the measurements to restore correlations neglected by the tensored mitigation, based on an error characterisation.

[0033] An internet server is configured to: offer a web-interface, the web interface comprising input elements to input a quantum algorithm and a characterisation of a quantum hardware; receive the quantum algorithm and the incomplete description of the quantum hardware through the web-interface; perform error characterisation or retrieve an error characterisation previously performed for the target quantum hardware; generate a decorated quantum circuit description that realises the quantum algorithm on the quantum hardware, wherein the decorated quantum circuit description comprises quantum logic blocks that are error corrected based on the characterisation; output the quantum circuit description; and receive and analyse the raw output data from the quantum hardware using the complete characterisation.

[0034] In some embodiments, outputting the quantum circuit description comprises sending the decorated quantum circuit description to the user through the webinterface; or sending the decorated quantum circuit description to the quantum hardware for execution on the quantum hardware.

[0035] In some embodiments, receiving and analysing the raw output data comprises receiving the raw output data from the user through the web-interface for analysis; or receiving the raw output data from the quantum hardware for analysis.

[0036] Optional features provided above with reference to one of the methods or the internet server are equally optional features of the other methods and the internet server.

Brief Description of Drawings

[0037] Fig. 1 illustrates dynamic decoupling (DD) motifs, (a, b) Show two motifs realizing a single qubit DD. As long as the idling time between the two bit flips is equal to the remaining idling time, the effect of phase scrambling is suppressed, (c) Since each bit flip reverse the ZZ effect, the simultaneous application of two flips leave the ZZ coupling unchanged. Therefore, while the motif in (c) suppresses T ₂ effects on both qubits, it does not mitigate the ZZ effect, (d) Combining the two motifs in (a) and (b) leads to ZZ mitigation. Since X gates (bit flips) are not instantaneous, an asymmetry parameter, 8 , can be optimize to achieve the best ZZ cancellation.

[0038] Fig. 2 illustrates an example of a compiled circuit. On the left, a snapshot of a 7-qubit algorithm, already compiled to the native gates available on this device. The disclosed method gets as an input the compiled circuit and the device connectivity, as appears on the right, and returns a decorated circuit with the optimal DD embedded in it.

[0039] Fig. 3 provides an example of the DD embedding. The input circuit, on the top, is a compiled circuit and the output circuit of the disclosed automated scheme, on the bottom, in the original circuit with the optimal DD structure embedded in it. The embedded DD structure comprises X operations at specific times as calculated by the error correction protocol specific for the input circuit and the quantum hardware. It is noted that this figure has been simplified for illustration purposes, which means the temporal (horizontal) location of the DD operations may not be accurate.

[0040] Fig. 4 illustrates an example of groups of four qubits each which minimizes inter-group correlations in the measurement readout.

[0041] Fig. 5 illustrates the success probability of the disclosed methods. A certain number of qubits is prepared, as given by the x-axis, in the 1 1 > state and measure the qubits. The plot illustrates the success probability of measuring the correct bit string. The shallow circuit-depth ensures that decoherence does not affect the success probability. Due to the readout error the success probability rapidly decreases with increasing number of qubits. However, the disclosed tensored mitigation protocol appropriately mitigates the readout error.

[0042] Fig. 6 illustrates an instance of the neural network architecture for measurement error correction on a 7 qubit quantum computer. [0043] Fig. 7 illustrates a comparison of measurement error, denoted by the Hellinger loss, averaged over 2000 random probability distributions on a 7 qubit quantum computer.

[0044] Figs. 8a and 8b compare the different compilation methods using QFT circuits. Method A is a stochastic method, therefore, the figures present 50 instances of the method. The total number of CX gates and the total circuit duration are used as comparison features. As seen, the hybrid method typically find shorter circuits with lower number of entangling gates. While this plot does not demonstrate it, the hybrid method better avoids low quality qubits. In the case above, Q3 has higher SPAM and CX errors than device average. The hybrid method avoid this qubit completely for circuits with less than 11 qubits. As a comparison, for the 10 qubits QFT, 70% of the circuits method A produced contain the problematic qubit.

[0045] Fig. 9 illustrates dividing a quantum circuit so that full device calibration can be done in parallel requiring a fixed number of steps depending on the device connectivity. Heavy-hex topology can be tuned up in only four steps irrespective of the device size.

[0046] Fig. 10 illustrates success probability of a Bemstein-Vazirani algorithm on a 16 qubits device. The black data corresponds to the best compilation available by the hardware provider, the grey data has similar compilation as the black data together with the newest DD scheme and measurement error mitigation available by the hardware provider. The purple data shows the performance using the software tools in this document.

[0047] Fig. 11 illustrates a method for generating an error-corrected quantum circuit.

[0048] Fig. 12 illustrates a method for characterising errors in quantum hardware comprising multiple qubits. [0049] Fig. 13 illustrates a method for compiling a quantum algorithm onto a quantum hardware having a native gate set.

[0050] Fig. 14 illustrates a method for quantum error correction of a quantum hardware.

[0051] Fig. 15 illustrates a method for error-correcting compilation.

[0052] Fig. 16 illustrates a method for correcting errors in quantum measurements

[0053] Fig. 17 illustrates an internet server.

Description of Embodiments

[0054] As mentioned above, the methods disclosed herein relate to quantum algorithms implemented by multiple qubits on a specific quantum hardware. Unlike classical digital computers, where the electronic characteristics are abstracted to stable binary bit values, quantum hardware does not provide this level of abstraction without incurring impractical inaccuracies. This means that each quantum hardware has significantly different characteristics with regards to the qubits. In particular, the relationship between qubits as well as the relationship between the qubits and the environment is different for every different quantum hardware and even for each circuit run on that hardware. As a result, hardware-agnostic error correction leads to unsatisfactory results. Further, error correction that does not take into account the compiled circuit structure, leads to high error rates.

[0055] Dynamic error suppression can be used to stabilise individual qubits or improve the fidelity of an isolated quantum logic gate between a pair of qubits. One example protocol involves the stabilisation of a qubit during an idle time period - this is known as dynamic decoupling. During this period, additional rotations can be applied to the qubit state to cancel out an accumulated error. In a multi -qubit quantum circuit, however, the idle times of the multiple qubits are not the same and the qubits also interact with each other. Therefore, it is difficult to apply individual dynamic decoupling and error correction depends on hardware characteristics as well as the compiled circuit.

[0056] Compilation in this context means the mapping of a quantum algorithm onto a quantum hardware, taking into account the physical operations available and connectivity between different qubits. Such quantum hardware often has a native gate set that may be specific for that quantum hardware, so the compiled quantum circuit uses the available gate set, noting that additional gates may be introduced. Compiling may also involve the optimization of the quantum circuit to reduce the number of gates, for example, via exploitation of mathematical relationships between the gates.

[0057] Similar to an algorithm on a classical computer, a quantum algorithm is a step- by-step procedure, where each of the steps can be performed on a quantum computer. Each step is an operation on a quantum state in the algorithm. During compilation, these steps are mapped to qubit operations, which are referred to as gates. Examples of quantum algorithms include Shor’s algorithm, the Variational Quantum Eigensolver, Grover’s algorithm, and even Quantum Error Correction, but many other quantum algorithms can be implemented using the method disclosed herein. It is noted that the methods disclosed herein are applicable to a wide range of different qubit types, including nitrogen vacancies, trapped ions, silicon qubits, superconducting qubits, and many others.

[0058] It is also noted that the methods disclosed herein are performed by a classical computer. That is, a classical, digital processor, executing software, performs compilation, processes error measurements, optimizes and selects gates, determines error correction protocols, and processes output measurements, etc.

[0059] The usefulness of a quantum computer is ultimately determined by its ability to successfully implement meaningful quantum algorithms. An ideal implementation of a quantum algorithm is not possible on current quantum hardware, however, being able to run algorithms with high success probability may provide a route to quantum advantage in the near future. The quality of a quantum algorithm is affected not only by the quality of the individual building blocks, e.g., the quality of qubits, gates and measurements, but also by global device and algorithm properties such as device topology, multi-qubit correlations and algorithmic structures. This disclosure provides an automated method for the optimization of the different components that eventually affect the quality of the algorithm implementation on a given quantum hardware and the incorporation of deterministic error suppression techniques. The disclosed methods lead to an improvement across different algorithms and quantum devices.

[0060] Overview of invention

[0061] The disclosed protocol is a procedure for enhancing the performance of quantum algorithms on quantum hardware based on deterministic error correction methods. Once the user provides a quantum circuit, through a website or an application programming interface (API), the disclosed protocol preforms a series of optimization and error correction steps and outputs the measured results of the quantum algorithm.

[0062] The workflow of the protocol is as follows-

[0063] • Accept a circuit - Given a quantum circuit, first it is converted into a suitable intermediate representation. This enables robust and hardware-agnostic compilation procedures.

[0064] • Front end compilation - A sequence of compiler passes is used to reduce the depth (gate count) of the quantum circuit.

[0065] • Hardware-specific back-end compilation - The logical operations in the circuit are mapped to the native gates available on the hardware. Additional hardwarespecific compilation passes are executed to account for device topology, gate errors, parallel gate crosstalk, etc.. [0066] • Idling and crosstalk-error reduction by DD decoration - Dynamical decoupling (DD) sequences are incorporated to mitigate various idling errors including dephasing and ZZ crosstalk at the algorithmic level, depending on the characteristics of the device and the circuit returned by the compilers. This disclosure relates to how to automatically incorporate the best DD sequence into an algorithm for execution, rather than specific sequence design.

[0067] • Gate-error reduction by system-wide Al-driven auto-calibration - AI- powered optimizers are used to perform pulse-level gate calibration throughout the quantum computer, including optimizing multiple gates in parallel. These optimal pulses are used to perform higher fidelity gates used in the circuit. There is an advantage in the manner and method of using Al to perform system-wide calibration and automation of gate optimization. The process can be automated in advance of user interaction. In one example, all relevant error-prone gates are replaced by these optimized gates.

[0068] • Execute algorithm on the quantum hardware. The final definition of the circuit is output in a format compatible with hardware execution. This may be accomplished by returning the “new” commands to the user for execution, or via direct connection to a hardware backend (locally or in the cloud).

[0069] • Measurement-error reduction by efficient Al-enhanced readout-error mitigation - The measured probability distribution from the execution of the algorithm on a quantum device contains measurement errors. These errors are corrected in postprocessing using an efficient Al-enhanced measurement-error-mitigation protocol. This disclosure provide an approach as part of the overall workflow which suppresses errors efficiently.

[0070] • Return solution with augmented likelihood of algorithmic success - The

“answer” from the quantum algorithm’s execution is returned with an augmented confidence level of success. [0071] These processes may be integrated into a hardware system locally or connected to a cloud-accessible machine via an API. The user need not incur any direct overhead - a single pass through the toolchain delivers maximum performance. This is an advantage relative to other known approaches to circuit level error suppression.

[0072] These approaches may be used for either direct algorithmic execution or for improving the performance of quantum error correction (QEC). QEC augmented with deterministic circuit-level error suppression through this protocol is an advantage. In addition, improving the performance of quantum algorithms without the need for full quantum error correction is another advantage.

[0073] These approaches are relevant to any quantum computing architecture, and are not specific to a single qubit type.

Background on noise and error processes

[0074] Quantum systems are subjected to various types of noise. These noise processes affect the building blocks of quantum circuits, such as gates and measurements. These operations may be optimized in order to reduce the effect of noise and imperfections. However, standard gate calibration techniques typically keep spectator (non-participating) qubits in the ground state. When applying an algorithm, a more complex context-dependent noise process can arise, resulting in different type of error.

Single-qubit decoherence

[0075] During a multi-qubit algorithm, at any given moment, some qubits are idle. Even in the presence of perfect gates and measurements, for wide and deep circuits, idling errors alone can fully randomize the quantum circuit rendering any quantum algorithm useless.

[0076] The quantum state of a single qubit can be represented by a complex superposition of its internal states, A | 0) + B exp i</> } 1 1) with A ² + B ² < 1 . While quantum gates intentionally steer quantum states towards a desired target, quantum noise and unwanted couplings may steer quantum states as well. For example, noise processes may arise due to energy loss to the environment, in which a qubit state | I) decays to 1 0) . This process is characterized by a typical time scale known as 7] . This type of error can be mitigated only by reducing the total circuit duration. Yet, as hardware quality improves, 1 times become longer and for mid-scale algorithms this process is, typically, not the bottleneck.

[0077] Another noise process is phase dephasing. In this process, the phase <f> scrambles and the quantum state loses its phase information. This process is characterized by a typical time scale known as T ₂ . In the presence of nearby drives, T ₂ may be much shorter than 7], dominating the overall algorithm performance.

Crosstalk

[0078] While the two processes above arise due to coupling between the system and the environment, idling errors may also arise due to unwanted coupling between nearby qubits. The most common idling error due to unwanted couplings known as the ZZ - error. In this process, a qubit acquires an unwanted phase which depends both on its state and a nearby qubit’s state. This unwanted coupling exists between pairs of coupled qubits and it has a constant static part, which only depends on systems’ parameters, and a dynamical part which depends on the drives we apply during the circuit.

Gate errors

[0079] Universal quantum computing can be achieved with arbitrary single-qubit gate and a two-qubit entangling gate. Both single-qubit and two-qubit gates are typically realized by irradiating the qubits with shaped wave-packets (pulses). On top of 7] and T ₂ errors as mention above, gates are prone to other types of errors as well. Gate implementation is characterized by its pulse parameters. The ideal gate implementation has specific ideal pulse parameter and any deviation of these parameters, known as over rotations, detunings, or other types lead to lower performance. Such deviations arise due to an unsuccessful calibration (optimization) process, extrinsic time-varying noise, or drift in system parameters. Another type of errors are control errors, pulses’ parameters can deviate due to the non-linear transfer function of the control chain and amplitude/phase noise in the pulse generators. These deviations lead to coherent gate errors similar to over rotations. Qubit decoherence further degrades the gate fidelity. While dephasing errors can often be mitigated by optimal pulse-shaping, the errors due to qubit relaxation can only be reduced with faster gates. However, fast gates are prone to another type of error known as leakage, where the system is excited to states outside the computational space which reduces the circuit fidelity.

Measurement and readout errors

[0080] Measuring qubits projects them to the eigenvalues of the observable. Typically it results in projecting the qubit to either the ground or excited state and ideally the repeated measurements of the same observable should give identical results. Measurement errors occur due to noise in the readout chain, qubit back-action, qubit relaxation and correlations between the multi -qubit measurements. Errors in measurement lead to large overheads for quantum error correction.

Overview of device aware algorithmic Dynamic Decoupling

[0081] Dynamical decoupling (DD) is an open-loop quantum control technique aimed to suppress errors on idling qubits. In its simplest form, DD is implemented by periodic sequences of control pulses (gates), whose net effect is to approximately cancel the unwanted couplings. Most DD protocols are designed to fight this T ₂ process, but different schemes exist for designing DD protocols for specific errorreducing tasks. For instance, a ZZ error can be mitigated by a DD protocol. Yet, protocols that mitigate ZZ errors can change dramatically from one algorithm to another and from one device to another, depending on the device topology, connectivity and ability to parallelize the different layers of the algorithm. There is a substantial body of literature on different approaches to designing DD sequences for different physical settings.

[0082] This disclosure provides methods for designing a protocol that can be both efficiently automated, aware of hardware and circuit context, and be applicable for generic algorithms and a wide range of quantum hardware. The ability to construct a well designed protocol for a given algorithm can render it useful.

Automated DD scheme

Basic DD motif

[0083] The disclosed automated scheme gets as an input a quantum circuit and device topology (Fig. 2), and returns a new circuit in which an optimal DD protocol is embedded in the original circuit.

[0084] The guiding principle of DD is the replacement of idling periods with an identity operation composed of one or more qubit manipulations which give no net change to the qubit state. Such examples appear in Fig. l(a, b). In these examples, the idling period is replaced by two applications of X gates (bit flip). Two consecutive bit flips are equivalent to no operation at all. Yet, each application of an X gate reverse the direction of the 7 ₂ related (stochastic) phase diffusion. Therefore, by matching the idling time between the two bit flips to the remaining idling time, the effect of 7 ₂ errors is suppressed (statistically cancels out). The statistical cancellation improves as the intermediate idling time, t , becomes smaller. Thus, if the total idling time is long, it may be beneficial to replace it with several repetitions of the basic motif. Since the application of X gates is not ideal, there is an optimal number of such repetitions. This number depends of the quality of the qubits ( f time and X gate error) and the strength of the ZZ coupling.

[0085] For a pair of coupled qubits, a ZZ idling error exists on top of the 7 ₂ error. Individual bit flip reverses the direction of the ZZ coupling. Hence, a simultaneous application of bit flips, as depicted in Fig. 1(c), leaves the ZZ coupling unchanged. In order to include ZZ mitigation, the two DD schemes must have a relative shift. Since the application of X gates is not instantaneous, an asymmetry parameter, 8 , can be optimized in order to achieve optimal ZZ cancellation. This motif, as appears in Fig. 1(d), is the basic building block of our method. More complicated motifs can be derived for cases where more than two qubits are all mutually coupled, and alternate couplings (such as XX) can be cancelled using sequences of different operations.

[0086] Including the basic motif for a set of fully idle qubits is a relatively easy task which only requires finding the optimal 8 parameter and the optimal number of motif repetitions. However, finding the optimal embedding of this motif in an arbitrary algorithm (Fig. 2) has no clear solution.

Automated embedding DD motifs in an arbitrary circuit

[0087] In this part the disclosure provides details on the automated scheme for embedding the DD motif in a generic circuit. The method is designed to cancel as much as possible the T ₂ and ZZ errors (typically, full cancellation is not possible) while keeping the number of X gates as low as possible. Extremely dense DD schemes (comprising many operations in a short time period) may be more harmful than useful, due to the individual errors of each X gates and due to heating effects.

[0088] Fig. 3 illustrates an example with the input circuit on top and the compiled circuit with embedded DD at the bottom.

[0089] The automated protocol is as follows:

[0090] 1. Given a device topology, the protocol divides the qubits to N groups by solving a graph coloring problem. For most hardware providers N = 2 , meaning, all qubits belong to one out of two possible groups. Qubits in one group will experience a 8 -shifted DD while qubits on the other group will experience a non-shifted 2t - 2t DD structure. See Fig. 1(d) for the distinction between the two groups. [0091] 2. Given a compiled circuit, the protocol slices the circuit to nonoverlapping ’Global Blocks’ which cover the full circuit. A block is a maximal time period where the set of idle qubits remains unchanged. Each block is characterized by initial and final times, [t,,Q] , and the set of idle qubits.

[0092] 3. Given the blocks structure, the total number of DD X gates can be calculated. Using this number together with X gates errors taken from the backend, the protocol may calculate an X -index. If this index is lower than a given threshold, the protocol keeps the block structure unchanged and skips step 4. Otherwise, the protocol moves to step 4.

[0093] 4. The protocol divides the circuit to non-overlapping groups of maximum size four of connected qubits. The protocol then applies the block slicing described in 2 for each group separately to find a new block structure ("Local Blocks"). This method sacrifices ZZ correction on some links in order to dramatically reduce the total number of X gates. The grouping of the qubits is not necessarily unique and is optimized to reduce the number of X gates in the circuit and ZZ correction mismatches. Given a device topology and set of active qubits, the optimal grouping construction is fully automated.

[0094] 5. Given the block structure (global or local) the protocol performs a set of block-merging rules to reduce the number of X gates. Our merging rules treat differently short blocks (under twice X gate duration), blocks of qubits with connectivity 1 and consecutive blocks with some similarity rules.

[0095] 6. Given the final blocks structure, the protocol applies the optimal number of DD motifs (appropriate to the block duration) for all idle qubits in a block according to their group as determined in 1. Qubits are considered idle or driven only after their first participation in the circuit.

[0096] See Fig. 3 for an example of input and output circuits. The scheme is based on the fact that within each global block, the DD motif optimally reduces both and ZZ effects. Yet, in reality, since the gates in the circuits are not synchronized and have different durations, some blocks may be too short for implementing any DD or two short for implementing the full motif. Also, since X gates are not ideal, perfect embedding of the DD motif is not enough and DD schemes with an extreme load of X gates are likely to underperform. Steps 3 and 4, are aimed to find a compromise that optimizes the performance of a specific algorithm on a specific device.

[0097] The procedure above is hardware agnostic and completely automated. Given a compiled circuit, device topology and backend data, it returns the a circuit with the optimal DD embedded in it. This methods does not require pulse-level access. As long as the API of the quantum hardware accepts a timed schedule of gates, this method is applicable. The ideal 8 -parameter and optimal number of motif application can be found in preliminary experiments which are automated as well.

Overview of scalable measurement error mitigation

[0098] An arbitrary quantum state is measured by projecting it on an observable. This task can be reduced to finding its probability distribution over all exponentially large set of basis states. The quantum circuit is executed multiple times to generate statistics required for constructing the probability distribution. The overall measurement error increases exponentially with the number of qubits due to compounding of readout errors from each individual qubit.

[0099] We can represent the error in readout assignment for a single qubit with a confusion matrix ( Cj _g )- where Cf = P[i | j] is the probability of assigning | i > to a measured state | j > . For a single qubit, one can obtain the ideal distribution with inverse of the confusion matrix i.e. P _ldeal = C ¹ P _meas and normalizing the quasi-probability distribution obtained.

However, this method is prone to several scalability issues-

• The size of the confusion matrix for the complete system (2 ’ x 2 ⁹ ) scales exponentially in the number of qubits ( N _q ). For N _q = 42 , storing C in a sparse format requires 580PiB which is 120-times more than that available on Fugaku the currently fastest supercomputer.

• Estimating the confusion matrix requires 2 ⁹ calibration experiments.

• Since the measured distribution itself has 2 ⁹ different possible outcomes, sampling only M times with M C 2 ⁹ produces a poor estimation of the confusion matrix.

• Inverting the confusion matrix for more than a handful of qubits is often ill-defined and is a time consuming process.

Automated measurement correction

Tensored mitigation

[0100] The disclosed method addresses the above mentioned problems by dividing a quantum device into smaller groups of qubits which can then be efficiently corrected via tensor algebra. The groups are automatically chosen in a way that minimizes intergroup correlations among the measurements based on the topology of the given quantum computer. One such example of grouping is shown in Fig. 4.

[0101] The disclosed method ensures that the all the groups combined span the whole quantum computer (or at least all the measured qubits in a quantum circuit). Let N _g be the number of groups and {G _j } for i e {k e N : k < N _g } denote the set of groups such that JG, = [ V ] . The confusion matrices corresponding to each group in {G are {C i=i and the size of each C _j matrix is given by 2 ^|G ‘ x 2 ^|G ‘ . [0102] The measured probability vector for N _q qubits has 2 ⁹ elements corresponding to each bit string i.e. P _t for i = 0,1,...,2 ⁹ - 1 where P _t denotes the probability of measuring the N _q -bit binary representation of i . The automated protocol is follows -

1. Reshape the measured probability vector of dimension (2 ⁹ x 1 ) into a tensor of dimensions (2x 2x...x2 ) such that each dimension i of the tensor corresponds to each qubit index i in the bit string.

2. Permute the qubit ordering in the tensor to correspond to the appropriate qubit orderings in G _j

3. If all qubits are not measured, then add additional dimensions to the tensor for all the unmeasured qubits that are part of the same group G _i as a measured qubit.

4. Reshape the permuted tensor into a tensor of dimensions ( 2 ⁰ x 2 ¹ X ...X 2 ^{1 g |} ). Lets denote this reshaped tensor as P .

5. Contract each index of i the tensor P with inverse of the appropriate confusion matrix C _t . Let a'. _k be the elements of C, ^-1 and til

6. Reshape the tensor P ^m,t to (2x 2x... x 2 ) and remove any additionally added dimensions in step 3.

7. The output of step 6 can contain negative elements. Convert this quasi-probability distribution into the closest probability distribution.

[0103] The number of calibration experiments for this method is given by 2 ' . In the example provided in Fig. 4, only 16 calibration experiments are needed to completely characterize a 16 qubit device as compared to 65536 calibration experiments needed for the complete confusion matrix approach. Moreover, since the disclosed method only estimates distributions over 16 states, the number of shots needed in order to achieve high accuracy is reduced dramatically. The requirement of inverting only small matrices provides additional speed and accuracy to the protocol execution.

[0104] The effectiveness of the disclosed mitigation can be seen in Fig. 5. The disclosed formalism works directly with sparse distributions. This results in a scalable, fast and a competitively accurate protocol. Lastly, the method incorporates the small corrections from long-range/ inter-group correlations by processing the output probability with a custom neural network as described below.

Neural network (NN) for multi-qubit correlations

[0105] The disclosed method uses the output from tensored mitigation described above as an input to a neural network (NN). The goal of the NN is to restore correlations neglected (at the boundaries of the groups) earlier, account for non-linear effects and contextual errors that are not captures in the confusion matrix formalism. Since the method is looking for small modifications to the identity transformation, the method uses a ResNet-like architecture for the NN. The number of tuneable parameters in the NN scales sub-linearly with the number of qubits (/V ). This approach minimizes the amount of training data required. An example of the neural network for 7 qubits is shown in Fig. 6

[0106] Disclosed herein is an automated approach to incorporate both the disclosed tensored mitigation methods and the disclosed neural network approach seamlessly. Fig. 7 shows that the neural network provides additional improvements in addition to that provided by the subset tensored mitigation protocol. Moreover, the trained network continues to provide improvement at least up to 15 days without additional training data. The disclosed methods are also applicable for mitigating error in the expectation of an observable.

Quantum compilation

[0107] Quantum compilers are used for finding more efficient ways to execute programs on quantum devices. A quantum compiler uses a sequence of “compiler passes" to handle the mapping of the circuit to the device gate-set and topology, and the simplification of the circuit instructions. This includes passes that: remove unnecessary gates, reduce circuit depth, and move gates onto qubits with lower error rates. Simplifying the logic of the circuit is a first step in mitigating the impact of noise during program execution - fewer operations gives fewer opportunities for error or can remove certain error-prone operations or qubits from the circuit.

[0108] To compile the circuit optimally, however, a delicate balance between these compiler passes is found. For example, moving single-qubit gates onto qubits with low error-rates requires the insertion of SWAP operations into the circuit. These SWAP gates increase circuit depth due to being made up of two-qubit gates (e.g., CNOT, CZ), those of which are also typically more prone to ZZ errors. So, while some error coming from the single-qubit gates are mitigated, new sources of error with two-qubit gates are introduced. It is these diminishing returns between each compiler pass that can be weighed for any given algorithm and device.

Cross-talk aware compilation

[0109] As highlighted above, finding the correct sequence of compiler passes is nontrivial and depends on both the device and the algorithm. There exist several open- source quantum compilers that can be used as a foundation to automate this procedure. By writing custom plug-ins to TKET (https://github.com/CQCL/tket) and qiskit (https://qiskit.org/), it is possible to tailor the compiler flow based on errorcharacteristics of the device. The “vanilla" procedure works as follows:

1. Run an initial “gate pass" to map the circuit to the device gates. 2. Use a specified “topology pass" to map the circuit to the device topology. This may involve the insertion of SWAP -gates into the circuit.

3. Use a specified “routing pass" to place the circuit in a desirable format. This will include moving circuit instructions onto qubits with lower gate errors. It may also involve the insertion of SWAP -gates.

4. Run a “SWAP-reduction pass" that iteratively minimizes the number of SWAP gates in the circuit.

5. Run another gate pass.

6. Run a specified sequence of isomorphic reductions (“simplification passes") on the circuit. This may include the removal of redundant gates, minimization of two-qubit operations, and replacement of certain gate sequences with simpler known definitions.

7. Use a “two-qubit-gate rerouting pass" to avoid running certain gates in parallel.

8. Run a final gate pass and topology pass before returning the circuit.

[0110] While this vanilla approach has moderate success in general, certain algorithms may require a more tailored approach to maximize error-mitigation. Important to this are the topology, routing, and simplification passes that are run on the circuit.

[0111] In particular, the behavior of the topology and routing passes largely depend on circuit characteristics such as the depth, density, and amount of two-qubit gates. One undesirable outcome of these passes are the insertion of an excess of SWAP gates. For N SWAP gates, 3N two-qubit gates are required to implement them. Too much rerouting from the original circuit placement can easily become detrimental to performance. Additionally, the behavior of the simplification passes is largely dependent on the format of the circuit. While two circuits may be isomorphic, differences in their gate operations may lead to different simplifications being made.

[0112] To alleviate this, disclosed herein is a hybrid compilation routine that alternates between different topology, routing, and simplification passes. More specifically, the disclosed method compiles the initial circuit using three different procedures:

1. Run the vanilla approach using topology pass A, routing pass A, and simplification pass sequence A (“routine A").

2. Run the vanilla approach using topology pass B, routing pass B, and simplification pass sequence B (“routine B").

3. Run the vanilla approach “M" times sequentially, passing the output of routine A into routine B and back until convergence (“hybrid routine").

4. If necessary, avoid specific gates in parallel.

[0113] With the hybrid approach, the disclosed method is alternating between two different sets of passes that, on their own, may only be moderately effective. By running them back and forth, however, the disclosed method is effectively exposing them to different initial conditions (topology, format, and gates) every time. This enables the disclosed method to extract as much benefit as possible from each pass. The last step is performed in cases of strong cross talk where the application of two gates simultaneously has a much lower quality than the conservative individual implementation of the two gates.

[0114] Once the disclosed method has run all three of these routines, the method selects the “best" using a heuristic based on the number of two-qubit operations in each circuit. This approach enables the selection of the optimally compiled circuit each time, regardless of the algorithm and device. A comparison of the three different routines is provided in Fig. 8 for QFT. The chosen circuit is ultimately embedded with the DD motif outlined above using a custom set of “decoupling passes".

Automated full device gate optimization and calibration

[0115] Quantum gates are the building blocks of any quantum circuit. Continuously maintaining a high quality (low error) basis gate set is a challenge all hardware providers are facing. Reducing gate errors can be achieved by manipulating a set of accessible experimental control probes. The exact details depend on the specifics of the hardware.

[0116] The disclosed method is able to provide low level implementations of quantum gates based only on measured system responses without requiring any prior knowledge of the particular device model or its underlying error processes.

[0117] This black box optimization protocol is based on a set of repeated experiments where the disclosed method extracts the gate error from an error-amplification protocol. One such protocol fits the estimated mean infidelity vs. the number of gate repetitions N . For each value of N the method applies N _batch different implementations of the gate under test N times on two or more different initial states. For example, the method evaluates the quality of a specific CX gate implementation by applying it on the initial states | +0) and | +1) .

[0118] After each run, a full state tomography is performed and an estimation of infidelity with respect to the ideal target state is calculated. An effective measure of error-per-gate is extracted by applying a linear fit to the average infidelity as a function of N , which provides a measure of the gate error in the low error limit.

[0119] The above procedure constitutes a cost function which assigns a quality measure to specific gate implementations. It is not the only approach to determining the error, and may incorporate measurement routines such as randomized benchmarking, gateset tomography, or the like to construct the cost function. The automated optimization procedures are designed to interact with the system in order to produce beter and beter gate implementations. More details can be found in Y. Baum, M. Amico, S. Howell, M. Hush, M. Liuzzi, P. Mundada, T. Merkh, A. R. Carvalho, and M. J. Biercuk, Experimental deep reinforcement learning for error robust gate-set design on a superconducting quantum computer, PRX Quantum 2, 040324 (2021). In particular, the method uses a form of optimization such as deep reinforcement learning to design a universal set of error-robust quantum logic gates in runtime , without requiring knowledge of a specific Hamiltonian model of the system, its controls, or its underlying error processes. More specifically, the method applies closed-loop control techniques such as autonomous deep-reinforcement-leaming to discover the best control signals drive state evolution through iterative interaction with a quantum computer; this delivers new waveforms defining a universal gate set that outperforms human-designed solutions. Because the control design process involves direct hardware measurements, all error sources — including leakage, dephasing, crosstalk, rf signal miscalibrations and distortions — are captured in the optimized control, even if they are known to a human operator.

[0120] The procedure above applies to a pair of qubits. In general, different pairs that do not share a qubit can be optimized in parallel. If strong cross talk effects exist, it may be beneficial to avoid a parallel optimization of neighboring pairs. The method automatically splits the device to a set of qubit pairs that can be optimized in parallel. Such spliting is depicted in Fig. 9 where due to strong cross talk effects the sixteen pairs are divided to four groups. This is an example grouping based on the example device’s connectivity. The gates between the pairs in each group are optimized in parallel.

[0121] Additional characterization routines may be run to learn about device error sources and noise processes in order to inform - either directly or indirectly, the gate optimization routine. This may include noise characterization or Hamiltonian parameter estimation processes useful in informing the definition of the cost function for optimization.

Summary of overall advantages [0122] The disclosed methods, implemented as a software package, are agnostic to the hardware and to the type of algorithm. Given an arbitrary algorithm and hardware properties, such as device topology, connectivity and backend data on qubits quality, the disclosed method enhances the performance of the algorithm by employing the methods disclosed herein. Other preliminary experiments can be added automatically, such as cross talk analysis or noise spectroscopy, in order to achieve further performance enhancement. The methods include optimized system aware compilation, optimal DD embedding, full device gate calibration/optimization and scalable measurement error mitigation. Fig. 10 compares the success probability of a Bemstein- Vazirani algorithm on a 16 qubits device. In the comparison, we compare our automated software tools to best compilation, DD scheme and measurement error mitigation available by the hardware provider.

Method for generating an error-corrected quantum circuit

[0123] Fig. 11 illustrates a method 1100 for generating an error-corrected quantum circuit. Method 1100 comprises compiling 1101 a quantum algorithm onto a quantum hardware using multiple qubits to generate a quantum circuit. As discussed above, this involves mapping the quantum algorithm onto the native gate set of the quantum hardware and replacing the native gates with error corrected gates using previous characterisation measurements.

[0124] The method 1100 then comprises determining 1102 a quantum relationship (e.g. coupling) between the multiple qubits, and a quantum relationship (e.g. coupling) between the multiple qubits and an external environment as a result of implementing the quantum circuit on the quantum hardware. This may involve determining pairs of gates that show cross-talk between them, for example. This may also involve measurements to characterise the error that is expected to occur as a result of the interaction with the environment. This quantum relationship can lead to an error that is specific for a given quantum hardware and is specific to the quantum circuit as generated by the compilation step because the compilation defines which gates are close to each other and the actions being applied to neighboring qubits, leading to potential crosstalk. Further details have been described above.

[0125] Method 110 then comprises using 1103 the quantum relationship between the multiple qubits and between the multiple qubits and an external environment to determine a deterministic error correction protocol for each of the multiple qubits and for interactions between the multiple qubits. For example, as explained with reference to Figs. 1 and 2, the deterministic error correction includes identity gates and a time shift to optimise the correction of ZZ errors as well as optimized error-robust quantum gates on qubit pairs and individual qubits.

Method for characterising errors

[0126] Fig. 12 illustrates a method 1200 for characterising errors in quantum hardware comprising multiple qubits. This may be seen as a more detailed version of step 1102 in Fig. 11. Method 1200 provides measured system responses without requiring any prior knowledge of the particular device model or its underlying processes. That is, method 1200 is part of a black box optimization method where the actual quantum hardware is treated as a black box with minimal knowledge about how the quantum hardware is built.

[0127] Method 1200 comprises determining 1201 groups of qubits to minimize intergroup correlations based on a topology of the quantum hardware and then performing 1202 multiple measurements to approximate a confusion matrix for individual qubit readouts. Method 1200 comprises repeating the multiple measurements for the qubit groups to determine the error characterisation of the hardware. In some examples, e procedure above applies to a pair of qubits. In general, different pairs that do not share a qubit can be optimized in parallel as shown in Fig. 9.

Method for compiling

[0128] Fig. 13 illustrates a method 1300 for compiling a quantum algorithm onto a quantum hardware having a native gate set. Method 1300 comprises repeatedly performing the steps of performing 1301 a first compilation process to map the quantum algorithm onto the quantum hardware and the native gate set and using 1302 the output of the first compilation process as an input for performing a second compilation process, different from the first compilation process, to maximize the use of low -error qubits as identified by an error characterisation process as explained above with reference to Figs. 8a and 8b.

Method for quantum error correction

[0129] Fig. 14 illustrates a method 1400 for quantum error correction of a quantum hardware as explained above with reference to DD motifs. Method 1400 comprises dividing 1401 qubits of the quantum hardware into groups based on a topology of the quantum hardware. Method 1400 then comprises dividing 1402 the qubits into blocks based on a quantum circuit compiled onto the quantum hardware. Method 1400 further comprises applying 1403 driven single-qubit operations to correct quantum errors arising during identity operations dependent on the quantum circuit compiled onto the quantum hardware. Finally, method 1400 comprises determining 1404 a time shift of the driven single-qubit operations to correct cross coupling for each of the groups during identity operations and the blocks and suppress decoherence as explained with reference to Figs. 1 and 2.

[0130] Additional error correction may be achieved using error-robust optimized gates using methods previously described. More specifically, there is provided a method for gate-set optimisation for a quantum hardware. The method comprises performing measurements on the quantum hardware to determine a quality measure to gate implementations on the quantum hardware. The method then comprises applying an optimisation procedure to iteratively adjust gate characteristics and repeat the measurements to progress towards a reduced error in the quantum gates. The gate characteristics may involve waveforms to control qubits in the quantum hardware. The method may further comprise performing the optimisation procedure to define a universal gate set. Further, the measurements are representative of multiple error sources, such as leakage, dephasing, crosstalk, rf signal miscalibrations and distortions. Even further, the measurements and optimisation procedure can be applied to the quantum hardware without knowledge of the details of the quantum hardware, such as the actual Hamiltonians of the physical apparatus.

Method for error-correcting compilation

[0131] Fig. 15 illustrates a method 1500 for error-correcting compilation to correct error sources identified in an error characterisation process. The method comprises receiving 1501 a compiled circuit compatible with an error characterisation and hardware device topology and gate set and replacing 1502 quantum logic gates in the compiled circuit having uncorrected errors over an acceptable threshold with error- corrected alternatives, derived using the error characterisation process. Finally, method 1500 comprises outputting 1503 a definition of the circuit with all replacement gate definitions in a format for hardware execution, including identity and non-identity operations.

Method for correcting errors in quantum measurements

[0132] Fig. 16 illustrates a method 1600 for correcting errors in quantum measurements of a quantum circuit on a quantum hardware. Method 1600 comprises receiving measurement results 1601 and using 1602 an approximated confusion matrix from an error characterisation to contract a tensor based on the groups of qubits. Method 1600 then comprises converting 1603 the tensor to a probability distribution and correcting 1604 the errors in the quantum measurements as indicated by the probability distribution. Finally, method 1600 comprises outputting 1605 a measurement-error-corrected result.

Internet server

[0133] Fig. 17 illustrates an internet server 1700, which is a computer system that is connected to the internet to receive and send data over the internet to various other computer systems. In particular, internet server 1700 is connected, via the internet, to a user client computer and an interface computer of a quantum hardware. Internet server 1700 is a classical, digital electronic computer system and comprises a processor 1701, program memory 1702, data memory 1703 and a communication port 1704.

[0134] Program memory 1702 is a non-volatile computer-readable medium and has program code stored thereon that, when executed by processor 1701, causes the processor to perform the methods disclosed herein, including methods disclosed in Figs. 11-16.

[0135] Internet server 1700 is configured, by way of program code installed on program memory 1702, to offer, or expose, a web-interface. The web interface comprises input elements to input a quantum algorithm and a characterisation of a quantum hardware. The web-interface may be a graphical user interface with graphical input elements for data entry or file upload, or may be an application programming interface (API) with syntactical input elements, such as XML or JSON fields.

[0136] Internet server 1700 is therefore configured to receive the quantum algorithm and an incomplete description of the quantum hardware through the web-interface. The quantum algorithm and the incomplete description may be provided by the same user, by different users or the incomplete description may be provided by the vendor or provider of the quantum hardware. The description is considered “incomplete” because it includes an abstract description of the quantum hardware (such as native gate set) but does not include an error characterisation of the individual gates or circuit blocks.

[0137] Therefore, internet server 1700 is further configured to perform error characterisation or retrieve an error characterisation previously performed, such as from data memory 1703, for the target quantum hardware. Error characterisation may involve communication with the quantum hardware to initiate qubits with quantum values, perform quantum operations and receive measurements to characterise the error as described above.

[0138] Internet server 1700 is further configured to generate a decorated quantum circuit description that realises the quantum algorithm on the quantum hardware. “Decorated” in this context means that the quantum circuit comprises quantum gates as well as control protocols for error correction. Further, the decorated quantum circuit description comprises quantum logic blocks that are error corrected based on the error characterisation as described above as gate calibration.

[0139] Internet server 1700 is further configured to output the quantum circuit description. This may be to the user so that the user can send the description to the quantum hardware for implementation. In other examples, the internet server 1700 sends the description directly to the quantum hardware, such as an API of the hardware provider for immediate implementation.

[0140] Once the quantum algorithm is performed on the quantum hardware, internet server 1700 receives and analyses the raw output data from the quantum hardware using the complete characterisation. This involves the measurement error correction described above.

[0141] As a result of the methods disclosed herein, deterministic error correction protocols are applied to the quantum hardware and error corrected gates are used together with measurement error correction. Together, these measures lead to a significant reduction in error rates, which was previously not achievable.

[0142] It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the above-described embodiments, without departing from the broad general scope of the present disclosure. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.