Present invention generally concerns analog-to-digital converters (ADCs), specifically successive approximation ADC's which are constituted by digital-to-analog converters (DACs) capacitively driven by control signals generated by a logic circuit.

Background of the Disclosed Invention

High-speed analog-to-digital conversion is required by trends in many commercial and research electronic applications including, but not limited to, high speed serial links in data centres, cellular communication systems and subsystems, and electronic testing/acquisition instruments. Asynchronous successive approximation analog-to-digital converters (ADCs) tend to incorporate differential capacitive digital-to-analog converters (DACs) which come with a logic circuit configured to produce control signals thereof. VCM based DACs are preferred for their fixed input common mode, therefore alleviating the design constraints of comparators. Logic circuits in question pose the danger of becoming bottlenecks for the overall speed and performance of the entire circuit, which urges the design effort for faster incarnations thereof. To improve the critical path within the circuit proper, architecture options favouring the design of control pathways of logic units in a time-interleaved and parallelism for delay prevention are available. Static or dynamic nature of said architecture options are however, subject to no specificity per se.

Prior art document with number US 9614540 teaches an architecture where positive and negative voltage inputs are collected along with an externally triggered clock frequency and a comparator mechanism for controlling DAC. The logic unit disclosed in this document consists of two distinct parts namely detector and successive approximation register (SAR), utilizing pipelining method. Said successive approximation register (SAR) is designed using CMOS gates, which results in a dynamic logic property.

Another teaching known in the art is disclosed in the application with number US 2011057823, where an asynchronous successive approximation register comprises n slices from the most to the least significant bits, for each of which a separate block performs logic operations. These blocks within themselves include parasitic capacitors and CMOS transistors for performing said logic operations, which implies dynamic logic, therefore bringing in higher levels of power consumption and computational complexity.

Yet another teaching known in the art is disclosed in the document with number US8344925, in which system and method are provided for adaptively controlling timing in SAR ADC of a sampled analog signal within a conversion period. Disclosed system includes state machine that maintains a set of SAR states including a sampling state and a plurality of bit conversion states defined with a reference generator, a comparator, a clock generator adaptively defines signals for clocking the state machine and comparator for each SAR state. The architecture proposed in one paper published in IEEE Journal of Solid- State Circuits of December 2013, titled "A 3.1 mW 8b 1.2 GS/s Single- Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS" L. Kull et al. refers to an asynchronous clock logic unit that comprises a memory cell characterized by a dynamic buffer, and dynamic logic transistors configured to minimize latency/delay at the output of the comparator. Said design, in addition to presenting a layered architecture resulting from the premise of storing comparator output for using in logic operations, also lacks static logic characteristics caused by the use of CMOS transistors.

Objects of the Disclosed Invention

Primary object of the present invention is to provide a system for successive approximation register (SAR) logic.

Another object of the present invention is to provide a bitwise discrete logic scheme for successive approximation registers (SARs). A further object of the present invention is to provide an event-triggered logic scheme for successive approximation registers (SARs).

A further object of the present invention is to provide a self-determining logic scheme for successive approximation registers (SARs).

A further object of the present invention is to provide a logic scheme for successive approximation registers (SARs) that comprise static logic with latch utility to improve critical path and computational complexity. A further object of the present invention is to provide a logic scheme for successive approximation registers (SARs) that comprise static logic with latch utility to improve power consumption and circuit size. Summary of the Disclosed Invention

It is disclosed herein that, according to the main and dependent claims, time interleaved single channel analog-to-digital converters (ADCs). The present invention discloses an event-triggered self-determining successive approximation register logic circuit (1) for controlling differential capacitive digital-to-analog converters found in analog-to-digital converters. In other words, disclosed invention is a logic circuit (1) comprising at least one positive and negative DREF cells (7, 9) and one DCM cell (8) at every bit level coordinating and handshaking therebetween through signal delivery, to control common mode based differential capacitive digital-to-analog converters found in successive approximation register analog-to-digital converters.

Brief Description of Figures

Accompanying drawings are given solely for the purpose of exemplifying an event-triggered self-determining successive approximation register logic circuit, whose advantages over prior art were outlined above and will be explained in brief hereinafter.

The drawings are not meant to delimit the scope of protection as identified in the Claims, nor should they be referred to alone in an effort to interpret the scope identified in said Claims without recourse to the technical disclosure in the description of the present invention. Figure 1 demonstrates top view of an n-bit successive approximation register logic circuit in its entirety according to the disclosed invention. Figure 2 demonstrates the circuit schematic of a common mode (DCM) cell of the successive approximation register logic circuit according to the disclosed invention.

Figure 3 demonstrates the circuit schematic of a reference (DREF) cell of the successive approximation register logic circuit according to the disclosed invention.

Detailed Description of the Present Invention

1) Logic unit

2) Comparator positive signal

3) Comparator negative signal

4) Positive reference block

5) Common mode cell block

6) Negative reference block

7) Positive DREF cell

8) DCM cell

9) Negative DREF cell

10) NOR2 gate

11) Inverter

12) Latch

13) T gate

14) PMOS switch

15) NMOS switch 16) NOR3 gate

As seen in Figure 1, disclosed invention is defined as a logic circuit (1) operating in an event-triggered and self-determining fashion for asynchronous, successive approximation register based analog to digital converters; comprising cells discrete for every bitwise comparation and designed entirely according to static logic character. Said successive approximation register logic circuit (1), following the asynchronous triggering of the comparator clock by a pulse generator, adjusts the corresponding switches of the digital to analog converter according to the comparator output. This asynchronous flow repeats for n+1 times, where n stands for number of bits and one extra time for sampling. Communication, coordination and handshakes between each of the discrete logic cells are handled using "done", "set" and "valid_nxt" signals exchanged therebetween.

Figure 1 still discloses logic cells arranged in three rows; a positive reference block (4) comprising n number of positive DREF cells (7), a common mode block (5) comprising n number of DCM cells, and a negative reference block (6) comprising n number of negative DREF cells (9). Each of the positive DREF cells (7) situated in the positive reference block (4) accept comparator positive signal (2), whereas each of the negative DREF cells (9) situated in the negative reference block (6) accept the comparator negative signal (3) as respective inputs thereto. These inputs, namely comparator positive and negative (2, 3) signals are activated once a comparation instance is finalized, which results in positive DREF cells (7) or negative DREF cells (9) being able to conduct logic operations. Critical path is, apart from the difference at the final bit level which is to be elaborated further in following paragraphs; defined as the signal exchange over two DREF cells (7, 9) and DCM cell (8) at each bit level.

Comparator positive (2) and negative (3) signals generated by the comparator conducting binary search, enable positive DREF cells (7) or negative DREF cells (9) to be moved to a state to conduct logic operations, respectively. Either of these cells generate a "set" signal delivered to the DCM cell (8) therefore, activating said DCM cell (8). DCM cell (8) then generates a signal to control corresponding switches of the digital-to-analog converter. While, the "done" signal still generated by said DCM cell (8) to be delivered to DREF cells (7, 9) at the same bit level activates the latches (12) in said DCM cell (8) and DREF cells (7, 9) which lock the cell in their current state and prevents any further alterations on present input and/or output states of said DREF (7, 9) cells when next comparison decision is made in the comparator. In other words, outputs of the DCM cell (8) is pulled high so that control signals from both the DREF and DCM cells are locked.

Figure 2 illustrates the circuit schematic of DCM (common mode) cells (8) situated in the central, common mode block (5) of said successive approximation logic circuit (1) previously demonstrated on Figure 1. This circuit, basically formed by a two-input NOR gate (10) and a following latch (12) structure, comprises MOSFET switches and ve static logic gates. Two-input NOR gate (10) accepts the output of positive or negative DREF cells (7, 9) as input, delivered thereto via set signal. Since when the input originating from a positive DREF cell (7) is 1 the input originating from negative DREF cell (9) will be 0 and conversely when the input originating from a positive DREF cell (7) is 0 the input originating from negative DREF cell (9) will be 1; NOR logic operation executed by the two-input NOR gate (10) always outputs 0. Output generated by the two-input NOR gate (10) is split, one is inverted via an inverter (11) to a 1, then both are delivered to the northern and southern terminals of a T gate (13). The T gate (13) relays outputs generated by PMOS switches (14) which are, in turn, in connection with the secondary DREF cell (7, 9) outputs delivered to the cell via the same set signal. Latch (12) structure in the cell comprises PMOS (14) and NMOS (15) keys; behaving in a manner to relay high current latching info to positive and negative DREF cells (7, 9) at the same bit level via done signal, is configured to be able to supply same signal unto itself; latch (12) state is unalterable unless in the case of one reset signal arriving and triggering the NMOS switch (15), disrupting the latch. Next to this, the valid_nxt signal which is one of the outputs generated by the DCM cell (8) and situated between two inverters (11), activates next bit level positive and negative DCM cells (7, 9) to act according to the comparison signal produced by the comparator for the next level bit comparison.

Figure 3 illustrates the circuit schematics of positive and negative DREF cells (7, 9) situated in the positive and negative reference blocks (4, 6) respectively of said successive approximation logic circuit (1) previously demonstrated on Figure 1. These cells, similar to the DCM cell (8) laid bare previously, is characterized by a NOR gate including MOSFET switches and a static logic latch construct, albeit the NOR in this circuit is a three-input NOR gate (16). Three-input NOR gate (16) accepts as one input directly the comparison result outputted by the comparator. Remaining two inputs are; the valid_nxt signal generated by the previous DCM cell (8) while the previous bit level comparison was handled, and the done signal generated by the current bit-level DCM cell (8). Output of the three-input NOR gate (16), unlike the case with the DCM cell (8) mentioned previously, is split to three; two of which are carried to the north and south terminals of a T gate (13) after one is inverted via an inverter (11). Third split is connected to the NMOS switch (15). The DREF Cell (7, 9) whose latch (12) structure is designed with PMOS and NMOS switches (14, 15) generates, in addition to the comparison signal to control the appropriate switches of the digital-to-analog converter based on the comparator output, a set signal to the relevant DCM cell (8) on the common mode block (5). With the reciprocating high current done signal delivered from said DCM cell (8) operating on the same bit level triggering the latch (12), cell values become unalterable unless/until a reset signal arrives and triggers the dissolution of said latch (12).

The critical path of the logic unit (1) is defined as, every bit level comparison is completed by the comparator, followed by the logic events triggered in the positive and negative DREF cells (7, 9) by signals delivered thereto, done and vaiid_nxt signals being generated after another logic event is triggered in the DCM cell (8) by set signal delivered thereto by DREF cells (7, 9), still followed by relaying comparator decision signals to be delivered to digital-to-analog converter. Said critical path is repeated n + 1 times, where n is the bitwise resolution of the analog-to- digital converter in the course of which critical path executes from the most significant bit (MSB) to the least significant bit (LSB), and 1 is for sampling. To rephrase, the disclosed invention in principle is an asynchronous, event-triggered and self-determining logic circuit (1) that addresses the speed bottleneck problem posed by logic units controlling digital-to-analog converters, found in in time interleaved single channel analog-to-digital converters. In multiple analog-to-digital converter applications which utilize V _CM based time interleaving switches, disclosed logic circuit (1) as a product of its highly optimized architecture offers superior performance in means of design constraints such as surface area, critical path length and power consumption. Dividing the voltage range into 2 ⁿ equal segments according to the binary search algorithm and at every bit stage, performs registration with respect to the comparison signal (either a 0 or a 1) relayed from the comparator. In said logic circuit (1) positive and negative reference blocks (4, 6) are respective DREF cells, positive and negative (7, 9), whereas in the common mode block (5) lie DCM cells (8), precisely in the quantity of the bitwise resolution of said analog-to-digital converter; communication between which is handled over signal exchange therebetween. Such is the process performed thereby, the comparator- ridden digital-to-analog converter control over the course of dependent logic events. Static logic character of said positive and negative DREF cells (7, 9) and DCM cells (8) architecture of said logic unit is based upon entirely, reduces computational complexity greatly as well as enabling superiority in means of power consumption and speed.

In one embodiment of the disclosed invention, an event-triggered self- determining logic circuit (1) for controlling differential, capacitive, common mode voltage based digital-to-analog converters delivering the values to be compared to a binary search comparator found in successive approximation register utilizing analog-to-digital converters is proposed. In another embodiment of the disclosed invention, said logic circuit (1) comprises at least one positive DREF cell (7) and at least one negative DREF cell (9), static logic-based, comparator positive and negative result for each bit level operation is delivered respectively thereto. In yet another embodiment of the disclosed invention, said logic circuit (1) further comprises at least one still static logic-based DCM cell (8) handling communication between said positive DREF cell (7) and negative DREF cell (9) and triggering next bitwise comparison.

In a further embodiment of disclosed invention, said logic circuit (1) further comprises a positive reference block (4), a negative reference block (6) and a common mode block (5) between said two blocks in accordance with the outputs of the comparator.

In a further embodiment of disclosed invention, said positive and negative DREF cells (7, 9) and said DCM cells (8) comprise latch (12) structure rendering unalterable thereof. In a further embodiment of disclosed invention, the critical path defined by the signal exchange between two DREF cells (7, 9) and a DCM cell (8) at every bit level comprises two NOR gates (11, 16) and a latch (12).

In a further embodiment of disclosed invention, said logic circuit (1) further comprises a comparator positive signal (2) exciting said positive reference block (4) and a comparator negative signal (3) exciting said negative reference block (6).

In a further embodiment of disclosed invention, said logic circuit (1) further comprises a reset signal input for the dissolution of said latch (12) structure found in said DREF cells (7, 9) and DCM cells (8). In a further embodiment of disclosed invention, said logic circuit further comprises a set signal outputted from said DREF cells (7, 9) to the DCM cell (8) at the same bit level for control thereof. In a further embodiment of disclosed invention, said logic circuit (1) further comprises a done signal outputted from the DCM cell (8) to the DREF cells (7, 9) at the same bit level for control thereof.

In a further embodiment of disclosed invention, said logic circuit (1) further comprises a valid_nxt signal outputted from said DCM cell (8) to the DREF cells (7, 9) at the next bit level for control thereof.

In a further embodiment of disclosed invention, said logic circuit (1) further comprises at least three control signals outputted therefrom, connected to to the digital-to-analog converter for control thereof.