Related Applications

[0001] This application is a non-provisional of U.S. Provisional Patent Application No. 62/312,340, filed March 23, 2016, which is incorporated by reference herein in its entirety.

Technical Field

[0002] The present disclosure relates to an extended synchronization signal for a symbol index. In particular, the present disclosure relates to an extended

synchronization signal for a symbol index in 5G.

Brief Description of the Drawings

[0003] FIG. 1 is a diagram of a subframe according to one embodiment.

[0004] FIG. 2 is a block diagram illustrating electronic device circuitry that may be eNodeB circuitry, user equipment (UE) circuitry, network node circuitry, or some other type of circuitry according to one embodiment.

[0005] FIG. 3 is a block diagram illustrating a method for the generation of an extended synchronization signal according to one embodiment.

[0006] FIG. 4 is a block diagram illustrating a method for deriving a symbol index according to one embodiment.

[0007] FIG. 5 is a block diagram illustrating components of a device according to one embodiment.

[0008] FIG. 6 is a block diagram illustrating components according to some embodiments. Detailed Description of Preferred Embodiments

[0009] Wireless mobile communication technology uses various standards and protocols to generate and/or transmit data between a base station and a wireless communication device. Wireless communication system standards and protocols can include, for example, 3rd Generation Partnership Project (3GPP) long term evolution (LTE); the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard, which is commonly known to industry groups as worldwide interoperability for microwave access (WiMAX); and the IEEE 802.1 1 standard, which is commonly known to industry groups as Wireless Local Area Network (WLAN) or Wi-Fi. In 3GPP radio access networks (RANs) in LTE systems, a base station may include Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (also commonly denoted as evolved Node B, enhanced Node B, eNodeB, or eNB) and/or Radio Network Controllers (RNCs) in the E-UTRAN, which communicate with a wireless communication device, known as user equipment (UE). In LTE networks, the E-UTRAN may include a plurality of eNodeBs and may communicate with the plurality of UEs. LTE networks include a radio access technology (RAT) and core radio network architecture that can provide high data rate, low latency, packet optimization, and improved system capacity and coverage.

[0010] Mobile communication has evolved significantly from early voice systems to today's highly sophisticated integrated communication platform. 4G LTE networks are deployed in more than 100 countries to provide service in various spectrum band allocations depending on spectrum regime. Recently, significant momentum has started to build around the idea of a next generation, e.g., fifth generation (5G), wireless communications technology.

[0011] High frequency band communication has attracted significant attention from the industry, since it can provide wider bandwidth to support the future integrated communication system. In some examples, high frequency bands can include bands at the 6 GHz frequency and above. Beam forming is a critical technology for the implementation of a high frequency band system due to the fact that the beam forming gain can compensate for the severe path loss caused by atmospheric attenuation, improve the signal to noise ratio (SNR), and enlarge the coverage area. By aligning the transmission beam to the target UE, the radiated energy is focused for higher energy efficiency, and the mutual UE interference is suppressed. In a number of embodiments, the synchronization signal (e.g., primary synchronization signal (PSS), secondary synchronization signal (SSS), and extended synchronization signal (ESS), beamforming reference signal (BRS), and 5G physical broadcast channel (xPBCH)) can be included in a downlink signal. A BRS can be frequency division multiplexing (FDM) interleaved for different beamformed antenna ports. In some examples, a physical broadcast channel xPBCH can be frequency division multiplexed (FDMed) with the PSS, the ESS, the SSS, and the distributed BRS within each orthogonal frequency-division multiplexing (OFDM) symbol.

[0012] Reference is now made to the figures, in which like reference numerals refer to like elements. For clarity, the first digit of a reference numeral indicates the figure number in which the corresponding element is first used. In the following description, numerous specific details are provided for a thorough understanding of the embodiments disclosed herein. However, those skilled in the art will recognize that the embodiments described herein can be practiced without one or more of the specific details, or with other methods, components, or materials. Further, in some cases, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0013] FIG. 1 is a diagram of a subframe 108 according to one embodiment. The subframe 108 includes an ESS 102, a PSS 104, and a SSS 106.

[0014] The PSS 104 can provide a timing synchronization signal. The PSS 104 can function as defined in the 4G LTE specification. In the ESS 102 at least 12 or 14 sequences are used to support subframe timing. The 12 or 14 sequences can be expressed within the subframe 108. For example, the 12 or 14 sequences can be expressed in symbols 1 10-1 to 1 10-12 and/or symbols 1 10-1 to 1 10-14.

[0015] The SSS 106 can be used to derive the physical cell identification (ID) (e.g., referred to generally as PCI). The SSS 106 sequence can be defined under the 4G LTE specification. A distributed beam reference signal (BRS) is a sequence that can be generated based on a physical cell ID. The distributed BRS can span an entire band excluding the middle 18 physical resource blocks (PRBs) occupied by the PSS 104, ESS 102, and SSS 106, which can be referred to as a synchronization region. [0016] The synchronization region can be defined by symbols 1 10-1 to 1 10-14 (referred to herein as symbols 1 10) in a subframe 108 and by PRBs 1 12-1 , 1 12-2, 1 12-3. The ESS 102, the PSS 104, and the SSS 106 can span a plurality of PRBs. The ESS 102 can span six PRBs 1 12-1 , the PSS can span six PRBs 1 12-2, and the SSS 106 can span six PRBs 1 12-3. In a number of examples, the PRBs 1 12-1 , the PRBs 1 12-2, and the PRBs 1 12-3 each span the consecutive PRBs.

[0017] Each of the ESS 102, the PSS 104, and the SSS 106 can span a plurality of symbols. For example, the ESS 102, the PSS 104, and the SSS 106 can span the symbols 1 10-1 to 1 10-14.

[0018] As described above, symbol boundary information can be provided by the PSS 104, the physical cell ID information can be provided by the PSS 104 and the SSS 106, the frame boundary information can be provided by the SSS 106, and symbol index information can be provided by the ESS 102. After detecting the PSS 104 and the SSS 106, a user equipment (UE) can determine the physical cell ID and a symbol, subframe and frame boundary. The ESS 102 can be generated based on a Zadoff-Chu (ZC) sequence with different cyclic shifts. The UE can derive the reference ZC sequence based on a PSS ID and subsequently perform cross- correlation to determine the cyclic shift of the ESS sequence, which can be used to derive the symbol index.

[0019] In previous examples, the root index of an ESS sequence is defined as a function of a PSS ID, which may not mitigate the inter-cell interference in the case when two cells have the same PSS IDs but different SSS IDs. The PSS ID can identify a PSS 104 and a SSS ID can identify a SSS 106. Given that the physical cell ID is available after the PSS 104 and the SSS 106 detection, it would be more desirable to define the ESS 102 sequence as a function of a full or partial physical cell ID to randomize the inter-cell interference. The UE can perform sanity checks on whether physical cell ID detection is successful from the PSS 104 and the SSS 106 detection in response to defining the ESS 102 as a function of the physical cell ID.

[0020] The ZC sequence can be generated based on a root index and a length. As such, the ESS 102 can be generated based on the root index of the ZC sequence and the length of the ZC sequence.

[0021] In a number of examples, the root index can be defined from a root index list. The root index list can be provided as rootlndexList = [1 , 2, 4, 5, 8, 10, 1 1 , 13, 16, 17, 19, 20, 22, 23, 25, 26, 29, 31 , 32, 34, 37, 38, 40, 41 , 43, 44, 46, 47, 50, 52, 53, 55, 58, 59, 61 , 62], among other possible definitions of a root index list. The root index for the ESS sequence can be generated as a function of physical cell ID such that:

u = rootIndexList[f(N^ ¹¹ )].

[0022] U is the root index. The physical cell ID is defined as Ν[β ¹¹ . A function derived using the physical cell ID is defined as f(N^ ^u ). The function derived using the physical cell ID can map the physical cell ID to an integer. The integer can be used as an index to the root index list from which the root index is selected. For example, an index equal to 0 can define a first item from the root index list, as described above, equal to 1. An index equal to 1 can define a second item from the root index list equal to 1 . The index equal to 2 can define a third item from the root index list equal to 4. The index equal to 31 can define a 32nd item from the root index list equal to 62.

[0023] In one embodiment, the root index is defined as:

cell

N\

u = rootlndexList M ID

L

[0024] The root index list and the physical cell ID are described as above. M and L are constant, which can be predefined in the specification (e.g., 4G LTE, 5G, and/or a different specification) and [-J is the floor operation. In one example, M = 1 and L = 14, such that:

cell

N

u = rootlndexList ID

14

[0025] In other examples, L = 12. Setting M = 1 and L = 14 can result in the creation of 36 root indexes that can be used to define the ESS sequence. For example, cells (e.g., eNodeBs) with a physical cell ID (e.g., Ν[β ¹¹ ) equal to 0, 1 , 13 can transmit the ESS 102 with a root index equal to 1 . Cells with a physical cell ID equal to 14, 15, 27 can transmit the ESS 102 with a root index equal to 2. Cells with a physical cell ID equal to 28, 29, 41 can transmit the ESS 102 with a root index equal to 4, and so forth.

[0026] In a different embodiment, to further reduce the number of root indexes used for the generation of the ESS 102, which can potentially reduce the memory size for storing reference ESS sequences, the root index can be defined as: rcell

u = rootlndexList

56

[0027] such that M = 4 and L = 56. In this embodiment, nine root indexes can be defined for the generation of the ESS sequence. For example, cells with a physical cell ID equal to 0, 1 , 55 can transmit the ESS 102 with a root index equal to 1 . Cells with a physical cell ID equal to 56, 57, 1 1 1 can transmit the ESS 102 with a root index equal to 8. Cells with a physical cell ID equal to 1 12, 1 13, 167 can transmit the ESS 102 with a root index equal to 16, and so forth.

[0028] In yet another embodiment, the root index for the ESS sequence is provided as:

[0029] Where K is a constant and mod(-) is the modulo operation. In one example, K = 36. Then:

[0030] In this example, 36 root indexes can be defined for the ESS sequence. For example, cells with a physical cell ID equal to 0, 36, 468 can transmit the ESS 102 with a root index equal to 1 . Cells with a physical cell ID equal to 1 , 37, 469 can transmit the ESS 102 with a root index equal to 2. Cells with a physical cell ID equal to 2, 38, 470 can transmit the ESS 102 with a root index equal to 4, and so forth.

[0031] The based sequence d _u (0), ..., d _u (62) used for the ESS 102 is the length- 63 Zadoff-Chu (ZC) with root index for the primary synchronization signal, where:

_ .nun(n+l)

d _u (ri) = e ¹ 63 , n = 0, l, ... , 62

where the Zadoff-Chu root sequence index u is defined as follows:

rootlndexList = [1 , 2, 4, 5, 8, 10, 1 1 , 13, 16, 17, 19, 20, 22, 23, 25, 26, 29, 31 , 32, 34,

37, 38, 40, 41 , 43, 44, 46, 47, 50, 52, 53, 55, 58, 59, 61 , 62]; u = rootlndexList

[0032] The sequence used for the ESS 102 in each OFDM symbol is defined as 2 ^■ Nsy _mb different cyclic shifts of d _u according to: d _u ^l (ri) = d _u ((n + A _shift ^■ l) mod 63) where 0 < n < 62 and A _9¾ift = — ¾— = 4.

s ^hlft [0033] The same antenna port as for the PSS 104 can be used for the ESS 102. The sequence d _u ^l can be mapped to resource elements according to

<½,; = d _u ^l (n), n = 0, ... , 62

where

k = n - 104 + ^{RB sc}

2

and 1 = 0, 1, ... , 12, 13.

[0034] FIG. 2 is a block diagram illustrating electronic device circuitry that may be eNodeB circuitry, user equipment (UE) circuitry, network node circuitry, or some other type of circuitry according to one embodiment. FIG. 2 illustrates an electronic device 200 that may be, or may be incorporated into or otherwise part of, an eNodeB, a UE, or some other type of electronic device in accordance with various embodiments. Specifically, the electronic device 200 may be logic and/or circuitry that may be at least partially implemented in one or more of hardware, software, and/or firmware. In embodiments, the electronic device logic may include radio transmit/transmitter logic (e.g., a first transmitter logic 277) and receive/receiver logic (e.g., a first receiver logic 283) coupled to a control logic 273 and/or a processor 271 . In embodiments, the transmit/transmitter and/or receive/receiver logic may be elements or modules of transceiver logic. The first transmitter logic 277 and the first receiver logic 283 may be housed in separate devices. For example, the first transmitter logic 277 can be incorporated into a first device while the first receiver logic 283 is incorporated into a second device, or the transmitter logic 277 and the receiver logic 283 can be incorporated into a device separate from a device including any combination of the control logic 273, a memory 279, and/or the processor 271 . The electronic device 200 may be coupled with or include one or more antenna elements 285 of one or more antennas. The electronic device 200 and/or the components of the electronic device 200 may be configured to perform operations similar to those described elsewhere in this disclosure.

[0035] In embodiments where the electronic device 200 implements, is

incorporated into, or is otherwise part of a UE and/or an eNodeB, or device portion thereof, the electronic device 300 can generate an ESS. The processor 271 may be coupled to the first receiver and first transmitter. The memory 279 may be coupled to the processor 271 having control logic instructions thereon that, when executed, generate and/or transmit the ESS. [0036] In embodiments where the electronic device 200 receives data, generates data, and/or transmits data to/from a UE to implement a downlink signal including the ESS, the processor 271 may be coupled to a receiver and a transmitter. The memory 279 may be coupled to the processor 271 having control logic 273 instructions thereon that, when executed, may be able to generate the ESS using a root index generated from a physical cell ID.

[0037] As used herein, the term "logic" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, the processor 271 (shared, dedicated, or group), and/or the memory 279 (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide

the described functionality. Specifically, the logic may be at least partially

implemented in, or an element of, hardware, software, and/or firmware. In some embodiments, the electronic device logic may be implemented in, or functions associated with the logic may be implemented by, one or more software or firmware modules.

[0038] FIG. 3 is a block diagram illustrating a method 320 for the generation of an extended synchronization signal according to one embodiment. The method 320 includes accessing 322 a physical cell ID of an eNodeB, generating 324 a root index based on the physical cell ID, and generating 326 an extended synchronization signal with the root index. The extended synchronization signal can span multiple symbols within a subframe. The extended synchronization signal can be generated based on the physical cell ID. The ESS can span 14 symbols and multiple PRBs within the subframe. For example, the ESS can span six physical resource blocks within the subframe.

[0039] In some embodiments, the ESS can span 72 subcarriers within the subframe. The ESS can be part of a downlink signal. The physical cell ID can identify an eNodeB. The eNodeB can be part of a 5G system.

[0040] In some embodiments, an apparatus for an eNodeB can comprise electronic memory and one or more baseband processors configured to generate for a user equipment (UE) a downlink signal including an extended synchronization signal, a primary synchronization signal, and a secondary synchronization signal in a time domain and a frequency domain, wherein the extended synchronization signal spans multiple symbols within a subframe, and wherein the extended synchronization signal is generated based on a physical cell identification (ID) of the eNodeB.

[0041] The ESS can be based on the entire physical cell ID. The ESS can also be based on a portion of the physical cell ID. A root index for the ESS can be selected from a root index list based on the physical cell ID. The root index list is given as 1 , 2, 4, 5, 8, 10, 1 1 , 13, 16, 17, 19, 20, 22, 23, 25, 26, 29, 31 , 32, 34, 37, 38, 40, 41 , 43, 44, 46, 47, 50, 52, 53, 55, 58, 59, 61 , 62. That is, the root index list is a list of root indexes. The root index can be given as u = rootIndexList[f N^ ¹¹ )], where Ν[β ¹¹ is the physical cell ID and f(N^ ^u ) is a function of the physical cell ID.

[0042] In some embodiments, a computer-readable storage medium can store thereon instructions that, when implemented by a computing device, cause the computing device to perform operations for an ESS. The operations comprise generating for a UE a downlink signal including an extended synchronization signal, a primary synchronization signal, and a secondary synchronization signal in a time domain and a frequency domain, wherein the extended synchronization signal spans multiple symbols and physical resource blocks within a subframe, and wherein the extended synchronization signal is generated based on a physical cell identification (ID) of the eNodeB.

[0043] In one embodiment, The root index for the ESS is given as u = rootlndexList M ^N ID

N

The root index list can be defined as 1 , 2, 4, 5, 8, 10, 1 1 , 13, 16, 17, 19, 20, 22, 23, 25, 26, 29, 31 , 32, 34, 37, 38, 40, 41 , 43, 44, 46, 47, 50, 52, 53, 55, 58, 59, 61 , 62. M and L are constants which can be predefined in the specification and [ ^■ ] is the floor operation. For example, M can be equal to 1 and N can be equal to 14. In this example, 36 root indexes can be defined for the ESS. In some examples, nine root indexes can be defined for the extended synchronization signal.

[0044] In other embodiments, a root index for the extended synchronization signal can be defined as u = rootIndexList[N^ ^ll mod(K)], wherein K is equal to 36. Thirty- six indexes can be defined for the ESS.

[0045] In some examples, an apparatus for a UE comprising one or more baseband processors can detect a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) from a received signal. The signal can be received from the eNodeB. [0046] The apparatus can also derive a reference derive a reference extended synchronization signal (ESS) sequence based on a physical cell ID. The reference ESS sequence can be the ZC sequence. The apparatus can also cross correlate a ESS from the received signal to the reference ESS sequence to determine a cyclic shift of the reference ESS sequence. That is, the received signal can also include the ESS.

[0047] The apparatus can further derive a symbol index from the cyclic shift and the ESS sequence. The symbol index can be used to align the subframe timing with the eNB.

[0048] FIG. 4 is a block diagram illustrating a method for deriving a symbol index according to one embodiment. The method 430 can include detecting 432, at a UE, a PSS and a SSS from a received signal from a eNodeB, deriving 434 a reference ESS sequence based on a physical cell ID, cross correlating 436 a ESS from the received signal to the reference ESS sequence to determine a cyclic shift of the reference ESS sequence, and deriving 438 a symbol index from the cyclic shift and the reference ESS sequence. The symbol index can used to align the subframe timing between the UE and the eNodeB.

[0049] FIG. 5 is a block diagram illustrating components of a device according to one embodiment. In some embodiments, the device may include application circuitry 503, baseband circuitry 505, Radio Frequency (RF) circuitry 507, front-end module (FEM) circuitry 509, and one or more antennas 514, coupled together at least as shown in FIG. 5. Any combination or subset of these components can be included, for example, in a UE device or an eNodeB device.

[0050] The application circuitry 503 may include one or more application processors. By way of non-limiting example, the application circuitry 503 may include one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processor(s) may be operably coupled and/or include memory/storage, and may be configured to execute instructions stored in the memory/storage to enable various applications

and/or operating systems to run on the system.

[0051] By way of non-limiting example, the baseband circuitry 505 may include one or more single-core or multi-core processors. The baseband circuitry 505 may include one or more baseband processors and/or control logic. The baseband circuitry 505 may be configured to process baseband signals received from a receive signal path of the RF circuitry 507. The baseband circuitry 505 may also be configured to generate baseband signals for a transmit signal path of the RF circuitry 507. The baseband circuitry 505 may interface with the application circuitry 503 for generation and processing of the baseband signals, and for controlling operations of the RF circuitry 507.

[0052] By way of non-limiting example, the baseband circuitry 505 may include at least one of a second generation (2G) baseband processor 51 1 A, a third generation (3G) baseband processor 51 1 B, a fourth generation (4G) baseband processor 51 1 C, and other baseband processor(s) 51 1 D for other existing generations and

generations in development or to be developed in the future (e.g., fifth generation (5G), 6G, etc.). The baseband circuitry 505 (e.g., at least one of the baseband processors 51 1 A-51 1 D) may handle various radio control functions that

enable communication with one or more radio networks via the RF circuitry 507. By way of non-limiting example, the radio control functions may include signal modulation/demodulation, encoding/decoding, radio frequency shifting, other functions, and combinations thereof. In some embodiments,

modulation/demodulation circuitry of the baseband circuitry 505 may be programmed to perform Fast-Fourier Transform (FFT), precoding, constellation

mapping/demapping functions, other functions, and combinations thereof. In some embodiments, encoding/decoding circuitry of the baseband circuitry 505 may be programmed to perform convolutions, tail-biting convolutions, turbo, Viterbi, Low Density Parity Check (LDPC) encoder/decoder functions, other functions, and combinations thereof. Embodiments of modulation/demodulation and

encoder/decoder functions are not limited to these examples, and may include other suitable functions.

[0053] In some embodiments, the baseband circuitry 505 may include elements of a protocol stack. By way of non-limiting example, elements of an evolved universal terrestrial radio access network (EUTRAN) protocol include, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), and/or radio resource control (RRC) elements. A central processing unit (CPU) 51 1 E of the baseband circuitry 505 may be

programmed to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers. In some embodiments, the baseband circuitry 505 may include one or more audio digital signal processor(s) (DSP) 51 1 F. The audio DSP(s) 51 1 F may include elements for compression/decompression and echo cancellation. The audio DSP(s) 51 1 F may also include other suitable processing elements.

[0054] The baseband circuitry 505 may further include a memory/storage 51 1 G. The memory/storage 51 1 G may include data and/or instructions for operations performed by the processors of the baseband circuitry 505 stored thereon. In some embodiments, the memory/storage 51 1 G may include any combination of suitable volatile memory and/or non-volatile memory. The memory/storage 51 1 G may also include any combination of various levels of memory/storage including, but not limited to, read-only memory (ROM) having embedded software instructions (e.g., firmware), random access memory (e.g., dynamic random access memory (DRAM)), cache, buffers, etc. In some embodiments, the memory/storage 51 1 G may be shared among the various processors or dedicated to particular processors.

[0055] Components of the baseband circuitry 505 may be suitably combined in a single chip or a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 505 and the application circuitry 503 may be

implemented together, such as, for example, on a system on a chip (SOC).

[0056] In some embodiments, the baseband circuitry 505 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 505 may support communication with an evolved universal terrestrial radio access network (EUTRAN) and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), or a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 505 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0057] The RF circuitry 507 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 507 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. The RF circuitry 507 may include a receive signal path, which may include circuitry to down-convert RF signals received from the FEM circuitry 509, and provide baseband signals to the baseband circuitry 505. The RF circuitry 507 may also include a transmit signal path, which may include circuitry to up-convert baseband signals provided by the baseband circuitry 505, and provide RF output signals to the FEM circuitry 509 for

transmission.

[0058] In some embodiments, the RF circuitry 507 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 507 may include a mixer circuitry 513A, an amplifier circuitry 513B, and a filter circuitry 513C. The transmit signal path of the RF circuitry 507 may include the filter circuitry 513C and the mixer circuitry 513A. The RF circuitry 507 may further include a synthesizer circuitry 513D configured to synthesize a frequency for use by the mixer circuitry 513A of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 513A of the receive signal path may be configured to down- convert RF signals received from the FEM circuitry 509 based on the synthesized frequency provided by the synthesizer circuitry 513D. The amplifier circuitry 513B may be configured to amplify the down-converted signals.

[0059] The filter circuitry 513C may include a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 505 for further processing. In some embodiments, the output baseband signals may include zero-frequency baseband signals, although this is not a requirement. In some embodiments, the mixer circuitry 513A of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

[0060] In some embodiments, the mixer circuitry 513A of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 513D to generate RF output signals for the FEM circuitry 509. The baseband signals may be provided by the baseband circuitry 505 and may be filtered by the filter circuitry 513C. The filter circuitry 513C may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.

[0061] In some embodiments, the mixer circuitry 513A of the receive signal path and the mixer circuitry 513A of the transmit signal path may include two or more mixers, and may be arranged for quadrature downconversion and/or upconversion, respectively. In some embodiments, the mixer circuitry 513A of the receive signal path and the mixer circuitry 513A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 513A of the receive signal path and the mixer circuitry 513A of the transmit signal path may be arranged for direct downconversion and/or direct upconversion, respectively. In some embodiments, the mixer circuitry 513A of the receive signal path and the mixer circuitry 513A of the transmit signal path may be configured for super-heterodyne operation.

[0062] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In such embodiments, the RF circuitry 507 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and the baseband circuitry 505 may include a digital baseband interface to communicate with the RF circuitry 507.

[0063] In some dual-mode embodiments, separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

[0064] In some embodiments, the synthesizer circuitry 513D may include one or more of a fractional-N synthesizer and a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect, as other types of frequency synthesizers may be suitable. For example, the synthesizer circuitry 513D may include a delta-sigma synthesizer, a frequency multiplier, a synthesizer comprising a phase-locked loop with a frequency divider, other synthesizers, and combinations thereof.

[0065] The synthesizer circuitry 513D may be configured to synthesize an output frequency for use by the mixer circuitry 513A of the RF circuitry 507 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 513D may be a fractional N/N+1 synthesizer.

[0066] In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 505 or the application circuitry 503 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the application circuitry 503. [0067] The synthesizer circuitry 513D of the RF circuitry 507 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may include a dual modulus divider (DMD), and the phase accumulator may include a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry-out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements; a phase detector; a charge pump; and a D-type flip-flop. In such embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL may provide negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0068] In some embodiments, the synthesizer circuitry 513D may be configured to generate a carrier frequency as the output frequency. In some embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency, etc.) and used in conjunction with a quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be an LO frequency (fLO). In some embodiments, the RF circuitry 507 may include an IQ/polar converter.

[0069] The FEM circuitry 509 may include a receive signal path, which may include circuitry configured to operate on RF signals received from the one or more antennas 514, amplify the received signals, and provide the amplified versions of the received signals to the RF circuitry 507 for further processing. The FEM circuitry 509 may also include a transmit signal path, which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 507 for transmission by at least one of the one or more antennas 514.

[0070] In some embodiments, the FEM circuitry 509 may include a TX/RX switch configured to switch between a transmit mode and a receive mode operation. The FEM circuitry 509 may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry 509 may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 507). The transmit signal path of the FEM circuitry 509 may include a power amplifier (PA) configured to amplify input RF signals (e.g., provided by the RF circuitry 507), and one or more filters configured to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 514).

[0071] In some embodiments, the device may include additional elements such as, for example, memory/storage, a display, a camera, one of more sensors, an input/output (I/O) interface, other elements, and combinations thereof.

[0072] In some embodiments, the device may be configured to perform one or more processes, techniques, and/or methods as described herein, or portions thereof.

[0073] FIG. 6 is a block diagram illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (e.g., a machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically, FIG. 6 shows a diagrammatic representation of hardware resources 600 including one or more processors (or processor cores) 610, one or more memory/storage devices 620, and one or more communication resources 630, all of which are communicatively coupled via a bus 640.

[0074] The processors 610 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, a processor 612 and a processor 614. The memory/storage devices 620 may include main memory, disk storage, or any suitable combination thereof.

[0075] The communication resources 630 may include interconnection and/or network interface components or other suitable devices to communicate with one or more peripheral devices 604 and/or one or more databases 606 via a network 608. For example, the communication resources 630 may include wired communication components (e.g., for coupling via a Universal Serial Bus (USB)), cellular

communication components, Near Field Communication (NFC) components,

Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components. [0076] Instructions 650 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least one of the processors 610 to perform any one or more of the methodologies discussed herein. The instructions 650 may reside, completely or partially, within at least one of the processors 610 (e.g., within the processor's cache memory), the memory/storage devices 620, or any suitable combination thereof. Furthermore, any portion of the instructions 650 may be transferred to the hardware resources 600 from any combination of the peripheral devices 604 and/or the databases 606. Accordingly, the memory of the processors 610, the memory/storage devices 620, the peripheral devices 604, and the databases 606 are examples of computer-readable and machine-readable media.

Example Embodiments

[0077] Example 1 is an apparatus for a user equipment (UE). The apparatus contains baseband processors to detect a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) from a received signal. The apparatus contains baseband processors to derive a reference extended synchronization signal (ESS) sequence based on a physical cell ID. The apparatus further contains baseband processors tocross correlate a ESS from the received signal to the reference ESS sequence to determine a cyclic shift of the reference ESS sequence, and to derive a symbol index from the cyclic shift and the reference ESS sequence.

[0078] Example 2 is the apparatus of Example 1 , where the symbol index is used to align the subframe timing between the UE and an eNodeB.

[0079] Example 3 is a computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to access a physical cell identification (ID) of an evolved node B (eNodeB). A computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to generate a root index based on the physical cell ID. A computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, further causes the computing device to generate an extended synchronization signal with the root index, where the extended synchronization signal spans multiple symbols within a subframe, and where the extended synchronization signal is generated based on the physical cell ID. [0080] Example 4 is the computer-readable storage medium of Example 3, where the extended synchronization signal spans 12 or 14 symbols within the subframe.

[0081] Example 5 is the computer-readable storage medium of Example 3, where the extended synchronization signal spans multiple physical resource blocks within the subframe.

[0082] Example 6 is the computer-readable storage medium of Example 3, where the extended synchronization signal spans six physical resource blocks within the subframe.

[0083] Example 7 is the computer-readable storage medium of Example 3, where the extended synchronization signal spans 72 subcarriers within the subframe.

[0084] Example 8 is the computer-readable storage medium of Example 3, where the extended synchronization signal is part of a downlink signal.

[0085] Example 9 is the computer-readable storage medium of Example 8, where the eNodeB is part of a 5G system.

[0086] Example 10 is an apparatus for an evolved NodeB (eNodeB). The apparatus contains electronic memory and one or more processors designed to access a physical cell identification (ID) of an eNodeB and generate a root index based on the physical cell ID. The apparatus contains electronic memory and one or more processors designed to generate for a user equipment (UE) a downlink signal including an extended synchronization signal, a primary synchronization signal, and a secondary synchronization signal where the extended synchronization signal spans multiple symbols within a subframe and where the extended synchronization signal is generated based on the physical cell ID of the eNodeB.

[0087] Example 1 1 is the apparatus of Example 10, where the extended synchronization signal is based on the entire physical cell ID.

[0088] Example 12 is the apparatus of Example 10, where the extended synchronization signal is based on a portion of the physical cell ID.

[0089] Example 13 is the apparatus of Example 10, where the root index for the extended synchronization signal is selected from a root index list based on the physical cell ID.

[0090] Example 14 is the apparatus of Example 13, where the root index list is given as 1 , 2, 4, 5, 8, 10, 1 1 , 13, 16, 17, 19, 20, 22, 23, 25, 26, 29, 31 , 32, 34, 37, 38, 40, 41 , 43, 44, 46, 47, 50, 52, 53, 55, 58, 59, 61 , 62. [0091] Example 15 is the apparatus of Example 14, where the root index is given as u=rootlndexList[f(N_ID ^A cell )], and where N_ID ^A cell is the physical cell ID, f(N_ID ^A cell ) is a function of the physical cell ID, and rootlndexList is the list of root indexes.

[0092] Example 16 is the apparatus of Example 10, where a root index for the extended synchronization signal is given as u=rootlndexList[M-[(N_ID ^A cell)/LJ] where rootlndexList is a list of root indexes, M is a constant, L is a constant, and N_ID ^A cell is the physical cell ID.

[0093] Example 17 is the apparatus of Example 16, where M is equal to 1 and L is equal to 12 or 14.

[0094] Example 18 is the apparatus of Example 16, where 36 root indexes can be defined for the extended synchronization signal.

[0095] Example 19 is the apparatus of Example 16, where nine root indexes are defined for the extended synchronization signal.

[0096] Example 20 is the apparatus of Example 10, where a root index for the extended synchronization signal is given as u=rootlndexList[N_ID ^A cell mod(K)] where rootlndexList is a list of root indexes, K is a constant, and mod() is a modular operation.

[0097] Example 21 is the apparatus of Example 20, where K is equal to 36.

[0098] Example 22 is a method including detecting a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) from a received signal. The method also includes deriving a reference extended synchronization signal (ESS) sequence based on a physical cell ID. The method also includes cross correlating a ESS from the received signal to the reference ESS sequence to determine a cyclic shift of the reference ESS sequence. The method also includes deriving a symbol index from the cyclic shift and the reference ESS sequence.

[0099] Example 23 is the method of Example 22, where the symbol index is used to align the subframe timing between the UE and an eNodeB.

[0101] Example 24 is a method including accessing a physical cell identification (ID) of an evolved node B (eNodeB). The method also includes generating a root index based on the physical cell ID. The method also includes generating an extended synchronization signal with the root index, where the extended

synchronization signal spans multiple symbols within a subframe, and where the extended synchronization signal is generated based on the physical cell ID. [0102] Example 25 is the method of Example 24, where the extended

synchronization signal spans 12 or 14 symbols within the subframe.

[0103] Example 26 is the method of Example 24, where the extended

synchronization signal spans multiple physical resource blocks within the subframe.

[0104] Example 27 is the method of Example 24, where the extended

synchronization signal spans six physical resource blocks within the subframe.

[0105] Example 28. The method of Example 24, where the extended synchronization signal spans 72 subcarriers within the subframe.

[0106] Example 29 is the method of Example 24, where the extended

synchronization signal is part of a downlink signal.

[0107] Example 30 is the method of Example 29, where the eNodeB is part of a 5G system.

[0108] Example 31 is a method including accessing a physical cell identification (ID) of an evolved node B ( eNodeB). The method also includes generating a root index based on the physical cell ID. The method also includes generating for a user equipment (UE) a downlink signal including an extended synchronization signal, a primary synchronization signal, and a secondary synchronization signal, where the extended synchronization signal spans multiple symbols within a subframe, and where the extended synchronization signal is generated based on the physical cell ID of the eNodeB.

[0109] Example 32 is the method of Example 31 , where the extended

synchronization signal is based on the entire physical cell ID.

[0110] Example 33 is the method of Example 31 , where the extended

synchronization signal is based on a portion of the physical cell ID.

[0111] Example 34 is the method of Example 31 , where the root index for the extended synchronization signal is selected from a root index list based on the physical cell ID.

[0112] Example 35 is the method of Example 34, where the root index list is given as 1 , 2, 4, 5, 8, 10, 1 1 , 13, 16, 17, 19, 20, 22, 23, 25, 26, 29, 31 , 32, 34, 37, 38, 40, 41 , 43, 44, 46, 47, 50, 52, 53, 55, 58, 59, 61 , 62.

[0113] Example 36 is the method of Example 35, where the root index is given as u=rootlndexList[f(N_ID ^A cell )], and where N_ID ^A cell is the physical cell ID, f(N_ID ^A cell ) is a function of the physical cell ID, and rootlndexList is the list of root indexes. [0114] Example 37 is the method of Example 31 , where a root index for the extended synchronization signal is given as u=rootlndexList[M-[(N_ID ^A cell)/LJ] where rootlndexList is a list of root indexes; M is a constant, L is a constant, and N_ID ^A cell is the physical cell ID.

[0115] Example 38 is the method of Example 37, where M is equal to 1 and L is equal to 12 or 14.

[0116] Example 39 is the method of Example 37, where 36 root indexes can be defined for the extended synchronization signal.

[0117] Example 40 is the method of Example 37, where nine root indexes are defined for the extended synchronization signal.

[0118] Example 41 is the method of Example 31 , where a root index for the extended synchronization signal is given as u=rootlndexList[N_ID ^A cell mod(K)] where rootlndexList is a list of root indexes, K is a constant, and mod() is a modular operation.

[0119] Example 42 is the method of Example 41 , where K is equal to 36.

[0120] Example 43 is a computer-readable storage medium having stored thereon computer-readable instructions, when executed, to implement a method as exemplified in any of Examples 22-42.

[0121] Example 44 is an apparatus including the procedure to perform a method as exemplified in any of Examples 22-42.

[0122] Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, a non-transitory computer-readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. In the case of program code execution on programmable computers, the computing device may include a processor, a storage medium readable by the processor (including volatile and nonvolatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and non-volatile memory and/or storage elements may be a RAM, an EPROM, a flash drive, an optical drive, a magnetic hard drive, or another medium for storing electronic data. The eNodeB (or other base station) and UE (or other mobile station) may also include a transceiver component, a counter

component, a processing component, and/or a clock component or timer component. One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like. Such programs may be implemented in a high-level procedural or an object-oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or an interpreted language, and combined with hardware implementations.

[0123] It should be understood that many of the functional units described in this specification may be implemented as one or more components, which is a term used to more particularly emphasize their implementation independence. For example, a component may be implemented as a hardware circuit comprising custom very large scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.

[0124] Components may also be implemented in software for execution by various types of processors. An identified component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, a procedure, or a function.

Nevertheless, the executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations that, when joined logically together, comprise the component and achieve the stated purpose for the component.

[0125] Indeed, a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code

segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within components, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. The components may be passive or active, including agents operable to perform desired functions. [0126] Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, appearances of the phrase "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0127] As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on its presentation in a common group without indications to the contrary. In addition, various embodiments and examples may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of embodiments.

[0128] Although the foregoing has been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be made without departing from the principles thereof. It should be noted that there are many alternative ways of implementing both the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.