Related applications

This application claims the benefit of U.S. Provisional Application 60/607,691, filed September 7, 2004, the entire disclosure of which is hereby incorporated by reference. Background High quality electro-optical layers are needed for fabrication of optical waveguides. Such layers may include crystalline material formed over semiconductor substrates. Barium titanate (BaTiO3 or, hereafter, BT), in particular, has attracted a great deal of attention in recent years for its electro-optic (E-O) and piezo-electric properties. Its large E-O coefficient, for example, may enable the fabrication of highly miniaturized optical modulators for fiber optic- based data transmission systems. To exploit the advantage of miniaturization, the integration of electro-optical layers onto semiconductor substrates, such as silicon (Si) substrates, is desirable. Silicon, in particular, represents an especially useful substrate material in that it can take the form of a high-quality single crystal and provides the basis for most microelectronics. The formation of electro-optical layers directly on a bulk silicon substrate or on a thick silicon layer, however, may result in difficulties in confining light to the electro-optical layer due to possible losses to the underlying silicon material. The higher refractive index of silicon can draw light from an electro-optical waveguide, for example. Summary The present invention facilitates formation of electro-optical layers on semiconductor- on-insulator (SOI) substrates having thin crystalline top layers, with or without buffer layers. For example, highly oriented BaTiO3-based thin films, suitable for microphotonic application, may be grown and integrated onto Si wafers by utilization of silicon-on-insulator substrates. Such substrates generally include a relatively thin layer of crystalline semiconductor material, such as silicon, over an insulator, which itself resides above a semiconductor, e.g., silicon, substrate. SOI structures have gained importance in the semiconductor industry because of their ability to limit transistor gate capacitance, thereby enabling faster switching speeds. Preferably, several criteria should be satisfied when integrating electro-optical thin films onto semiconductor substrates. First, the electro-optical layer should be grown in an epitaxial fashion, highly oriented along a crystalline direction, to provide a relatively high E-O effect. Preferably, the electro-optical layer is grown with a (001) orientation. Second, the electro- optical layer should be sufficiently spatially separated from the semiconductor substrate to optically decouple a device formed in the electro-optical film from the higher refractive index semiconductor substrate. This separation may be achieved by the formation of one or more layers between the substrate and the electro-optical layer. Lastly, the layer(s) separating the electro-optical layer from the underlying semiconductor substrate should have an index of refraction lower than that of the electro-optical layer to insure confinement of light within the subsequently formed waveguides, and should be chemically stable in contact with the electro- optical layer. These criteria may be satisfied by the use of commercially available SOI wafers with a sufficiently thick insulator layer, e.g., an oxide layer, to optically decouple the E-O waveguide structures from the semiconductor substrate, and a thin, high-quality, single-crystalline semiconductor top layer, capable of initiating the growth of high quality epitaxial films thereover. Atypical thickness of the insulator layer is from 1 to 3 micrometers (μm), although, for some applications, the required insulator thickness may be as high as 10 μm. However, if the top crystalline semiconductor layer of an SOI wafer is too thick, e.g., > 100 nanometers (nm), light leakage may result from the electro-optical layer into the crystalline semiconductor top layer. One solution to this problem is to insert another buffer layer between the electro-optical and the crystalline semiconductor top layer sufficiently thick to optically decouple these layers. This solution, however, may introduce additional complexity into the waveguide design and fabrication process. Moreover, because the thick intermediate oxide of the SOI wafer already serves to decouple the electro-optical layer from the underlying semiconductor substrate, the buffer layer(s) are not needed for decoupling the electro-optical layer from the underlying semiconductor substrate. On the other hand, it has been found that a crystalline semiconductor layer having a thickness no greater than 100 nm may prevent light leakage between the electro-optical layer and the top crystalline semiconductor layer. In some embodiments, the original crystalline semiconductor layer is no thicker than 100 nm, while in other embodiments, the layer is thinned to a suitable thickness (e.g., less than or equal to about 50 nm). In still other embodiments, the crystalline semiconductor layer is oxidized completely during or subsequent to the process of depositing buffer or electro-optical layers. In accordance with the invention, a semiconductor crystalline layer no thicker than about 100 nm placed over an insulating layer provides a suitable basis for growing an electro-optical crystalline layer and at the same time has no significant optical effects on the optical radiation propagating in the electro-optical crystalline layer. In one aspect, therefore, the invention features an optical waveguide structure that includes a semiconductor substrate, an insulator layer disposed over the semiconductor substrate, a crystalline semiconductor layer disposed over the insulator layer, and an electro-optical layer disposed over the crystalline semiconductor layer. The crystalline semiconductor layer desirably has a thickness less than or equal to approximately 100 nm. The electro-optical layer may include at least one Of BaTiO3, PbTiO3, (Pb5La)TiO3, (Pb5Zr)TiO3, (Pb5La)(Zr5Ti)O3, ZrTiO3, LaZrTiO3, LiNbO3, LiTaO3, SrxBa1-xNb206 (SBN:x), Ba1-xCaxTiO3 with x selected from a range of about 0.2 to about 0.5, KNbO3, and KNbTaO3, and may have a thickness ranging from about 500 nm to about 1000 nm. The electro-optical layer may also be thicker or thinner depending on the specific waveguide. For a ridge waveguide, a thickness ranging from 300 nm to about 2 μm is preferred; for an indiffused waveguide, a higher thickness may be needed, i.e., 10 μm. The crystalline semiconductor layer includes a semiconductor material, such as silicon, and its thickness may be less than approximately 100 nm and, more desirably, no greater than 50 nm. A first buffer layer may be disposed between the electro-optical layer and the crystalline semiconductor layer. The first buffer layer may include at least one of MgO, MgAl2O4, Al2O3, LaAlO3, LSAT (LaAlO3)0.3(Sr2AlTaO6)0.7, CeO2, Y2O3, YSZ, BaO, SrO, Ba1-xSrxO, SrTiO3, PbxBa1-xTiO3, BaTiO3, and Ba1-xSrxTiO3. The thickness of the first buffer layer may be selected from a range of approximately 30 nm to approximately 3000 nm. A first buffer layer thickness below 500 nm helps to achieve a high quality, highly oriented electro-optical layer. Moreover, in contrast to a thicker film, less process time is necessary to grow a thin layer, the thickness may be more uniform, and the thin layer is more likely to be dislocation-free. A second buffer layer may be disposed over the first buffer layer. The second buffer layer may include at least one of MgO, MgAl2O4, Al2O3, LaAlO3, LSAT (LaA103)0.3(Sr2AlTa06)o.7j CeO2, Y2O3, YSZ, BaO, SrO, Ba1-xSrx0, SrTiO3, PbxBa1-JiO3, BaTiO3, and Ba1-xSrxTiO3. The second buffer layer may have a thickness selected from a range of about 10 nm to about 3000 nm. A ridge layer may be disposed over the electro-optical layer. The ridge layer may include a dielectric material, such as at least one of Si3N4, silicon-rich nitride (SIN), hydrogensilsesquioxanes (HSQ), SiO2, yttrium-stabilized zirconia (YSZ), CeO2, MgO, BaO, SrO, Ba1-xSrxO, MgAl2O4, LaAlO3, LSAT (LaAlO3)0.3(Sr2AlTaO6)0.7, Al2O3, Y2O3, BaTiO3, PbTiO3, (Pb5La)TiO3, (Pb5Zr)TiO3, (Pb5La)(Zr5Ti)O3, ZrTiO3, LaZrTiO3, LiNbO3, LiTaO3, SrxBa1-XNb2O6 (SBN:x), Ba1-xCaxTi03 with x selected from a range of about 0.2 to about 0.5, KNbO3, and KNbTaO3. A ridge may be defined by a lift-off technique, an etch step, and/or transforming a portion of an HSQ layer into silicon dioxide. The ridge material and method of ridge formation may be selected to define a ridge with relatively smooth sidewalls, thereby enhancing light confinement. The ridge-material may include a material with an index of refraction similar to that of the electro-optical layer. ( A cladding layer may be disposed over the electro-optical layer and the ridge layer. The cladding layer should have an index of refraction lower than that of the electro-optical layer, and may include at least one of silicon dioxide, Si3N4, SIN, HSQ, a polymer, MgO, and Al2O3. In typical applications, one or more electrodes are disposed in electrical communication with the electro-optical layer. The insulator layer may be amorphous. The insulator layer may include silicon dioxide, silicon nitride, aluminum oxide, and/or magnesium oxide. In another aspect, an optical waveguide structure includes an amorphous insulator layer, and an electro-optical layer in contact with the amorphous insulator layer. In another aspect, the invention features a method for forming an optical waveguide structure, including the steps of (i) providing an insulator layer, and a crystalline semiconductor layer disposed over the insulator layer; (ii) forming an electro-optical layer over the crystalline semiconductor layer; and (iii) controlling the thickness of the crystalline semiconductor layer to be no greater than about 100 nm. Forming the electro-optical layer may include selecting a crystallographic orientation of the electro-optical layer, such as by growing the electro-optical layer in the preferred crystallographic orientation, or by poling and/or cleaving. The crystallographic direction may be determined by a crystallographic orientation of the crystalline semiconductor layer. The electro- optical layer may be formed using at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, a sol-gel technique, screen printing, and layer transfer. The step of controlling the thickness of the crystalline semiconductor layer may be performed prior to forming the electro-optical layer. The thickness of the crystalline semiconductor layer may be controlled to be no greater than 50 nm. The crystalline semiconductor layer may include or consist of a semiconductor, such as silicon. A first buffer layer may be formed over the crystalline semiconductor layer, such as by at least one of physical vapor deposition (e.g. sputtering or pulsed laser deposition), chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, and a sol-gel technique. Using any or a combination of these techniques, a second buffer layer may be formed over the first buffer layer, and a ridge may be formed over the electro-optical layer. Forming the ridge layer may include forming an HSQ layer, and a portion of the HSQ layer may be transformed, e.g., by exposure by an electron beam, into silicon dioxide to define a ridge. Finally, a cladding layer may be formed over the electro-optical layer. An electrode in electrical communication with the electro-optical layer may be formed. In another aspect, the invention includes a method for forming an optical waveguide structure, including the steps of (i) providing an insulator layer, and a crystalline semiconductor layer disposed over the insulator layer, (ii) forming an electro-optical layer over the crystalline semiconductor layer, and (iii) essentially completely oxidizing the crystalline semiconductor layer. Oxidizing the crystalline semiconductor layer may involve a high temperature anneal. Oxidizing the crystalline semiconductor layer may involve oxygen diffusion through the electro- optical layer. A first and possibly additional buffer layer(s) may be formed over the crystalline semiconductor layer, and oxidizing the crystalline semiconductor layer may involve oxygen diffusion through the first buffer and/or additional buffer layers. Brief Description of Drawings Figures IA -IH are schematic cross-sectional and perspective views illustrating a method for fabricating a structure including an electro-optical layer in accordance with the invention; Figures 2A- 2B are schematic cross-sectional views illustrating alternative embodiments including buffer layers; Figures 3 A-3D are schematic cross-sectional views illustrating an alternative method for fabricating a structure including an electro-optical layer in accordance with the invention; Figures 4A-4D are schematic cross-sectional views illustrating another alternative method for fabricating a structure including an electro-optical layer in accordance with the invention; Figures 5A-5D are schematic cross-sectional views illustrating yet another alternative method for fabricating a structure including an electro-optical layer in accordance with the invention; and Figures 6A-6D are schematic cross-sectional views and graphs illustrating the light propagation characteristics of a waveguide made in accordance with the invention. Like-referenced features represent common features in corresponding drawings. Detailed Description In accordance with the present invention, high-quality electro-optical materials, such as BT, are formed on crystalline materials such as silicon. In particular, an electro-optical layer is formed over a thin crystalline semiconductor layer, such as silicon, that enables the epitaxial formation thereover of a high-quality layer. An insulating layer may keep the electro-optical layer optically decoupled from an underlying semiconductor substrate. This approach results in structures with reduced light losses to underlying material during operation of optical devices, and can utilize conventional, readily available SOI wafers for the fabrication of waveguides. It is to be understood that the presence of an underlying semiconductor substrate is not essential to the invention. The insulating layer may also act as an underlying substrate. Referring to Figure IA, an SOI wafer 100 may include a semiconductor substrate 110 formed of a semiconductor material, such as a group IV material, a III-V material, or a II- VI material, and may include or consist of Si, Ge, SiGe, SiC, GaAs, InP, or GaN; a preferred substrate 110 includes or consists of Si. An insulator layer 120 may be disposed over the semiconductor substrate 110. Insulator layer 120 may include or consist of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4 or other compositions), aluminum oxide, magnesium oxide, and/or other dielectric materials, or may be a multilayer structure including one or more different materials. The insulator layer 120 may have a thickness ti ranging from approximately 2 to 10 or more (e.g., up to approximately 100) μm, although the preferred thickness t\ range is approximately 3 to 10 μm. The economics of fabrication may favor relatively thin insulator layers, while the need to optically couple to large-diameter fibers may require relatively thick layers. A crystalline semiconductor layer 130 may be disposed over the insulator layer 120. The crystalline semiconductor layer 130 may include or consist of a semiconductor material, such as a group IV material, a III-V material, or a II- VI material (e.g., Si, Ge, SiGe, SiC, GaAs, InP, and/or GaN). In a preferred embodiment, the crystalline semiconductor layer 130 includes or consists of Si. The crystalline semiconductor layer 130 preferably has a thickness t2 greater than 0 A, i.e., sufficient to enable epitaxial growth of electro-optical or other crystalline layers over the crystalline semiconductor layer 130; this may involve as few as one or several atomic - I -

layers. To prevent any significant optical loss from a waveguide fabricated over the crystalline semiconductor layer 130 to the crystalline semiconductor layer 130, the crystalline semiconductor layer 130 should be thinner than -100 nm, and ideally is no thicker than ~50 nm. Commercially available SOI wafers generally include a top crystalline silicon layer having a thickness greater than or equal to 300 nm, typically up to 1000 nm. Managing this excess thickness is discussed below. Referring to Figure IB, an electro-optical layer 140 may be disposed over the crystalline semiconductor layer 130. The electro-optical layer 140 may include a material having a relatively high E-O effect, e.g., higher than 20 pm/V, such as BaTiO3, PbTiO3, (Pb5La)TiO3, (Pb5Zr)TiO3, (Pb5La)(Zr5Ti)O3, ZrTiO3, LaZrTiO3, LiNbO3, LiTaO3, SrxBa1-xNb206 (SBN:x), Ba1-xCaxTiO3 with x selected from a range of about 0.2 to about 0.5, KNbθ3, and KNbTaθ3. The electro-optical layer 140 generally has a thickness t3 suitable for use as a waveguide. Preferably, thickness t3 ranges from about 500 nm to about 1000 nm, although the electro-optical layer 140 may be thicker or thinner depending on the specific waveguide for which it will be used. For example, for a ridge waveguide, a thickness t3 ranging from 300 nm to about 2 μm may be preferred; for an indiffused waveguide, a higher thickness t3 may be needed, e.g., 10 μm. The electro-optical layer 140 may be formed by a suitable deposition process, such as physical vapor deposition (e.g., sputtering by use of, e.g., a sputtering deposition tool manufactured by Kurt J. Lesker or pulsed laser deposition by use of, e.g., a LPX325i system manufactured by Lambda Physics); chemical vapor deposition; atomic layer deposition; molecular beam epitaxy; a sol-gel technique; screen printing; or electro-optical layer transfer from a single crystal substrate using ion slicing and wafer bonding techniques. The electro-optical layer 140 may be formed with a particular crystallographic orientation. The crystallographic orientation of the electro-optical layer 140 may be determined by growing the electro-optical layer 140 in a particular crystallographic orientation, which itself may be determined by a crystallographic orientation of the underlying crystalline layer 130. Alternatively, the crystallographic direction of the electro-optical layer 140 may be selected by poling or cleaving the layer. For example, the electro-optical layer 140 may have a highly (110)/( 101) orientation when it is grown on a YSZ, CeO2, or SrTiO3 buffer layer on an SOI wafer 100. The orientation of such polycrystalline electro-optical layer 140 may be modified by poling and cleaving to obtain, e.g., (001) crystallographic orientation. The insulator layer 120 may ultimately serve to optically decouple, i.e., optically isolate the electro-optical layer 140 from the semiconductor substrate 110 (which typically has a higher refiractive index). Referring to Figure 1C, a ridge 150 may be defined by patterning the electro-optical layer 140. The ridge 150 may serve as a waveguide in a finished device, in which case it will have dimensions suitable for use as a waveguide, e.g., a height Ji1 of about 50 nm to about 400 nm and a width W1 of about 300 nm to about 3000 nm. The ridge 150 may be defined by patterning the electro-optical layer 140 by, e.g., the definition of a photoresist mask (not shown) and an etch step, e.g., an anisotropic etch. Referring to Figures ID and IE, an alternative method for defining the ridge 150 may include the use of a lift-off technique, which permits use of different materials for ridge 150 and electro-optical layer 140. Here, a photoresist layer (not shown) is defined over the electro- optical layer 140 and exposed, such that substantially no photoresist remains on the regions of the electro-optical layer 140 over which the ridge 150 will be defined. A ridge layer (not shown) may be formed over the photoresist layer. The photoresist layer and portions of the ridge layer disposed over the photoresist layer are then lifted off by developing the photoresist layer, leaving behind ridge 150. Referring to Figures IF- IG, in another alternative embodiment, the ridge 150 may be defined by the use of HSQ. A ridge layer 155 including or consisting of HSQ is spun onto a top surface of the electro-optical layer 140. The ridge layer 155 may have a thickness t10 selected from a range of about 400 nm to 5000 nm. A region 155a of the HSQ ridge layer 155 may be exposed with an electron beam 157 to define the ridge 150. Upon exposure to the electron beam, HSQ is transformed to SiO2. After the exposure of the region 155a, unexposed regions 155b are developed and washed away. Ridge 150 including or consisting of silicon dioxide disposed over the electro-optical layer is thereby defined. A suitable anneal may be performed to complete the SiO2 transformation and to reduce possible optical losses. It is to be understood that the method of defining a ridge waveguide by the use of HSQ described above is a method of fabrication of silicon dioxide waveguides that may find applications in a more general context than the one of the present invention. It may be used for forming a silicon dioxide ridge waveguide over a dielectric layer having a refractive index higher than, or equal to, that of silicon dioxide. In an embodiment, the dielectric layer may comprise SIN or SiO2. The ridge 150 may include a dielectric material, such as Si3N4, silicon-rich nitride (SIN), HSQ, SiO2, YSZ, CeO2, MgO, BaO, SrO, Ba1-xSrxO, MgAl2O4, LaAlO3, LSAT (LaA103)0.3(Sr2AlTa06)o.7) Al2O3, Y2O3, BaTiO3, PbTiO3, (Pb5La)TiO3, (Pb5Zr)TiO3, (Pb5La)(Zr5Ti)O3, ZrTiO3, LaZrTiO3, LiNbO3, LiTaO3, SrxBa1-xNb206 (SBN:x), Ba1-xCaxTiO3 - y -

with x selected from a range of about 0.2 to about 0.5, KNbO3, and/or KNbTaO3. The ridge material and method of ridge formation may be selected to define a ridge with relatively smooth sidewalls, thereby enhancing light confinement. The ridge material may include a material with an index of refraction similar to that of the electro-optical layer. In an exemplary embodiment, ridge 150 is formed from Si3N4 and the electro-optical layer 140 consists OfBaTiO3. The use Of Si3N4 enables the formation of a ridge 150 with smoother sidewalls than may be achieved with a ridge formed from BaTiO3, thereby enhancing light confinement. The material of the ridge 150 may be selected to have an index of refraction similar to that of the electro-optical layer 140. For example, ridge 150 may be formed from SIN with an index of refraction of 2.2, and the electro-optical layer 140 may be formed from BaTiO3 with an index of refraction of 2.25. Referring to Figure IH, a first electrode 160a and a second electrode 160b may be formed to enable electrical communication with the electro-optical layer 140. The electrodes 160a, 160b may be formed, for example, above the electro-optical layer 140. The first and second electrodes 160a, 160b may be formed from a conductive material, such as Au, Au/Ti, Pt, Cr, Ag, Ir, Ru, and/or Ni. For example, the electrodes 160a, 160b may be defined by the formation of a conductive layer by, e.g., deposition, followed by patterning the conductive layer by, e.g., photoresist definition and an anisotropic etch. A cladding layer 170 may be formed over the electro-optical layer 140 and ridge 150. The cladding layer 170 may include a material having a refractive index less than that of the electro-optical layer 140 and ridge 150. Suitable materials include, e.g., silicon dioxide, Si3N4, SIN, SiON, HSQ, a polymer such as polymethyl methacrylate (PMMA), MgO, and Al2O3. Referring to Figures 2A and 2B, in an embodiment, buffer layers (e.g., a first buffer layer 180 and, optionally, a second buffer layer 190) may be grown between the crystalline semiconductor layer 130 and the electro-optical layer 140 to prevent chemical reaction between the layers 130, 140, and to control the orientation and quality of the electro-optical layer 140. These first and second buffer layers 180, 190 may include or consist of, e.g., MgO, MgAl2O4, Al2O3, LaAlO3, LSAT (LaA103)0.3(Sr2AlTa06)o.7, CeO2, Y2O3, YSZ, BaO, SrO, Ba1-xSrxO (-0.3 < x < ~1), SrTiO3, PbxBa1-XTiO3, BaTiO3, Ba1-xSrxTiO3 (-0.3 < x < -1) or some combination of these materials. The first buffer layer 180 may have a thickness t4 and the second buffer layer 190 may have a thickness ts, with each thickness t4, t5 selected from a range of about 10 nm to about 3000 nm, preferably about 200 nm to about 500 nm. The use of a relatively thick first buffer layer 180 and/or second buffer layer 190 may enhance optical decoupling, as well as enable the formation of relatively crack-free electro-optical layer 140. Buffer layers that are too thick, however, may crack or peel off. In an exemplary embodiment, the electro-optical layer 140 consists Of BaTiO3 having a thickness t3 selected from a range of approximately 500 nm to approximately 1000 nm. The first buffer layer 180 consists of MgO with a thickness t4 of about 200 nm. In an alternative exemplary embodiment, the electro-optical layer 140 consists Of BaTiO3 having a thickness t3 selected from a range of approximately 500 nm to approximately 1000 nm. The electro-optical layer 140 is disposed over second buffer layer 190, which consists Of (Pb3Ba)TiO3 and has a thickness t$ of equal to or less than 50 nm. The second buffer layer 190 is disposed over the first buffer layer 180 consisting of MgO with a thickness t4 of about 200 nm. In both exemplary embodiments, the electro-optical layer 140 and the first buffer layer 180 may be disposed over an SOI wafer. The electro-optical layer 140 may include BT. Then, in an embodiment with only one buffer layer, the first buffer layer 180 may include a very thin Ba1-xSrxTiO3 (-0.3 <x< ~1) seed layer (with thickness t4 equal to or less than 50 nm) that may be used to control the BaTiO3 orientation. Electro-optical layer 140 may include material having a selected crystalline orientation. In an exemplary structure, SOI wafer 100 may include a crystalline semiconductor layer 130 having a thickness t2 of 100 nm or less, preferably 50 nm or less, and an insulator layer 120 including SiO2 and having thickness ti of about 3000 nm. A first buffer layer 180 including MgO and having a thickness t4 of 200 nm is disposed over the crystalline semiconductor layer 130. Electro-optical layer 140 may include BaTiO3 having a strong (001) crystallographic orientation, with a thickness t3 selected form a range of about 500 nm to 1000 nm. In another exemplary embodiment, as above, SOI wafer 100 may include crystalline layer 130 with a thickness t2 of 100 nm or less, preferably 50 nm or less, and insulator layer 120 including SiO2 and having thickness ti of about 3000 nm. A first buffer layer 180 consisting of MgO and having a thickness t4 of about 200 nm is disposed over the crystalline semiconductor layer 130. A second buffer layer 190 including Pb1-xBaxTiO3 with x = 0.9 may be disposed over the first buffer layer 180. The thickness t5 of the second buffer layer 190 is less than 100 nm. Electro-optical layer 140 consists Of BaTiO3 having a strong (001) crystallographic orientation, with a thickness t3 selected form a range of about 500 nm to 1000 nm. In an embodiment, prior to the formation of the electro-optical layer 140, crystalline semiconductor layer 130 may be thinned to the desired thickness t2 (generally less than 100 nm) if, for example, a conventional SOI wafer is employed. The thickness of the crystalline semiconductor layer may be controlled to be no greater than 100 nm. For example, if the starting SOI wafer has a semiconductor top layer (e.g., crystalline semiconductor layer 130) with an initial thickness of greater than ~100 nm, the crystalline semiconductor layer 130 may be thinned by, e.g., oxidation, before or after the deposition of overlying layers, or by, e.g., polishing or etching before the deposition of overlying layers. Furthermore, thinning may involve a multi- step process beginning, for example, with oxidation followed by a chemical etch and, optionally, a dry etch, as is well-known in the art. Oxidation may be partial, i.e., so that a residual thin crystalline semiconductor layer 130 exists at the end of the fabrication process, or complete, i.e. so that the crystalline semiconductor layer 130 is essentially gone at the end of the process. In any event, complete oxidation may not take place before the deposition of the overlaying layer has started. Oxidation may be initiated by diffusion of oxygen from the atmosphere through the layers deposited over the SOI structure, either after the buffer layer growth or after the electro- optical layer growth. The oxidation step may be performed even if the semiconductor top layer is less than 100 nm thick. / More specifically, referring to Figure 3 A, in an embodiment, an initial thickness t2 of crystalline semiconductor layer 130, disposed over insulator layer 120, is greater than 100 nm. First buffer layer 180 is disposed over crystalline semiconductor layer 130. A high temperature anneal is performed, e.g., at a temperature selected from a range of about 600 0C to about 900 0C for approximately 0.1 to 3 hours in an oxygen or air ambient. During this annealing step, oxygen diffuses through the first buffer layer 180 to the crystalline semiconductor layer 130. Referring to Figure 3 B, the crystalline semiconductor layer 130 may be completely oxidized, resulting in a thicker insulator layer in direct contact with first buffer layer 180. Referring to Figure 3 C and 3D, electro-optical layer 140 may be formed over first buffer layer 180, and ridge 150 may be defined either from or over the electro-optical layer 140. In another embodiment, the crystalline semiconductor layer is oxidized after the formation of the electro-optical layer 140. Referring to Figure 4A, the first buffer layer 180 is disposed over the crystalline semiconductor layer 130. The electro-optical layer 140 is disposed over the first buffer layer 180. Referring to Figure 4B, a high temperature anneal is performed, e.g., at a temperature selected from a range of about 600 0C to about 900 0C for approximately 0.1 to 3 hours in an oxygen or air ambient. During this annealing step, oxygen diffuses through the electro-optical layer 140 and the first buffer layer 180 to the crystalline semiconductor layer 130. Referring to Figure 4C, the crystalline semiconductor layer 130 may be completely oxidized, resulting in a thicker insulator layer in direct contact with first buffer layer 180. Referring to Figure 4D, ridge 150 may be defined either from or over the electro-optical layer 140. Referring to Figures 5A-5D, in an alternative embodiment, the electro-optical layer 140 may be disposed over and in contact with insulator layer 120 (i.e., there is no first buffer layer 180). The insulator layer 120 includes an amorphous, i.e., non-crystalline material. This structure may be obtained as follows. Referring to Figure 5 A, electro-optical layer 140 is disposed directly on crystalline semiconductor layer 130, as discussed above with reference to Figures IA and IB. Referring to Figure 5B, a high temperature anneal is performed, e.g., at a temperature selected from a range of about 600 0C to about 900 0C for approximately 0.1 to 3 hours in an oxygen or air ambient. During this annealing step, oxygen diffuses through the electro-optical layer 140 to the crystalline semiconductor layer 130. Referring to Figure 5C, the crystalline semiconductor layer 130 may be completely oxidized, resulting in the electro-optical layer being disposed over and in direct contact with amorphous insulator 120. Referring to Figure 5D, ridge 150 may be defined either from or over the electro-optical layer 140. Exemplary embodiments illustrate the effect of having a thin crystalline semiconductor layer on light confinement. Referring to Figures 6 A - 6D, in an exemplary embodiment, ridge 150 has a height h\ of 0.5 μm and a width W1 of about 1.2 μm. Ridge 150 is made of BT and is disposed over electro-optical layer 140 that is also formed from BT and has a thickness t3 of about 0.5 μm. First buffer layer 180 is formed from MgO and has a thickness of about 0.3 μm. The electro-optical layer and first buffer layer 180 are formed over an SOI wafer 100. The SOI wafer 100 includes Si substrate 110, insulator layer 120 formed of SiO2 and having a thickness t! of 3 μm, and crystalline semiconductor layer 230 formed of Si and having a thickness t2 thicker than about 100 nm, e.g., about 0.2 μm, i.e., 200 nm. This crystalline semiconductor layer 230 is thicker than the crystalline semiconductor layer desirably employed in connection with the invention. As illustrated in Figure 6B, the mode shape for this waveguide fabricated with a thick silicon layer is indicative of great propagation losses, e.g., 25dB/cm at a wavelength of 1.55 μm, due to the spreading of the non-confined components of the optical mode into the thick Si crystalline semiconductor layer. Referring to Figure 6C, an exemplary waveguide formed in accordance with the invention has the same materials, thicknesses, and dimensions as the waveguide of Figure 6 A. Instead of the thick Si crystalline semiconductor layer, however, the exemplary waveguide formed in accordance with the invention has a thin Si crystalline semiconductor layer 130 with a thickness t2 that is less than 100 nm, e.g., about 0.05 μm, i.e., 50 nm. Referring to Figure 6D, light propagated through the waveguide is confined to the ridge 150 and a portion of the electro- optical layer 140. The thin Si crystalline semiconductor layer 130 does not support the propagation of non-confined light components, so that the mode propagation is substantially loss free. > The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to e considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. What is claimed is: