Title:
FABRICATION METHOD FOR SEMICONDUCTOR ULTRA-THIN STACKED STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2022/241662
Kind Code:
A1
Abstract:
A fabrication method for a semiconductor ultra-thin stacked structure, comprising: forming a stop layer structure in a semiconductor substrate by using ion implantation, and then providing an electrical element and an interconnect layer on an active surface of the semiconductor substrate so as to form a semiconductor wafer; joining together interconnect layers of two semiconductor wafers which are opposite and up and down relative to each other; removing a part of the semiconductor substrate of an upper semiconductor wafer and the stop layer structure from the back surface of the upper semiconductor wafer by a back surface grinding and thinning process, so that the upper semiconductor wafer forms a thinned semiconductor wafer; then performing bonding, back surface grinding and thinning processes of the other semiconductor wafer one by one on the thinned semiconductor wafer; then stacking the other thinned semiconductor wafer one by one on top; and finally, performing back surface grinding and thinning processes on the bottommost semiconductor wafer. The present fabrication method can stack a plurality of layers of thinned semiconductor wafers to meet high integration requirements.
Inventors:
CHIU TZU-WEI (CN)
Application Number:
PCT/CN2021/094503
Publication Date:
November 24, 2022
Filing Date:
May 19, 2021
Export Citation:
Assignee:
CHIU TZU WEI (CN)
International Classes:
H01L21/304; H01L23/12
Foreign References:
| CN101971328A | 2011-02-09 | |||
| JP2011138825A | 2011-07-14 | |||
| CN101853804A | 2010-10-06 | |||
| CN101320684A | 2008-12-10 |
Attorney, Agent or Firm:
JIAQUAN IP LAW (CN)
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