Title:
FABRICATION METHODS FOR LOW TEMPERATURE POLYSILICON, THIN FILM TRANSISTOR AND ARRAY SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2019/174195
Kind Code:
A1
Abstract:
The present invention relates to fabrication methods for low temperature polysilicon, a thin film transistor and an array substrate. The fabrication method for low temperature polysilicon comprises: providing a substrate, and forming a buffer layer on the substrate; forming an amorphous silicon layer on the buffer layer; performing an excimer laser annealing treatment on the amorphous silicon layer under the shielding of a semipermeable membrane mask to convert the amorphous silicon layer into a polysilicon layer, wherein the semipermeable membrane mask comprises a light transmitting substrate and a patterned semipermeable membrane disposed on a surface of the substrate. Also provided in the present invention are corresponding fabrication methods for a low temperature polysilicon thin film transistor and an array substrate. The fabrication methods for low temperature polysilicon, a thin film transistor and an array substrate of the present invention may improve the effect of polycrystalline silicon crystallization, thus improving the electrical performance of the polysilicon thin film transistor while improving the dry etching efficiency of the polysilicon layer and releasing the production capacity for fabricating the polysilicon.
Inventors:
XU XIANGYANG (CN)
Application Number:
PCT/CN2018/103164
Publication Date:
September 19, 2019
Filing Date:
August 30, 2018
Export Citation:
Assignee:
SHENZHEN CHINA STAR OPTOELECT (CN)
International Classes:
H01L21/02; H01L21/336; H01L27/12
Foreign References:
| CN106876480A | 2017-06-20 | |||
| CN106847746A | 2017-06-13 | |||
| CN108346562A | 2018-07-31 | |||
| CN1501437A | 2004-06-02 |
Attorney, Agent or Firm:
COMIPS INTELLECTUAL PROPERTY OFFICE (CN)
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