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Title:
FAILURE TOLERANT POWER ELECTRONIC CONVERTER SYSTEM
Document Type and Number:
WIPO Patent Application WO/2011/064277
Kind Code:
A2
Abstract:
A drive device and method for controlling a rotating machine. The drive device includes plural inverters configured to transform first alternate currents (AC); DC links connected to the plural inverters and configured to transmit the DC currents; plural converters connected to the DC links and configured to transform the DC currents received from the DC links to second AC currents, where the plural converters are connected in series; semiconductor switches configured to switch the second AC currents and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the plural converters; and a controller connected to gates of the semiconductor switches and configured to switch on and off, when a semiconductor switch in a converter is in a failed mode, remaining semiconductor switches in the converter such that an AC current passes the converter.

Inventors:
RITTER ALLEN (US)
ZHANG RICHARD (US)
WANG CHANGYONG (CN)
SCHROEDER STEFAN (DE)
ZHANG FAN (CN)
BACCANI ROBERTO (IT)
Application Number:
PCT/EP2010/068164
Publication Date:
June 03, 2011
Filing Date:
November 24, 2010
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NUOVO PIGNONE SPA (IT)
RITTER ALLEN (US)
ZHANG RICHARD (US)
WANG CHANGYONG (CN)
SCHROEDER STEFAN (DE)
ZHANG FAN (CN)
BACCANI ROBERTO (IT)
International Classes:
H02M5/458
Foreign References:
US5986909A1999-11-16
US20090073622A12009-03-19
US20080174182A12008-07-24
US6377478B12002-04-23
Other References:
None
Attorney, Agent or Firm:
ILLINGWORTH-LAW, William (Global Patent Operation - Europe15 John Adam Street, London WC2N 6LU, GB)
Download PDF:
Claims:
CLAIMS:

1. A drive device for controlling a rotating machine, the drive device comprising:

plural inverters configured to transform first alternate currents (AC) having a first frequency to direct currents (DC);

DC links connected to the plural inverters and configured to transmit the DC currents;

plural converters connected to the DC links and configured to transform the DC currents received from the DC links to second AC currents having a second frequency, wherein the plural converters are connected in series;

semiconductor switches configured to switch the second AC currents and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the plural converters to generate the second AC currents; and

a controller connected to gates of the semiconductor switches and configured to switch, when a semiconductor switch in a converter is in a failed mode, remaining semiconductor switches in the converter such that an AC current passes the converter.

2. The drive of Claim 1 , wherein the plural converters include only two converters and the plural inverters include only two inverters, and the two converters and the two inverters are connected in series with the rotating machine.

3. The drive of Claim 2, wherein one inverter and one converter form a first cell and the other inverter and the other converter form a second cell and the first cell, the rotating machine and the second cell are connected in series in this order.

4. The drive of Claim 3 , wherein each winding of the rotating machine is connected between the first and second cells.

5. The drive of Claim 3, further comprising:

a first transformer connected to the first cell; and

a second transformer connected to the second cell.

6. The drive of any preceding Claim, wherein the semiconductor switches are press-pack housing devices including one of Integrated Gate Commutated Thyristor (IGCT), Press-Pack Insulated Gate Bipolar Transistors (IGBT) or Injection Enhanced Gate Transistor (IEGT).

7. The drive of any preceding Claim, further comprising:

plural cells, each cell including one or more corresponding inverters of the plural inverters, a corresponding converter of the plural converters, and a set of semiconductor switches of the plural semiconductor devices.

8. The drive of Claim 7, wherein the controller is configured, when one or more cells fails due to failed semiconductor switches, to gate the remaining semiconductor switches to provide a short circuit on an output of the one or more cells.

9. A high speed drive device for controlling a motor, the drive device comprising:

two cells connected in series with the motor, each cell including,

an inverter configured to transform a first alternate current (AC) having a first frequency to direct currents (DC),

DC links connected to the inverter and configured to transmit the DC currents, and

a converter connected to the DC links and confi gured to transform the DC currents received from the DC links to a second AC current having a second frequency, the converter including semiconductor switches configured to switch the second AC current and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the converter to generate the second AC current;

a fault detection mechanism configured to detect a failed mode of a semiconductor switch; and

a controller connected to the fault detection mechanism and to the two cells and configured to switch, when a semiconductor switch in the converter i s in a failed mode, remaining semiconductor switches, based on a signal from the fault detection mechanism, such that an AC current passes through the converter.

10. A high speed drive device for controlling a motor, the dri ve device comprising:

plural inverters configured to trans form first alternate currents (AC) having a first frequency to direct currents (DC) ;

plural DC links connected to the plural inverters and configured to transmit the DC currents ;

plural groups of cel ls, each group including cel ls connected in series with a phase of the motor, each cell including,

a converter connected to corresponding DC links and configured to transform corresponding DC currents received from the corresponding DC links to a second AC current having a second frequency, the converter including semiconductor switches configured to switch the second AC current and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the converter to generate the second AC current;

a fault detection mechanism configured to detect a failed mode of a semiconductor switch; and

a controller connected to the fault detection mechanism and to the plural groups of cells and configured to switch, when a semiconductor switch in a corresponding converter is in a failed mode, remaining semiconductor switches in the corresponding converter based on a signal from the fault detection mechanism, such that an AC current passes through the corresponding converter.

Description:
FAILURE TOLERANT POWER ELECTRONIC CONVERTER SYSTEM

BACKGROUND

TECHNICAL FIELD

Embodiments of the subject matter disclosed herein generally relate to methods and systems and, more particularly, to mechanisms and techniques for using converters for generating voltage that may withstand various component failures.

DISCUSSION OF THE BACKGROUND

The oil and gas industry is using large compressors and other machines for compressing and transporting fluids that may include, gas, oil , etc. To control the rotation of the compressors and other machines, a drive is attached between the electric power utility and the machine for regulating the voltage, frequency or other parameter of the electric power supplied to the machine. Converters are part of the dri ve and they are particularly sensitive to unexpected failures of their components.

The power range required for these applications are typically higher than a mature and si mple confi guration where the desirable reliabi lity can be mimicked. Present electronic switches used in switch-mode-voltage-sourced converters are too small to readily provide adequate power in simple converters . The traditional drives use a multiplicity of converters to fill this power class. When multiple converters are selected failure rates increase. To restore limited dri ving capabili ty when components of the drive failed require expensive and problematic circuit isolators to be used in a parallelism of individual converters. Figure 1 shows such a traditional drive 10 that includes a connection 12 to the electrical grid (not shown), an AC (alternate current) transformer 14, plural legs 16 that connect to the transformer 14 and are configured to transform input AC current from transformer 14 into DC (direct current) current and back to AC current but having a desired frequency, and a machine 18, that may be connected to a compressor. One or more legs 16 may be used to change the standard frequency f of the input current from 50 or 60 Hz to a desired frequency that is required by the motor 18. The desired frequency may be in the range of 100 to 600 Hz.

According to the configuration shown in Figure 1 , one leg 16 may include inductors 20, circuit isolators 22, and a cell 24. Cell 24 receives from transformer 14 an AC current (three phase) as input and provides a different AC current (three phase) as output. One possible configuration for cell 24 is shown in Figure 2. Cell 24 may include a rectifier 30 that, for example, may transform the AC current to DC current by using plural diodes 28. The DC current is provided to the converter 32, where the DC current is transformed back to AC current but having the desired frequency. The traditional converters 32 may use a combination of switches 34 and diodes 36 for achieving the above-noted function.

For obtaining a desired voltage to be applied to the machine 18, cells 24 may be connected in a cascaded-cell topology, as shown for example in Figure 3. Fi gure 3 shows that rectifiers 30 are connected to transformer 14 and the inverters 30 provide DC currents to converters 32, which are connected in series for each phase of the motor power supply. This cascaded-cell topology offers a high modularity and can hence potentially be used with a large number of cells and thus, it can provide a high drive power. However, the component count of the system is increased, which increases the likelihood of failures and hence reduces reliability and availability of such systems. As a consequence, the reliability requirements in critical processes, as common, e.g., in oil and gas industry, cannot be met by such systems.

Use of a parallel implementation of cells is possible and utilizes individual harmonic contribution to reduce a net distortion by slightly altering the voltage waveform of each converter. Since the converter voltages are different and the impedance of voitage-sourced converters are inherently low, additional circuit elements are added. Such additional elements may include inductors. However, this arrangement is also prone to failure.

In order to minimize a down time of the drive due to failures of the converter components, it is possible to bypass the failed cell with an external by-pass switch. One such approach (illustrated in Figure 4) uses external by-pass switches B l to B3 for switching off a failed cell of the plural cells A l to A3. In this way, a current path from a neutral N to a phase A of the machine 18 may either traverses each cell Al to A3, or any number of the cells depending on the positions of the switches B l to B3. The positions of the switches B l to B3 illustrated in Figure 4 are used when no cell is to be bypassed.

Thus, when a failure in a cell is detected, the corresponding eel] is by-passed by a dedicated switch. The remaining cells will keep the converter operational when the control is adjusted accordingly. However, this configurati on does not only need additi onal bypass switches (B l to B3 for three cells), but also a failure detection logic that activates the switches. If one of both fails, the redundancy is lost. The bypass switch also does not interrupt the short circuit current within the cell. This may cause the failed semiconductor switches to mechanically rupture and cause secondary damage in the dri ve. To avoid this effect, additional fuses have to be added to the system, further complicating the confi guration of the system.

In one example, a high-speed motor is defined as being at least 6000 rpm and is typically on the order of 25 ,000 rpm for lower power machines and 7000 rpm for higher power machines. In another example, high frequency is defined as being at least 100 Hz or more, specifically on the order of 400 Hz or 600 Hz or one kHz or more with the selected frequency depending upon machine size and pole number. High power machines are typically defined as being in the megawatt range. The drivers discussed above are intended to control a motor having the high frequency and high power noted in this paragraph . For this reason, a low speed and low power driver, which are known in the art, are not suitable for such a motor given the fact that the high power requires semiconductor devices that may withstand those powers.

Accordingl y, it would be desirable to provide systems and methods that avoid the afore-described problems and drawbacks.

SUMMARY

According to one exempl ary embodi ment, there is a drive device for controll ing a rotating machine. The drive incl udes plural inverters configured to transform first alternate currents (AC) having a first frequency to direct currents (DC); DC links connected to the plural inverters and configured to transmit the DC currents; plural converters connected to the DC links and configured to transform the DC currents received from the DC links to second AC currents having a second frequency, wherein the plural converters are connected in series; semiconductor switches configured to switch the second AC currents and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the plural converters to generate the second AC currents; and a controller connected to gates of the semiconductor switches and configured to switch, when a semiconductor switch in a converter is in a failed mode, remaining semiconductor switches in the converter such that an AC current passes the converter.

According to another exemplary embodiment, there is a high speed drive device for controlling a motor. The drive includes two cells connected in series with the motor, each cell including, an inverter configured to transform a first alternate current (AC) having a first frequency to direct currents (DC), DC links connected to the inverter and configured to transmit the DC currents, and a converter connected to the DC links and configured to transform the DC currents received from the DC links to a second AC current having a second frequency, the converter including semiconductor switches configured to switch the second AC current and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the converter to generate the second AC current. The drive also includes a fault detection mechanism configured to detect a failed mode of a semiconductor switch; and a controller connected to the fault detection mechanism and to the two cells and configured to switch, when a semiconductor switch in the converter is in a failed mode, remaining semiconductor switches, based on a signal from the fault detection mechanism, such that an AC current passes through the converter.

According to still another exemplary embodiment, there is a high speed drive device for controlling a motor. The drive includes plural inverters configured to transform first alternate currents (AC) having a first frequency to direct currents (DC); plural DC links connected to the plural inverters and configured to transmit the DC currents; plural groups of cells, each group including cells connected in series with a phase of the motor, each cell including, a converter connected to corresponding DC links and configured to transform corresponding DC currents received from the corresponding DC links to a second AC current having a second frequency, the converter including semiconductor switches configured to switch the second AC current and to sustain a short circuit during a failed mode, the semiconductor switches being provided inside the converter to generate the second AC current; a fault detection mechanism configured to detect a failed mode of a semiconductor switch ; and a controller connected to the fault detection mechanism and to the plural groups of cells and configured to switch, when a semiconductor switch in a corresponding converter is in a failed mode, remaining semiconductor switches in the corresponding converter based on a signal from the fault detection mechanism, such that an AC current passes through the corresponding converter. According to still another exemplary embodiment, there is a computer readable medium including computer executable instructions, wherein the instructions, when executed, implement a method for gating plural semiconductor switches in a drive device for controlling a motor. The method includes a step of detecting a mode of each of the plural semiconductor switches; and a step of gating, when a semiconductor switch is detected as failed, remaining semiconductor switches in a converter such that an alternative current passes through the converter without using an external mechanical by-pass device.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these embodiments. In the drawings:

Figure 1 is a schematic diagram of a conventional drive;

Figure 2 is a schematic diagram of a power cell that is part of the drive of Figure 1 ;

Figure 3 is a schematic diagram of another conventional dri ve;

Figure 4 is a schematic diagram of plural cells connected to each other with external switches;

Figure 5 is a schematic diagram of a drive according to an exemplary embodiment;

Figure 6 is a schematic diagram of a cell according to an exemplary embodiment; Figure 7 is a schematic diagram of plural cells arranged in a ring arrangement;

Figure 8 is a schematic diagram of an H-bridge cell according to an exemplary embodiment;

Figure 9 is the H-bridge cell of Figure 8 with a path of a current passing through the bridge when one element has failed according to an exemplary embodiment;

Figure 10 is a flow chart illustrating steps performed for controlling a converter according to an exemplary embodiment; and

Figure 1 1 is a schematic diagram of a controller according to an exemplary embodiment.

DETAILED DESCRIPTION

The following description of the exemplary embodiments refers to the accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims. The following embodiments are discussed, for simplicity, with regard to the terminology and structure of series connected converters. However, the embodiments to be discussed next are not limited to this arrangement, but may be applied to other configurations, as for example, ring arrangement and stacked arrangement.

Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

According to an exemplary embodiment, high power, high power density converters may be achieved with semiconductor switches that are configured to fail to a short circuit state. Such semiconductor switches may, for example, be provided in a press-pack housing. Examples of such press-pack devices are Integrated Gate Commutated Thyristor (IGCT), Press-Pack Insulated Gate Bipolar Transistors (IGBT) or Injection Enhanced Gate Transistor (IEGT). Press-Pack devices have a defined and guaranteed failure mode that is providing a short-circuit. Hence, the current path on the output of a failed cell can be maintained by properly gating the remaining healthy switches within the cell, as will be discussed later.

Known existing implementation of cascaded cell converters use semiconductor switches in plastic module housing. Such devices have an undefined behavior in case of failure, i.e., they can get open or short-circuited and can even mechanically rupture (explode). This uncertainty about the failed state of the switch makes difficult a reliable operation of the cell including the failed switch .

According to an exemplary embodiment, the low switching frequencies associated with high power densities and press-pack semiconductor devices may be combined with a multiplicity of converters to achieve a lower distortion for individual converters having different output voltages, without the complexity of combining reactors if the converters are arranged in series instead of parallel avoiding thus, the consequence of circulating currents increasing the dimension of the combining reactors.

Several possibilities for implementing series connected converters may be used. A push/pull arrangement and a ring arrangement can all benefit from using the maintained switch short circuit in combination with selective allowed states of non shorted switches to provide limited operation without expensive isolation equipment or circuit combiners due to the characteristic of shorted devices ability to continue to conduct current in the series path leaving the voltage adjustment necessary to compensate for the shorted device voltage error to the remaining operating switches.

Thus, according to an exemplary embodiment, a failure tolerant power electronic converter system may include series-connected H-bridge cells to produce single or multi-phase output voltages. By using press-pack power devices as switching devices, the continuity of the load current path can be maintained even when such a device fails, since it is guaranteed by design that such devices provide a short-circuit in case of device failures. By this measure, the converter system can be kept operational with failed devices without the need for additional fast-acting by-bass switches. Thus, the overall system availabi lity can be improved. However, the failure of a switch has to be recognized and the remaining switches need to be gated accordingly, as will be discussed later. One exemplary embodiment of series connected converters with press-pack power devices is shown in Figure 5. It is noted that this is a particular arrangement intended not to limit every embodiment to be discussed in this application, neither obvious modifications of the discussed embodiments. Figure 5 shows a motor 50 connected in series with two cells 52a and 52b via three-phase connections 54. Throughout the specification, the connections between the motor and the cells may be three-phase or one-phase, as would be recognized by those skilled in the art. Similar three phase connections 54 are used to connect each cell to a corresponding transformer 56a or 56b. In one application, a single transformer may be used instead of transformers 56a and 56b. Transformers 56a and 56b shown in Figure 5 are configured, for example, to change a phase of the current from an AC input to AC output. Transformers 56a and 56b may be connected to contactor 58. Contactors 58 are connected to a source of AC power 59. This source of AC power may be the electric grid and may have a frequency of 50 or 60 Hz. Cells 52a and 52b may be configured, as discussed later, to change a first frequency (50 or 60 Hz) of the AC current to a second frequency, for example, 400 Hz or another desired value.

By connecting cells 52a and 52b in series in a push/pull arrangement, the configuration shown in Figure 5 advantageously provides a sum of the voltages of the cells to drive a current to the motor, which is different from the configuration shown in Figure 1 , in which a voltage difference between legs 16 drives the current to the motor.

According to an exemplary embodiment, a configuration of the cells 52a and 52b is shown in Figure 6. For example, cell 52a may include an inverter 60, DC links 62 and a converter 64. Inverter 60 may include six diodes 66 configured to transform the AC currents from transformer 56a to DC currents. Although connection 54 is represented as a single line, one skilled in the art would understand that in this exemplary embodiment a three-phase current is provided by transformer 56a and connection 54 represents three distinct lines, one for each phase. Inverter 60 has three inputs and two outputs, 62a and 62b, which are the DC links. The DC currents from DC links 62a and 62b are provided to converter 64. Converter 64 includes three legs 64a to 64c, each providing an AC current to outputs 66a to 66c. Thus, an output of cell 52a is a three-phase AC current having the second frequency, different from the first frequency provided by transformer 56a. Converter 64 is a two-level converter as only two DC links are connected to the converter. However, a three-level converter or a multi-level converter may be used.

Each leg 64a, 64b and 64c may include a pair of semiconductor devices 68 and corresponding diodes 70. According to an exemplary embodiment, semiconductor devices 68 are configured to switch on and off the DC currents received from the DC links 62 to provide the second AC currents. The semiconductor devices are configured to sustain a short-circuit during a failure mode, i .e., if the semiconductor devices fail, the semiconductor devices remain close so that electric current passes through the semiconductor devices even if the devices have failed. Such semiconductor devices that fail in a short circuit mode are called press-pack housing devices and examples of press-pack housing devices are IGCT, IGBT or IEGT already di scussed. Figure 6 shows that the semiconductor devices 68 have a gate 72 configured to receive a signal from a controller 80. The applied signal from controller 80 gates the semiconductor device 68, determining the semiconductor device 68 to open or close, i .e. , to act as a switch. Controller 80 may be configured to determine a failure of each of the semiconductor devices 68 and to consequently (i) either switch the remaining semiconductor devices 68 inside the cell so that the entire cell acts as a conductor, i.e., current from transformer 56a passes the affected cell without being modified, (ii) or switch the remaining semiconductor devices 68 inside the cell so that the cell is still active, i.e., increases a voltage across the failed cell. A structure of controller 80 is discussed later.

In one application, the arrangement shown in Figure 6 includes no more than two cells 52a and 52b, two transformers 56a and 56b, and the motor 50. Although not shown, one skilled in the art would recognize that motor 50 may include three winding circuits, each having an input and an output. Thus, cells 52a and 52b may be connected to motor 50 such that a first output from cell 52a is connected to an input of the first winding of the motor and a first output from cell 52b is connected to an output of the first winding of the motor, and so on for the remaining windings of the motor.

However, according to another exemplary embodiment, more than two cells may be used to drive the motor. Figure 7 illustrates an exemplary embodiment in which the converters are connected in series for each phase. This arrangement is called a ring arrangement and it is defined by the fact that a transformer 92 provide three phases AC currents to multiple cells 94a to 96c and the cells are arranged such that groups of cells provide currents for each phase of a motor 100. More specifically, three cells 94a, 94b, and 94c are fed from a separate secondary of the transformer 92 and each cell is responsible for producing the AC current for a single phase of the motor 100. More cells may be added to this arrangement, for example, cells 96a, 96b, and 96c, similarly arranged with cells 94a - 94c. In one exemplary embodiment, further cells may be added to each phase, between, for example, cells 94a and 96a. The cells may also be connected in a stack arrangement, which includes three phase converters connected in a series arrangement of individual transformer winding.

According to an exemplary embodiment, a cell as shown in Figures 5 and 7 may have the structure shown in Figure 8. Figure 8 shows three DC links DCP, DCN, and DCM, which provide DC voltages having different polarities connected to an H-bridge cell 1 10. Because 3 DC currents are provided to the H-bridge cell, this arrangement is called a three-level H-bridge cell. As would be recognized by those skilled in the art, a two-level or multilevel arrangement may also be used to implement the novel features. The DC links are connected to the H-bridge cell 1 10 via capacitors 1 12. The H-bridge cell 1 10 includes two ports HA and HB. One port may be connected to another H- bridge cell or to a neutral whi le the other port may be connected to still another H-bridge cell or to the motor.

Plural diodes D 1 A to D6A are arranged on one side of the H-bridge cell as shown in the fi gure with switches S I A to S4A mirroring the arrangement of diodes D 1 A to D4A. A similar arrangement is used for the other side of the H-bridge cell . Switches S 1A to S4A and S IB to S4B may be any of the press- pack devices discussed above, i.e. , Integrated Gate Commutated Thyristor (IGCT), Press-Pack Insulated Gate Bipolar Transistors (IGBT) or Injection Enhanced Gate Transistor (IEGT). A gate of each switch is connected to a controller 120 for controlling a mode of the switch, for example, open or closed. For simplicity, Figure 8 shows a gate of only a switch being connected to the controller 120. However, all gates may be connected to the controller 120.

A fault detection mechanism 130 may be connected to the controller 120, directly to the switches, or may be part of the controller 120 and is configured to detect when any of the switches of the H-bridge cell fails. Computer software instructions may be stored in a memory of the controller 120 and/or the fault detection mechanism 130 for instructing each switch when to close or to open and at what time and/or in which sequence. The memory may also store a configuration of the switches and diodes and the computer software instructions may control the H-bridge cell 1 10 for generating an AC current. Even in the event that one switch fails, the controller and/or fault detection mechanism may be configured to instruct the remaining switches to either provide a short circuit between ports HA and HB or to actively produce an output voltage between ports HA and HB . This capability of the H-bridge cell 1 10 and the controller 120 and/or fault detection mechanism 130 is discussed now with regard to Figure 9.

In an exemplary embodiment illustrated in Figure 9, assume that switch S 1A has failed, i .e. , it is not functional and cannot be controlled by controller 120. Because the switch is a press-pack device, the switch fails to a short-circuit mode. After detecting the failure of switch S I A, controller 120 may control the remaining switches for ensuring that current flows through H-bridge cell 1 10, between ports HA and HB as discussed next.

A current entering port HB proceeds along diodes D2B and D I B as switches S IB to S4B are gated as shown in the figure by corresponding arrows, i.e. , the switches are gated by controller 120 to conduct current only in the direction shown by the arrows. After passing diode DIB, the current passes short- circuited switch S I A and gated switch S2A to arrive at port HA. Switches S3A and S4A are gated as also shown in the figure to prevent DC current from DC link DCP to reach DC link DCM. A reverse flow of the current is also possible, i.e. , from HA to HB by following a path defined by D2A, S 1 A, S IB, and S2B .

Thus, the appropriate control of the switches by the controller 120 ensures that the H-bridge cell 1 10 passes a current even if a switch has failed. The controller may control the switches to pass a current when more than one switch fails. This mode of the cell passing the current without modifying the current is called a short circuit mode of the cell . According to an exemplary embodiment, an active mode is present when the cell may be configured to provide an active output voltage, i.e., to increase a voltage across the cell even when one or more switches have failed. The arrangement shown in Figures 8 and 9 includes 3-level Neutral Point Clamped (NPC) phase-legs as the neutral point i s clamped by DCN. The DC links may be provided by two inverters connected to each other. Because the controller 120 and/or the fault detection mechanism 130 may configure the cells to either work in a short circuit mode or in an active mode, no external mechanical by-pass is necessary, which is contrary to the device shown in Figure 4, which requires mechanical by-passes B l to B3 and corresponding logic for controlling the by-passes. Thus, one or more of the exemplary embodiments discussed above advantageously has a lower count of parts, which makes the device less prone to failure.

According to an exemplary embodiment, the controller 120 and/or the fault detecting mechanism 130 may be programmed to include computer executable instructions, wherein the instructions, when executed, implement a method for gating p!urai switches in a drive device for controlling a motor. The method includes a step 1000 of detecting a mode of each of the plural switches, and a step 1002 of gating, when a switch is detected as failed, remaining switches in a converter such that an alternative current passes the converter without using an external mechanical by-pass device.

The drive mechanism may include semiconductor switches provided in stacked H-bridges with diode rectifier front-ends, which is a combination of rectifiers converting AC current to DC current. In another embodiment, the drive mechanism may include semiconductor switches provided in stacked H- bridges with diode active front ends, which is a combination of silicon control rectifiers converting AC current to DC current.

For purposes of illustration and not of limitation, an example of a representative controller capable of carrying out operations in accordance with the exemplary embodi ments is i llustrated in Figure 1 1 . It should be recognized, however, that the principles of the present exemplary embodiments are equally applicable to other computing systems that include a processor and a memory.

The exemplary controller 1 100 may include a processing/control unit 1 102, such as a microprocessor, reduced instruction set computer (RISC), or other central processing module. The processing unit 1 102 need not be a single device, and may include one or more processors. For example, the processing unit 1102 may include a master processor and associated slave processors coupled to communicate with the master processor. In one exemplary embodiment, controller 1 100 may be implemented as a programmable logic device, e.g. , a field programmable gate array (FPGA), complex programmable logic device (CPLD), application specific integrated circuit (ASIC), etc.

The processing unit 1 102 may control the basic functions of the system as dictated by programs available in the storage/memory 1 104. Thus, the processing unit 1 102 may execute the functions described in Figure 10. More particularl y, the storage/memory 1 104 may include an operating system and program modules for carrying out functions and applications on the controller. For example, the program storage may include one or more of read-only memory (ROM), flash ROM, programmable and/or erasable ROM, random access memory (RAM), subscriber interface module (SIM), wireless interface module (WIM), smart card, or other removable memory device, etc. The program modules and associated features may also be transmitted to the controller 1 100 via data signals, such as being downloaded electronically via a network, such as the Internet. One of the programs that may be stored in the storage/memory 1104 is a specific program 1 106. As previously described, the specific program 1106 may interact with the switches to determine a mode of the switches and may gate other switches if one of the switches fails. The program 1 106 and associated features may be implemented in software and/or firmware operable by way of the processor 1 102. The program storage/memory 1 104 may also be used to store data 1 108, for example, the topology of a cell, or other data associated with the present exemplary embodiments. In one exemplary embodiment, the programs 1 106 and data 1 108 are stored in non-volatile electrically-erasable, programmable ROM (EEPROM), flash ROM, etc. so that the information is not lost upon power down of the controller 1 100.

The processor 1 102 may also be coupled to user interface 11 10 elements. The user interface 1 1 10 may include, for example, a display 1 1 12 such as a liquid crystal display, a keypad 1 1 14, speaker 1 1 16, and a microphone 1 1 18. These and other user interface components are coupled to the processor 1 102 as is known in the art. The keypad 1 1 14 may include alpha-numeric keys for performing a variety of functions, including dialing numbers and executing operations assigned to one or more keys. Alternatively, other user interface mechanisms may be employed, such as voice commands, switches, touch pad/screen, graphical user interface using a pointing device, trackball, joystick, or any other user interface mechanism.

Controller 1 100 may also include a digital signal processor (DSP) 1 120. The DSP 1 120 may perform a variety of functions, including analog-to-digital (A/D) conversion, digital -to-analog (D/A) conversion, speech coding/decoding, encryption/decryption, error detection and correction, bit stream translation, filtering, etc. The transceiver 1 122, generally coupled to an antenna 1 124, may transmit and receive the radio signals associated with a wireless device.

Controller 1 100 of Figure 1 1 is provided as a representative example of a computing environment in which the principles of the present exemplary embodiments may be applied. From the description provided herein, those skilled in the art will appreciate that the present invention is equally applicable in a variety of other currently known and future computing environments. For example, the specific application 1 106 and associated features, and data 1 108, may be stored in a variety of manners, may be operable on a variety of processing devices, and may be operable in mobile devices having additional, fewer, or different supporting circuitry and user interface mechanisms. It is noted that the principles of the present exemplary embodiments are equally applicable to non-mobile terminals, i.e., landline computing systems.

The disclosed exemplary embodiments provide drivers and a computer program product for controlling plural switches when one or more other switches have failed. It should be understood that this description is not intended to limit the invention. On the contrary, the exemplary embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the exemplary embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the clai med invention . However, one skilled in the art would understand that various embodiments may be practiced without such specific details.

As also will be appreciated by one skilled in the art, the exemplary embodiments may be embodied in a wireless device, a network, as a method or in a computer program product. Accordingly, the exemplary embodiments may take the form of an entirely hardware embodiment or an embodiment combining hardware and software aspects. Further, the exemplary embodiments may take the form of a computer program product stored on a computer-readable storage medium having computer-readable instructions embodied in the medium. Any suitable computer readable medium may be utilized including hard disks, CD-ROMs, digital versatile disc (DVD), optical storage devices, or magnetic storage devices such a floppy disk or magnetic tape. Other non-limiting examples of computer readable media include flash- type memories or other known memories.

Although the features and elements of the present exemplary embodiments are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the embodiments or in various combinations with or without other features and elements disclosed herein. The methods or flow charts provided in the present application may be implemented in a computer program, software, or firmware tangibly embodied in a computer-readable storage medium for execution by a specifically programmed computer or processor.

This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other example are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements within the literal languages of the claims.