Title:
FALL IMPACT MITIGATING DEVICE FOR CHIP COMPONENTS, AND WIRE JIGS
Document Type and Number:
WIPO Patent Application WO/2015/098440
Kind Code:
A1
Abstract:
In the present invention, a fall impact mitigating device that mitigates the impact of falling chip components (C) is provided with a wire aggregate (10) formed by the accumulation of a plurality of wire jigs (11). The wire jigs (11) have a plurality of wires (13) that are disposed in parallel and set apart at intervals through which the chip components (C) can pass. The wire jigs (11) are obtained by processing a base material of a certain thickness to integrally form a pair of frames (12) and the plurality of wires (13) extending in parallel between the frames. When the chip components (C) are made to fall on top of the wire aggregate (10), the chip components (C) collide with the wires (13) of any of the wire jigs (11), and the collision with the wires causes the force of impact to be mitigated. The chip components easily pass through the spaces between wires, thereby reducing the frequency of collisions with subsequent chip components and preventing the chip components from cracking or chipping.
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Inventors:
AKIMOTO SHIGERU (JP)
Application Number:
PCT/JP2014/081966
Publication Date:
July 02, 2015
Filing Date:
December 03, 2014
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
B65G11/20
Domestic Patent References:
| WO2008041172A1 | 2008-04-10 |
Foreign References:
| JP2008081312A | 2008-04-10 | |||
| JPH02931Z1 | ||||
| JPS5288765U | 1977-07-02 | |||
| JPH08111467A | 1996-04-30 | |||
| JP2000264432A | 2000-09-26 | |||
| JPH07163950A | 1995-06-27 |
Attorney, Agent or Firm:
TSUTSUI HIDETAKA (JP)
Hidetaka Tsutsui (JP)
Hidetaka Tsutsui (JP)
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