FAST MEMORY CLEAR OF SYSTEM MEMORY

Title:

FAST MEMORY CLEAR OF SYSTEM MEMORY

Document Type and Number:

WIPO Patent Application WO/2024/066668

Kind Code:

A1

Abstract:

Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer

Inventors:

RAO RAJAT (IN)
MISHRA ASHUTOSH (US)
ABALI BULENT (US)
BUYUKTOSUNOGLU ALPER (US)

Application Number:

PCT/CN2023/107001

Publication Date:

April 04, 2024

Filing Date:

July 12, 2023

Export Citation:

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Assignee:

IBM (US)
IBM CHINA CO LTD (CN)

International Classes:

G06F12/0806

Foreign References:

CN101409675A	2009-04-15
CN112424757A	2021-02-26
CN113900967A	2022-01-07
US20210165580A1	2021-06-03
US20210073355A1	2021-03-11

Attorney, Agent or Firm:

CCPIT PATENT AND TRADEMARK LAW OFFICE (CN)

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