BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to electronic circuits, and more particularly relates to a latched comparator.

[0002] Latched comparators may be often of use in integrated circuit devices. Unfortunately, latched comparators may have difficulties in quickly performing comparisons, and quickly providing reliable outputs.

BRIEF SUMMARY OF THE INVENTION

[0003] Embodiments provide a fast latched comparator in accordance with aspects of the invention. Some embodiments utilize a reset pulse to short together outputs of the latched comparator. The reset pulse may allow faster settling of outputs of the latched comparator.

[0004] Some embodiments in accordance with aspects of the invention provide a high-speed comparator, comprising: a differential amplifier configured to receive differential input signals and generate a differential pair of intermediate signals; a latch configured to generate a pair of output signals at a respective pair of latching nodes based on the differential pair of intermediate signals; and a reset switch configured to control the pair of output signals based on a reset pulse so as to settle the pair of output signals, the reset switch configured to couple the pair of latching nodes.

[0005] Some embodiments in accordance with aspects of the invention provide a method for operating a high-speed comparator having a differential amplifier and a latch comprising: receiving a differential pair of input signals by the differential amplifier; generating a differential pair of intermediate signals by the differential amplifier using the differential pair of input signals; receiving, by the latch, the differential pair of intermediate signals; providing, by the latch, a pair of output signals at a respective pair of latching nodes based on the differential pair of intermediate signals; and activating a reset switch based on a reset pulse having a duty cycle, the reset switch coupling the pair of latching nodes.

[0006] These and other aspects of the invention are more fully comprehended upon review of this disclosure.

BRIEF DESCRIPTION OF THE FIGURES

[0007] FIG. 1 illustrates a block diagram of a latching comparator in accordance with aspects of the invention.

[0008] FIG. 2 illustrates a schematic diagram of a latching comparator in accordance with aspects of the invention.

[0009] FIG. 3 illustrates a graph depicting signals in a latching comparator including transient response data in accordance with aspects of the invention.

[0010] FIG. 4 is a semi-schematic, semi-block diagram of a circuitry for generating a reset signal for controlling a reset switch in accordance with aspects of the invention.

[0011] FIG. 5 is a graph depicting signals in a circuitry for generating a reset pulse in accordance with aspects of the invention.

DETAILED DESCRIPTION

[0012] FIG. 1 illustrates a block diagram of a latching comparator in accordance with aspects of the invention. The latching comparator 100 includes a differential amplifier 121 and a latch 131. A non-inverting input signal and an inverting input signal may be provided to the differential amplifier at input IN_P and input IN_N respectively. The differential amplifier generates a pair of intermediate differential signals 15a,b using the inverting and non-inverting input signals. The pair of intermediate differential signals may be provided to the latch 131. The latch generates an output signal at output (Out) based on the intermediate differential signals.

[0013] Generally, the differential amplifier 121 amplifies the non-inverting and inverting input signals of inputs IN_P and IN_N, respectively, whose common-mode component may vary over a wide range of voltages. More specifically, the differential amplifier receives the inverting and non-inverting input signals at gates of transistors and a difference between the input signals is operated on for outputting the pair of intermediate differential signals using a pre-amplification operation.

[0014] Latch 131 receives the pair of intermediate differential signals from the differential amplifier, and holds or latches the intermediate differential signals when the latch transitions from a track phase to a hold phase. In essence, the latch transitions from the track phase to the hold phase when a latch signal (CLK) transitions from logic low ("0") to logic high ("1")· The latch then produces an output signal based on the latched intermediate differential signals. In some embodiments, the latch may generate a pair of output signals at a respective pair of latching nodes based on the latched intermediate differential signals. As a result of this arrangement, there is a lower loss in rail to rail swing between the latch and the differential amplifier.

[0015] FIG. 2 illustrates a schematic diagram of a latching comparator in accordance with aspects of the invention. The latching comparator 200 includes pre-amplifying circuitry 210 and latch circuitry 230. In some embodiments, the pre-amplifying circuit 210 may implement circuitry of the differential amplifier 121 of FIG. 1, and the latch circuitry 230 may implement circuitry of the latch 131 of FIG. 1. [0016] As illustrated in FIG. 2, the pre-amplifying circuitry 210 and the latch circuitry 230 are formed using various pull-up and pull-down devices. The pull-up and pull down devices may be formed, for example, with metal-oxide-semiconductor field-effect transistor (MOSFET) transistors, with p-channel MOS transistors forming the pull-up devices and n-channel MOS transistors forming the pull-down devices.

[0017] The pre-amplifying circuitry 210 includes a first pull-up device 211a, a first pull-down device 21 lb, a second pull-up device 213a, and a second pull-down device 213b. The first pull- up and pull-down devices are connected in series. The second pull-up and pull-down devices are also connected in series. Sources of the first and second pull-up devices are connected to a high power source, and sources of the first and second pull-down devices are connected to a low power source. A gate of the first pull-down device is connected to an output node between drains of the first pull-up and pull-down devices. A gate of the second pull-down device is connected to an output node between drains of the second pull-up and pull-down devices.

[0018] The latch circuitry 230 includes a third pull-up device 231a and a third pull-down device 231b coupled in series, and a fourth pull-up device 233a and a fourth pull-down device 233 b also coupled in series. Sources of the third and fourth pull-up devices are connected to a latching switch 241, and sources of the third and fourth pull-down devices are connected to the lower voltage source, as with the first and second pull-down devices. The third and fourth pull- up devices are arranged in a cross-coupled configuration, a gate of each device being connected to a drain of the other device. The third and fourth pull-down devices are also arranged in a cross-coupled configuration with the first and second pull-down devices. As such, a gate of the third pull-down device is connected to the output node between the drains of the second pull-up and pull-down devices, and a gate of the fourth pull-down device is connected to the output node between the drains of the first pull-up and pull-down devices.

[0019] Referring to FIG. 2, the comparator 200 may further include a first output switch 261, a second output switch 263, and a reset switch 251. The first output switch has one end connected to the output node between the drains of the first pull-up and pull-down devices and another end connected to a first latching node at a drain of the third pull-down device. Similarly, the second output switch has one end connected to the output node between the drains of the second pull-up and pull-down devices and another end connected to a second latching node at a drain of the fourth pull-down device. The reset switch has one end connected to first latching node and another end connected to the second latching node. In many embodiments, the reset switch is provided a clock pulse.

[0020] In operation, the pre-amplifying circuitry 210 receives differential input signals (inp, inm) at gates of the first and second pull-up devices. The pre-amplifying circuitry amplifies the differential input signals and provides intermediate differential signals at the output node between the drains of the first pull-up and pull-down devices and the output node between the drains of the second pull-up and pull-down devices. In particular, input signal inp is connected to the gate of the first pull-up device and a complimentary input signal inm is connected to the gate of the second pull-up device. The intermediate differential signals are formed from the drains of the first pull-up and pull-down devices and the drains of the second pull-up and pull- down devices.

[0021] The intermediate differential signals are provided to the gates of the third and fourth pull-down devices of the latch 230. As with the latch 131 of FIG. 1 , the latch 230 holds or latches the intermediate differential signals when the latch 230 transitions from a track phase to a hold phase. In various embodiments, transitioning from the track phase to the hold phase occurs when the latching switch 241 transitions to a closed state from an open state. In many embodiments, the latching switch 241 is driven by a clock signal. The latch 230 then produces output signals (Lxn, Lxp) at the first and second latching nodes respectively.

[0022] Moreover, the reset switch 251 may be utilized to balance or settle the output signals (Lxn, Lxp) so that bias current is divided evenly between the first and second latching nodes. In some embodiments, this is accomplished by providing the reset switch a pulse. For example, when the reset switch is active or ON, a resistance is provided between the first and second latching nodes. This tends to bring the output signals (Lxn, Lxp) fast to settle. Similarly, the first output switch may be utilized to stabilize output signals at the output node between the first pull-up and pull-down devices and the first latching node, and the second output switch may also be utilized to stabilize output signals at the output node between the second pull-up and pulldown devices and the second latching node. In various embodiments, the reset switch 251 is driven by a reset signal with a duty cycle much smaller compared to that of the clock signal.

[0023] FIG. 3 illustrates a graph depicting signals in a latching comparator including transient response data in accordance with aspects of the invention. In some embodiments, FIG. 3 may depict simulated results of the latching comparator 200 of FIG. 2.

[0024] In graph 300 shown in FIG. 3, six signals are depicted with respect to time, including a clock signal (elk), a reset pulse (elkp), a high voltage signal (vdd), output signals (Lxp, Lxn), a low voltage signal (gnd), and differential input signals (Inp, inm). In general, graph 300 shows the effect on the output signals (Lxp, Lxn) when the reset pulse (elkp) is active or high. In more detail, during setup in a latching comparator (e.g., latching comparator 200 of FIG. 2), differential output signals generated from a differential amplifier often pull back output signals at output latching nodes of a latch. Moreover, the differential output signals often suffer disturbance which leads to kickback of differential input signals of the differential amplifier. Accordingly, by having a reset signal providing pulses for driving a reset switch, such disturbance can be mitigated and the output signals at the output latching nodes are stabilized.

[0025] Referring to FIG. 3, at every rising edge of the clock signal (elk), the reset pulse (elkp) transitions from low to high providing a pulse with a duty cycle equivalent or approximate to a setup time. The pulse, for example, drives a reset switch (e.g., the reset switch 251 of FIG. 2) to short output signals at output latching nodes of a latch (e.g., the latch 230 of FIG. 2) for a period of time in accordance with the pulse provided by the reset signal (elkp). Accordingly, as shown in FIG. 3, the output signals (Lxp, Lxn) remain steady and generally maintain a flat line without any indication of disturbance during the setup time.

[0026] FIG. 4 is a semi-schematic, semi-block diagram of a circuitry for generating a reset signal for controlling a reset switch in accordance with aspects of the invention. The reset switch, for example, may be the reset switch 251 of FIG. 2. In some embodiments, the reset signal may be the reset signal (elkp) of FIG. 3.

[0027] As illustrated in FIG. 4, the circuitry 400 includes an inverter 411, a variable delay block 421, and an AND gate 431. The inverter 41 1 generally receives an input signal, for example from a local clock, and outputs an inverted or negated signal. The variable delay block 421 receives the inverted signal from the inverter, and holds or delays the inverted signal for a reset time period tp. The variable delay block 421 then forwards the inverted signal to the AND gate 431. The AND gate receives the inverted signal along with the input signal and generates a reset signal based on states of the input and inverted signals. Such arrangement would allow the circuitry 400 to generate a reset signal with a duty cycle equal or approximate to the reset time period tp.

[0028] FIG. 5 is a graph depicting signals in a circuitry for generating a reset pulse in accordance with aspects of the invention. In some embodiments, FIG. 5 may depict simulated results of the circuitry 400 of FIG. 4.

[0029] In graph 500 shown in FIG. 5, two types of data are depicted including a clock signal (elk) and a reset pulse (elkp). As illustrated in FIG. 5, the reset signal (elkp) transitions from low ("0") to high ("1") at every rising edge of the clock signal (elk). The reset pulse (elkp) remains high for a period of time tp and subsequently, transitions from high to low. In various embodiments, the period of time tp is equivalent or approximate to the reset time period tp shown in FIG. 4.

[0030] Although the invention has been discussed with respect to various embodiments, it should be recognized that the invention comprises the novel and non-obvious claims supported by this disclosure.