BACKGROUND

[0001] A phase locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. The PLL generally includes an oscillator and a phase detector. The oscillator generates an output signal based on a reference signal. The phase detector compares a phase of the output signal with a phase of the reference signal and adjusts the oscillator so that the phase of the reference signal and the phase of the output signal match.

[0002] PLLs can be used to synchronize signals, track input frequencies and the like. PLLs can also be used for clock synchronization, demodulation, modulation, and frequency synthesis. PLLs are employed in communications, electronic applications, radio frequency (RF) communications and the like.

[0003] In operation, it is important that PLLs synchronize clock signals quickly and accurately. Two related characteristics of PLLs are setting time and phase shift accuracy. The PLL setting time is a period of time in which a PLL settles from a change of frequency from one frequency to another. The settling time is generally based on achieving a selected percentage of the new frequency. The phase shift or phase shift accuracy refers to how close the output signal is to the reference signal. The phase shift accuracy can be expressed in percentage.

[0004] The setting time and phase shift are important characteristics, but they can be at odds with each other. A superior settling time can result in inferior phase shift accuracy while a superior phase shift accuracy can result in an inferior settling time.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Fig. 1 is a diagram illustrating a control loop arrangement.

[0006] Fig. 2 is a diagram illustrating a digital phase locked loop (PLL) arrangement in accordance with an embodiment.

[0007] Fig. 3 is a diagram illustrating a digital phase locked loop (PLL) arrangement in accordance with an embodiment.

[0008] Fig. 4 is a diagram illustrating a transmitter (TX) arrangement in accordance with an embodiment. [0009] Fig. 5 is a diagram illustrating a receiver (RX) arrangement in accordance with an embodiment.

[0010] Fig. 6 is a diagram illustrating an exemplary user equipment or mobile communication device.

[0011] Fig. 7 is a flow diagram illustrating a method of operating a digital phase locked loop (PLL) to reduce settling times.

DETAILED DESCRIPTION

[0012] The systems and methods of this disclosure are described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.

[0013] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms "component," "system," "interface," and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor (e.g., a

microprocessor, a controller, or other processing device), a process running on a processor, a controller, an object, an executable, a program, a storage device, a computer, a tablet PC, an electronic circuit and/or a mobile phone with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other components can be described herein, in which the term "set" can be interpreted as "one or more."

[0014] Further, these components can execute from various computer readable storage media having various data structures stored thereon such as with a module, for example. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network, such as, the Internet, a local area network, a wide area network, or similar network with other systems via the signal). [0015] As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components.

[0016] Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term

"comprising".

[0017] As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules. In some embodiments, circuitry may include logic, at least partially operable in hardware.

[0018] A phase locked loops (PLL) is a control system that generates an output signal whose phase is related to the phase of an input or reference signal. The PLL generally includes an oscillator and a phase detector. The oscillator generates an output signal based on a reference signal. The phase detector compares a phase of the output signal with a phase of the reference signal and adjusts the oscillator so that the phase of the reference signal and the phase of the output signal match.

[0019] Two characteristics of a PLL are phase shift accuracy and setting time. Other characteristics of PLL include attenuation of oscillator phase noise and the like. The phase shift accuracy/stability is the accuracy or stability of a phase of an output signal with a phase of an input or reference signal. The settling time is a time period for changing from a first frequency to a new or next frequency. The setting time is typically based on a percentage of the new frequency or steady state of the new frequency.

[0020] PLLs used in radio frequency (RF) applications, including wireless

communication, typically require fast settling time. In some examples, settling times of 1 -2 micro seconds are required. However, PLLs used in RF applications can also require high phase shift accuracy, which means that a phase of the output signal closely matches a phase of the reference signal. The accuracy can be expressed as a percentage. The term phase shift can refer to an amount of shift in a phase of the output signal from a phase of the input signal.

[0021] The PLL includes a loop filter, in addition to the phase detector and the oscillator. The loop filter can include one or more integrators, which increase the order of the PLL and its behavior. The oscillator can be considered as having an integrator. The order or type of the PLL indicates the number of integrators.

[0022] A type I PLL has a proportional feedback loop without integration, thus the PLL has one integrator via the oscillator and an order of one. A type II PLL has a feedback loop with integration, thus there are two integrators via the oscillator and the loop filter. Thus, the type II PLL has two integrators and has an order of two.

[0023] The type I PLL has a relatively fast settling time when compared with type II PLLs, but typically lacks in phase stability. The type I PLL can suffer from a phase shift when the PLL settles to a changed frequency.

[0024] The type II PLL is generally used more than type I PLLs for RF applications because of its phase stability and attenuation of oscillator phase noise. The phase stability of the type I I PLL is typically superior to the phase stability of the type I PLL. However, the settling time can be significantly longer.

[0025] In one example, a type I PLL is compared with a type II PLL after a 4 Mega Hertz (MHz) frequency change or jump. The type I PLL settles to the changed frequency in about 1 micro second whereas the type II PLL takes about 9 micro seconds to settle. However, the type I PLL has phase instability, which includes an unwanted phase shift of over 550 degrees. This phase shift is generally unwanted and may not be allowed for a communications standard. The type II PLL omits a substantial phase shift and, thus has phase stability. However, the type I I PLL has a settling time that is long and may be too long for a communication standard.

[0026] Embodiments are disclosed that include a technique to reduce the settling time for both type I and type II PLLs while mitigating phase shift. Thus, relatively fast settling times and phase stability can be obtained as compared with other approaches.

[0027] The embodiments utilize correction paths that predict behavior of an outer or feedback path. The correction paths can improve the settling time and facilitate phase stability for PLLs.

[0028] Fig. 1 is a diagram illustrating a control loop arrangement 100. The arrangement 100 includes a correction component or paths that predict errors or variations in a feedback path and apply corrections before processing and remove corrections after processing.

[0029] The arrangement 100 includes a feedback path 106, a correction component 104, a loop component 102 and a forward combiner 108, an output combiner 1 14 and an output signal generator 1 16. The arrangement receives an input signal 1 10 and generates an output signal 1 12.

[0030] The control loop arrangement 1 00 is configured to adjust a control output based on an input signal. The input signal could indicate a change in frequency, phase, and/or another parameter. The amount of time it takes for the change to occur is referred to as a settling time.

[0031] The feedback path 106 is coupled to an output of the loop component 102 and generates an error signal. The error signal indicates a variation in one or more characteristics of the output signal from the input signal. In one example, the one or more characteristics include a phase error and the error signal is a phase error obtained by comparing a phase of the output signal with a phase of the input signal.

[0032] The correction component 104 predicts and/or detects variations in the one or more characteristics and generates a feedback correction and an output correction. The output correction is provided to a loop filter output via an output correction path. The feedback correction is provided to combiner 108 via a feedback correction path, which removes the forward correction from the error signal. The combiner 108 is also referred to as a feedback correction combiner. The error signal, without correction, is provided as an input to the loop component 102. Thus, the loop component 102 performs its functions without interference and/or adjustment from the forward correction.

[0033] The loop component 1 02 is configured to process the error signal and generate a loop output signal. The loop component 102 is configured to process the error signal by applying a proportional gain, scaling, filtering, integrating, and/or the like to the error signal to generate the loop output signal. The error signal received at its input has had the forward correction removed. Thus, the loop component 102 performs its processing without impact or substantial impact of the forward correction.

[0034] The output combiner 1 14 combines the loop output signal with the output correction to generate a combined loop signal. The output correction serves to apply the forward correction to the loop output signal.

[0035] The output signal generator 1 16 generates the output signal 1 12 based on the corrected loop signal from the output combiner 1 14. Possible variations or errors in the one or more characteristics are mitigated by the correction component 104.

However, operation of the loop component 1 02 is not impacted or altered by the correction as the combiner 1 08 removes the correction from the error signal, which is then provided to the loop component 102.

[0036] As a result, the setting time based on a change is reduced by using the correction component 104.

[0037] Fig. 2 is a diagram illustrating a digital phase locked loop (PLL) arrangement 200 in accordance with an embodiment. The arrangement 200 utilizes correction paths to improve settling times and phase stability for frequency changes or jumps.

[0038] The arrangement 200 receives an input/reference signal 1 10 and generates an output signal 1 1 2 substantially synchronized with the input signal 1 1 0 in terms of phase. A change in the input/reference signal 1 10 indicates a change or jump in frequency for the generated output signal 1 12. The change or jump can be to a same phase or a new or selected phase. The period of time it takes for the output signal 1 12 to settle to the new frequency and phase is referred to as the settling time. The settling time is based on a percentage of the changed frequency, such as +/- 5%, +/- 10%, and the like. The phase error, after setting, should be within a selected amount, such as 5- 10 degrees, of the new phase. The following description is based on a jump or change in frequency. [0039] The frequency jump can be as a result of switching from transmitting to receiving, switching transmission (TX) slots, and the like. In one example, settling times for a PLL are in the range of 2-3 micro-seconds for a frequency jump of 4 MHz.

[0040] The arrangement 200 includes a loop filter 202, a feedback combiner 208, an output/forward combiner 224, an oscillator 216, a time to digital converter (TDC) 226, a divider 228, a multiplier 222, a delay component 214, an output component 220, and a coefficient generator component 218.

[0041] The divider 228 generates a comparison signal based on the output signal 1 1 2. The divider 228 reduces the frequency of the output signal 1 12 by a division factor that includes an integer and a fractional part. It is also appreciated that the divider 228 can be omitted, wherein the division factor is set to one. In one example, the divider is a multi-modulus divider (MMD), which allows selection or programming of the division factor.

[0042] The TDC 226 can act as a phase frequency detector. The TDC 226 is configured to generate an error signal based on a phase difference between the comparison signal and the input signal 1 10. Generally, the TDC 226 measures a time interval between an edge of the comparison signal and a next edge of the input signal 1 1 0. The phase difference is proportional to the measured value.

[0043] The loop filter 202 is configured to generate a loop signal from a signal at its input. The loop filter 202 is configured to apply an adjustment or loop filter adjustment to the received signal to generate the loop signal. The loop filter adjustment can include and/or apply scaling/gain, proportional scaling/gain, integration and the like to generate the loop signal.

[0044] The oscillator 216 generates the output signal 1 12 based on the loop signal received at its input. The output signal 1 12 oscillates at a selected frequency. In one example, the oscillator 21 6 is a digitally controlled oscillator (DCO). In another example, the oscillator 21 6 includes a digital to time converter (DTC) and an RF oscillator. The DTC generates the output signal 1 12 based on the RF oscillator output and the filtered error signal. In another example, the oscillator 216 includes a digital to analog converter (DAC) in series with a voltage controlled oscillator (VCO). In another example, the oscillator 21 6 includes a digitally controlled oscillator (DCO) in series with a DTC.

[0045] The feedback combiner 208 subtracts or removes a correction of a feedback correction path 230 from the error signal provided by the TDC 226. The feedback combiner 208 is also referred to as a feedback correction combiner. The feedback correction path 230 converts a phase error of the corrected error signal to a frequency signal. The frequency signal represents a detected or measured phase error. The correction is already in the error signal from the TDC 226, so the feedback combiner 208 merely removes the correction so that the filter 202 receives an uncorrected error signal. A suitable delay based on a feedback path is applied to the correction so that it subtracts the correction applied by the combiner 224.

[0046] The output combiner 224 adds the correction from the filtered error signal to generate the corrected filtered error signal, which is provided to the oscillator 216. The correction is provided from a feed forward correction path 232.

[0047] The forward correction path 232 includes the output differentiation component 220, the coefficient generator 218 and the multiplier 222. Generally, the forward correction path 232 differentiates a measured phase error at the input of the filter 202, scales the measured phase error by a coefficient C, which is used to convert the phase signal to a frequency signal.

[0048] The component 220 differentiates, measures and/or identifies a phase error at the input of the loop filter 202. The multiplier 222 combines or multiples the measured phase error with the coefficient C, which is a scaling coefficient. The combiner 224 applies the correction to the filtered error signal to generate the corrected filter error signal, which is applied to an input of the oscillator 21 6.

[0049] The coefficient C is generated by the coefficient generator 21 8 and the amount of correction provided is based on the coefficient C. The coefficient generator 21 8 can include circuitry, memory, storage and the like that is used to generate the coefficient C. The memory or storage element can be used to look up previous values. In one example, the generator 218 includes a lookup table.

[0050] The scaling coefficient C is defined as:

[0051] C = -^ (1 )

[0052] Where K ₀ sc is the oscillator 216 gain, K _TD c is the TDC gain of the TDC 226 and fREF is the reference frequency of the input signal 1 10.

[0053] The coefficient generator 218 is configured to generate the coefficient C that facilitates or reduces settling time for the PLL arrangement 200. A variety of suitable values can be used for C and the used C is not required to be an optimum value. The above equation (1 ) provides an example of a suitable C that mitigates or eliminates phase shifts. However, other values of C are contemplated.

[0054] The feedback correction path 230 includes a delay element 214, which accounts for a loop delay in a feedback path from the output of the oscillator 21 6 to the combiner 208. The feedback path takes into account the loop delay and subtracts the correction from the error signal provided by the TDC 226. After the subtraction, the correction is no longer present in the error signal.

[0055] The delay element 214 can be configured to determine the loop delay, use a predetermined loop delay, receive a determined loop delay and the like. In one example, the loop delay is shown as N. The delay can include integer N and/or fractional values . The fractional values are delays of less than a clock cycle. The delay element is shown as a digital delay Z ^~N for illustrative purposes.

[0056] Because the feedback path 230 cancels the correction of the forward path 232, the phase correction is wideband and not limited by a loop bandwidth. So the bandwidth can be chosen for fast settling, whereas the correction takes care for any unwanted phase shifts.

[0057] It is noted that in a type I PLL configuration, the loop filter 202 is a

proportional gain. However, the loop filter 202 can also include an integrator, which results in the arrangement 200 being a type II PLL.

[0058] The PLL arrangement 200 can be used in applications, such as generating frequencies for transmission (TX), reception (RX) and the like. In one example, TX and RX frequencies range from 600 MHz to about 6 GHz. In another example, the PLL arrangement 200 is utilized to generate frequency for long term evolution (LTE) Band 1 , which is 1950 MHz for TX and 2140 MHz for RX. It is appreciated that other suitable frequencies can be generated.

[0059] In one example, the setting time is reduced compared with other approaches for frequencies of the output signal 1 12 in the range of about 600 MHz to about 6 GHz and for frequency jumps of the output signal 1 12 of about 1 -20 MHz. However, it is appreciated that other suitable output signal frequencies and frequency jumps can be used with the arrangement 200.

[0060] Fig. 3 is a diagram illustrating a digital phase locked loop (PLL) arrangement 300 in accordance with an embodiment. The arrangement 300 utilizes correction paths to improve settling times and phase stability for frequency changes or jumps. The PLL arrangement 300 is similar to the arrangement 200, described above, but includes some variations including use of a digitally controlled oscillator (DCO) and a multi-modulus divider (MMD). Additional description of components can be found above with reference to the arrangement 200, described above.

[0061] The arrangement 300 receives an input/reference signal 1 10 and generates an output signal 1 1 2 substantially synchronized with the input signal 1 1 0 in terms of phase. A change in the input/reference signal 1 10 indicates a change or jump in frequency for the generated output signal 1 12. The change or jump can be to a same phase or a new or selected phase. The period of time it takes for the output signal 1 12 to settle to the new frequency and phase is referred to as the settling time. The settling time is based on a percentage of the changed frequency, such as +/- 5%. The phase error, after setting, should be within a selected amount, such as 5-10 degrees, of the new phase. The following description is based on a jump or change in frequency.

[0062] The arrangement 300 includes a loop filter 202, a feedback combiner 208, an output/forward combiner 224, a digitally controlled oscillator (DCO) 216, a time to digital converter (TDC) 226, a multi-modulus divider (MMD) 228, a multiplier 222, a delay component 214, an output component 220, and a coefficient generator component 218.

[0063] The MMD 228 generates a comparison signal based on the output signal 1 12. The MMD 228 allows selection of a division factor by programming. It is appreciated that other suitable dividers can be utilized in alternate embodiments.

[0064] The TDC 226 is configured to generate an error signal based on a phase difference between the comparison signal and the input signal 1 10. Generally, the TDC 226 measures a time interval between an edge of the comparison signal and a next edge of the input signal 1 10. The phase difference is proportional to the measured value.

[0065] The loop filter 202 is configured to generate a loop signal from the error signal, provided by the combiner 208. Additionally, the loop filter 202 can apply proportional scaling, integration and the like to the filter input signal to generate the filtered corrected error signal. In one example, the loop filter 202 includes circuitry configured to provide a selected or adjustable gain. In another example, the loop filter 202 includes circuitry configured to provide a selected gain and additional circuitry in parallel configured to integrate the filter input signal. [0066] The DCO 21 6 generates the output signal 1 12 based on the loop signal received at its input. The output signal 1 12 oscillates at a selected frequency and phase based on the corrected loop signal.

[0067] The feedback combiner 208 subtracts a correction provided by a feedback correction path 230 from the error signal provided by the TDC 226. The feedback correction path 230 converts a phase error of the corrected error signal to a frequency signal. The frequency signal represents a detected or measured phase error. The correction is already in the error signal from the TDC 226, so the feedback combiner 208 merely removes the correction so that the loop filter 202 receives an uncorrected error signal.

[0068] The output combiner 224 adds the correction to the loop signal, which is then provided to the oscillator 216. The correction is provided from a feed forward correction path 232.

[0069] Fig. 4 is a diagram illustrating a transmitter (TX) arrangement 400 in accordance with an embodiment. The arrangement 400 utilizes a PLL having correction paths to facilitate settling time for frequency jumps. The arrangement 400 is provided for illustrative purposes. It is appreciated that additional and/or alternate components can be utilized. Further, the TX arrangement 400 is shown in operation as a TX, however it is appreciated that the arrangement can include operation as or with a receiver or transceiver.

[0070] The arrangement 400 includes a PLL 402, a digital frequency shifter 404, a digital to analog converter (DAC) 406 and a multiplier or combiner 408. The PLL 402 generates a local oscillator (LO) signal based on a received reference clock and a frequency shift. The LO signal is generated at a frequency based on the frequency shift and having a phase in line with a phase of the reference clock. If the frequency shift changes or jumps to a different value, the PLL is configured to adjust the frequency of the LO signal based on the frequency shift.

[0071] The digital frequency shifter receives a baseband signal and converts the baseband signal into a frequency shifted signal based on the frequency shift received. The baseband signal is typically at a relatively low frequency. The DAC 406 converts the frequency shifted signal into analog. The multiplier 408 multiplies the analog signal with the LO signal to generate a radio frequency (RF) signal. The RF signal can be transmitted using one or more antennas and the like. Other components, such as an amplifier and modulation component, can be included. The amplifier amplifies the RF signal prior to transmission. The modulation component can apply one or more modulation techniques to the baseband signal and/or the frequency shifted signal.

[0072] During operation, the frequency shift can vary or jump to different values. This jump is referred to as a frequency jump and can be due, for example, to a new channel being used. It is noted that the frequency jump can include a change in frequency and, optionally, a change in phase.

[0073] The PLL 402 is configured to perform or accommodate a frequency jump with relatively short settling time and phase stability. Thus, the generated LO can change frequencies relatively quickly. The PLL 402 includes correction paths to facilitate fast settling times. Examples of a suitable PLL are shown with regard to Fig. 2 and Fig. 3.

[0074] Fig. 5 is a diagram illustrating a receiver (RX) arrangement 500 in accordance with an embodiment. The arrangement 500 utilizes a PLL having correction paths to facilitate settling time for frequency jumps. The arrangement 500 is provided for illustrative purposes. It is appreciated that additional and/or alternate components can be utilized. Further, the RX arrangement 500 is shown in operation as a RX, however it is appreciated that the arrangement can include operation as or with a TX or

transceiver.

[0075] The arrangement 500 includes a PLL 502, a digital frequency shifter 504, an analog to digital converter (ADC) 506 and a multiplier or combiner 508. The PLL 502 generates a local oscillator (LO) signal based on a received reference clock and a frequency shift. The LO signal is generated at a frequency based on the frequency shift and having a phase in line with a phase of the reference clock. If the frequency shift changes or jumps to a different value, the PLL is configured to adjust the frequency of the LO signal based on the frequency shift.

[0076] The multiplier 508 receives an RF signal and uses the LO signal to obtain a received signal. The ADC 506 converts the received signal into a digital signal. The frequency shifter 504 shifts the digital signal from a received frequency to a baseband frequency and provides a baseband signal at the baseband frequency.

[0077] The RF signal can be received via one or more antennas. Other

components, such as demodulation components and the like, can be included but are omitted for brevity.

[0078] During operation, the frequency shift can vary or jump to different values. This jump is referred to as a frequency jump and can be due, for example, to a new channel being used. It is noted that the frequency jump can include a change in frequency and, optionally, a change in phase.

[0079] The PLL 502 is configured to perform or accommodate a frequency jump with relatively short settling time and phase stability. Thus, the generated LO can change frequencies relatively quickly. The PLL 502 includes correction paths to facilitate fast settling times. Examples of a suitable PLL are shown with regard to Fig. 2 and Fig. 3.

[0080] In one example, the PLL 502 is used for a TX arrangement and a RX arrangement. In this example, the frequency jumps can be based on changing from transmitting operation to receiving operation or from receiving operation to transmitting operation.

[0081] Fig. 6 is a diagram illustrating an exemplary user equipment or mobile communication device 600 that can be utilized with one or more aspects or

embodiments described above.

[0082] The mobile communication device 600, for example, comprises a digital baseband processor 602 that can be coupled to a data store or memory 603, a front end 604 (e.g., an RF front end, an acoustic front end, or the other like front end) and a plurality of antenna ports 607 for connecting to a plurality of antennas 6O6 ₁ to 606 _k (k being a positive integer). The antennas 6O6 ₁ to 606 _k can receive and transmit signals to and from one or more wireless devices such as access points, access terminals, wireless ports, routers and so forth, which can operate within a radio access network or other communication network generated via a network device. The user equipment 600 can be a radio frequency (RF) device for communicating RF signals, an acoustic device for communicating acoustic signals, or any other signal communication device, such as a computer, a personal digital assistant, a mobile phone or smart phone, a tablet PC, a modem, a notebook, a router, a switch, a repeater, a PC, network device, base station or a like device that can operate to communicate with a network or other device according to one or more different communication protocols or standards.

[0083] The front end 604 can include a communication platform, which comprises electronic components and associated circuitry that provide for processing,

manipulation or shaping of the received or transmitted signals via one or more receivers or transmitters 608, a mux/demux component 612, and a mod/demod component 614. The one or more transmitters 608 are configure to use PLL arrangement, such as the arrangement 200 described above, which facilitates generation of the transmitted signals.

[0084] The front end 604, for example, is coupled to the digital baseband processor 602 and the set of antenna ports 607, in which the set of antennas 6O6 ₁ to 606 _k can be part of the front end.

[0085] The user equipment device 600 can also include a processor 602 or a controller that can operate to provide or control one or more components of the mobile device 600. For example, the processor 602 can confer functionality, at least in part, to substantially any electronic component within the mobile communication device 600, in accordance with aspects of the disclosure.

[0086] The processor 602 can operate to enable the mobile communication device 600 to process data (e.g., symbols, bits, or chips) for multiplexing/demultiplexing with the mux/demux component 612, or modulation/demodulation via the mod/demod component 614, such as implementing direct and inverse fast Fourier transforms, selection of modulation rates, selection of data packet formats, inter-packet times, etc. Memory 603 can store data structures (e.g., metadata), code structure(s) (e.g., modules, objects, classes, procedures, or the like) or instructions, network or device information such as policies and specifications, attachment protocols, code sequences for scrambling, spreading and pilot (e.g., reference signal(s)) transmission, frequency offsets, cell IDs, and other data for detecting and identifying various characteristics related to RF input signals, a power output or other signal components during power generation.

[0087] The processor 602 is functionally and/or communicatively coupled (e.g., through a memory bus) to memory 603 in order to store or retrieve information necessary to operate and confer functionality, at least in part, to communication platform or front end 604, the power amplifier (PA) system 610 and substantially any other operational aspects of the PA system 610.

[0088] Fig. 7 is a flow diagram illustrating a method 700 of operating a digital phase locked loop (PLL) to reduce settling times. The method 700 can be used within a transceiver for communication purposes and/or other applications.

[0089] The above systems, devices, arrangements and the like can be referenced and used with or in conjunction with the method 700.

[0090] A forward/output correction path determines a phase error correction at block 702 based on an error signal at an input to a loop filter. In one example, a component differentiates the error signal and multiplies the differentiated error signal with a coefficient C to generate the phase error correction. The coefficient C can be generated as described above. A control circuit or other component can determine or generate the coefficient C. A memory element can be used to store and reuse previous values.

[0091] The loop filter generates a loop signal based on the error signal at block 704. The loop filter can apply a proportional gain to the error signal and/or integrate the error signal as part of generating the loop signal.

[0092] An output combiner applies the determined phase error correction to the loop signal at block 706. The combiner, in one example, adds the determined phase error correction to the loop signal. The added phase error correction cancels or removes at least a portion of a phase error present in the loop signal.

[0093] An oscillator generates an output signal at a selected frequency and at a selected phase at block 708 based on the loop signal. The oscillator can be a digitally controlled oscillator (DCO), a serial combination of a voltage controlled oscillator (VCO) and a digital to time converter (DTC), and the like.

[0094] A time to digital converter (TDC) determines a phase error and generates an error signal based on the determined phase error at block 710. The phase error is determined based on the output signal and an input or reference signal. In one example, a divider generates a comparison signal from the output signal by dividing the output signal by a division factor. The TDC compares the comparison signal with the reference signal to determine the phase error present in the output signal. The TDC generates the error signal based on the determined phase error.

[0095] A feedback combiner removes the correction from the error signal and provides the error signal to the input of the loop filter at block 712. The feedback combiner receives the correction by a feedback correction path. The feedback correction path applies a suitable delay to the correction. The suitable delay is at or about equal to a path delay of the feedback path, which can include the TDC, divider and the like. A control circuit and/or other component can determine the suitable path delay based on measurements, a look up table, previous values and the like.

[0096] By using the correction paths to determine, add and subtract corrections, the settling time for the PLL can be reduced. The correction paths do not interfere with operation of the loop filter so one does not impact the other.

[0097] It is appreciated that the method 700 can be repeated at regular or irregular intervals. [0098] While the methods provided herein are illustrated and described as a series of acts or events, the present disclosure is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts are required and the waveform shapes are merely illustrative and other waveforms may vary significantly from those illustrated. Further, one or more of the acts depicted herein may be carried out in one or more separate acts or phases.

[0099] It is noted that the claimed subject matter may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter (e.g., the systems shown above, are non-limiting examples of circuits that may be used to implement disclosed methods and/or variations thereof). The term "article of manufacture" as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. Those skilled in the art will recognize many modifications may be made to this configuration without departing from the scope or spirit of the disclosed subject matter.

[00100] Examples may include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described herein.

[00101 ] Example 1 is a phase locked loop arrangement and includes a loop filter, a correction path, an oscillator and a feedback path. The loop filter is configured to apply a loop filter adjustment to an error signal to generate a loop signal. The correction path is configured to detect a phase shift at an input of the loop filter and to apply a correction at an output of the loop filter to remove the detected phase shift. The correction includes a phase correction and reduces settling time in response to frequency jumps. The oscillator is configured to generate an output signal based on the corrected loop signal. The feedback path is configured to generate the error signal.

[00102] Example 2 includes the subject matter of Example 1 , including or omitting optional elements, where the arrangement further includes a combiner configured to apply the correction to the loop signal at the output of the loop filter to generate the corrected loop signal.

[00103] Example 3 includes the subject matter of any of Examples 1 -2, including or omitting optional elements, where the forward correction path is configured to obtain a measured phase error at the input to the loop filter and scale the measured phase error by a coefficient and convert the scaled measured phase error to a frequency signal and apply the frequency signal as the correction to the loop signal

[00104] Example 4 includes the subject matter of any of Examples 1 -3, including or omitting optional elements, where wherein the coefficient is based on a reference frequency and a gain of the oscillator.

[00105] Example 5 includes the subject matter of any of Examples 1 -4, including or omitting optional elements, further comprising a feedback correction combiner configured to remove the correction from the error signal at an input of the loop filter.

[00106] Example 6 includes the subject matter of any of Examples 1 -5, including or omitting optional elements, further comprising a correction removal path configured to provide the correction to the feedback correction combiner using a delay associated with the feedback path.

[00107] Example 7 includes the subject matter of any of Examples 1 -6, including or omitting optional elements, where the correction removal path includes a delay element configured to delay the correction provided to the combiner by the delay associated with the feedback path.

[00108] Example 8 includes the subject matter of any of Examples 1 -7, including or omitting optional elements, where the feedback path includes a phase detector configured to generate the error signal.

[00109] Example 9 includes the subject matter of any of Examples 1 -8, including or omitting optional elements, where the phase detector is a time to digital converter (TDC).

[001 10] Example 10 includes the subject matter of any of Examples 1 -9, including or omitting optional elements, where the feedback path includes a divider configured to generate a comparison signal from the output signal and a time to digital converter (TDC) configured to generate the error signal based on the comparison signal and an input signal.

[001 11 ] Example 1 1 includes the subject matter of any of Examples 1 -10, including or omitting optional elements, where the loop filter is non-integrating and the arrangement is type I.

[00112] Example 12 includes the subject matter of any of Examples 1 -1 1 , including or omitting optional elements, where the loop filter includes an integrator and the arrangement is type II.

[00113] Example 13 includes the subject matter of any of Examples 1 -12, including or omitting optional elements, where the oscillator is a digitally controlled oscillator.

[00114] Example 14 is a control loop arrangement that includes a loop component, a correction component, an output component and a feedback component. The loop component is configured to generate a loop signal at its output based on a received error signal. The correction component is configured to determine a correction based on an input to the loop component and apply the correction to the loop signal to generate a corrected loop signal. The output component is configured to generate an output signal based on the corrected loop signal. The feedback component is configured to generate the error signal based on the output signal. The correction component is further configured to remove the correction from the error signal at the input of the loop component.

[00115] Example 15 includes the subject matter of Example 14, including or omitting optional elements, where the output component includes a digitally controlled oscillator (DCO) and is configured to generate the output signal at a changed frequency, wherein the changed frequency is varied from a previous frequency.

[00116] Example 16 includes the subject matter of any of Examples 14-15, including or omitting optional elements, where the error signal includes a phase error and the correction compensates for the phase error.

[00117] Example 17 includes the subject matter of any of Examples 14-16, including or omitting optional elements, where the correction component is configured to measure the error and determine the correction based on the measured error that reduces a settling time for changing a frequency of the output signal.

[00118] Example 18 is a method of reducing settling time for a phase locked loop (PLL). A loop signal is generated from the error signal by the loop filter. The correction is applied to a loop signal at an output of the loop filter. A phase error correction is determined based on the error signal at an input to the loop filter. The phase error correction is applied to the loop signal at an output of the loop filter to generate a corrected loop signal. An output signal is generated within a predetermined frequency based on the corrected loop signal.

[00119] Example 19 includes the subject matter of Example 18, including or omitting optional elements, where the loop signal is generated by applying a

proportional gain to the error signal.

[00120] Example 20 includes the subject matter of any of Examples 18-19, including or omitting optional elements, where the selected frequency is changed to a changed value.

[00121 ] Example 21 includes the subject matter of any of Examples 18-20, including or omitting optional elements, where the predetermined frequency is within a range of about 1 Giga Hertz to about 6 Giga Hertz.

[00122] Example 22 is a phase locked loop (PLL) arrangement. The arrangement includes a means for determining a correction based on a signal at an input to a first component; a means for generating a first component signal at an output of the first component, wherein the first component signal is based on the signal; a means for applying the correction at the output of the first component; a means for generating an output signal at a selected frequency based on the corrected signal; a means for determining an error signal based on the output signal and a reference signal; and a means for removing the correction from the error signal at the input to the first component.

[00123] Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, although a transmission circuit/system described herein may have been illustrated as a transmitter circuit, one of ordinary skill in the art will appreciate that the invention provided herein may be applied to transceiver circuits as well.

[00124] Furthermore, in particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. The component or structure includes a processer executing instructions in order to perform at least portions of the various functions. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and

advantageous for any given or particular application.

[00125] Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term

"comprising".