Related Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63/352,301 , filed on June 15, 2022, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power management integrated circuit (PMIC).

Background

[0003] Fifth-generation (5G) new radio (NR) (5G-NR) has been widely regarded as the next generation of wireless communication technology beyond the current third-generation (3G) and fourth-generation (4G) technologies. In this regard, a wireless communication device capable of supporting the 5G-NR wireless communication technology is expected to achieve higher data rates, improved coverage range, enhanced signaling efficiency, and reduced latency across a wide range of radio frequency (RF) bands, which include a low-band (below 1 GHz), a mid-band (1 GHz to 6 GHz), and a high-band (above 24 GHz). [0004] Downlink and uplink transmissions in a 5G-NR system are widely based on orthogonal frequency division multiplexing (OFDM). In this regard, Figure 1 is a schematic diagram of an exemplary OFDM time-frequency grid 10 illustrating at least one resource block (RB) 12 for physical resource allocation in the 5G-NR system. The OFDM time-frequency grid 10 includes a frequency axis 14 representing a frequency domain and a time axis 16 representing a time domain. Along the frequency axis 14, there are multiple subcarriers 18(1 )-18(M). The subcarriers 18(1 )-18(M) are orthogonally separated from each other by a subcarrier spacing (SOS) (e.g., 15 KHz). Along the time axis 16, there are multiple OFDM symbols 20(1 )-20(N). The OFDM symbols 20(1 )-20(N) may be modulated either as data symbols to carry data payload and/or reference symbols to carry such reference signals as demodulation reference signals (DMRS), sounding reference signals (SRS), and so on. Each of the OFDM symbols 20(1)-20(N) is separated by a cyclic prefix (CP) (not shown) configured to act as a guard band to help overcome inter-symbol interference (ISI) between the OFDM symbols 20(1 )-20(N). In the OFDM time-frequency grid 10, each intersection of the subcarriers 18(1 )-18M) and the OFDM symbols 20(1 )-20(N) defines a resource element (RE) 22.

[0005] In a 5G-NR communication system, an RF signal can be modulated into multiple subcarriers among the subcarriers 18(1 )-18(N) in the frequency domain (along the frequency axis 14) and multiple OFDM symbols among the OFDM symbols 20(1 )-20(N) in the time domain (along the time axis 16). The table (Table 1 ) below summarizes OFDM configurations supported by the 5G-NR communication system.

Table 1

[0006] In the 5G-NR communication system, the RF signal is typically modulated with a high modulation bandwidth in excess of 200 MHz. In this regard, according to Table 1 , the SOS will be 120 KHz and a transition settling time between two consecutive OFDM symbols among the OFDM symbols 20(1 )- 20(N) (e.g., amplitude change of the RF signal) needs to be less than or equal to the CP duration of 0.59 ps.

[0007] In addition, the wireless communication device may also need to support such internet-of-things (loT) applications as keyless car entry, remote garage door opening, contactless payment, mobile boarding pass, and so on. Needless to say, the wireless communication device must also always make 91 1/E911 service accessible under emergency situations. As such, it is critical that the wireless communication device remains operable whenever needed. [0008] Notably, the wireless communication device relies on a battery cell (e.g., Li-Ion battery) to power its operations and services. Despite recent advancement in battery technologies, the wireless communication device can run into a low battery situation from time to time. In this regard, it is desirable to prolong battery life concurrent to enabling fast voltage changes between the OFDM symbols 20(1 )-20(N).

[0009] Embodiments of the disclosure relate to a fast-switching power management integrated circuit (PMIC). The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying a radio frequency (RF) signal modulated in multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a present voltage level in a present one of the time intervals to a future voltage level in an upcoming one of the time intervals with a very short switching interval (e.g., < 20 nanoseconds). When the APT voltage transitions from the present voltage level to the future voltage level, the PMIC opportunistically activates a voltage amplifier to help ensure proper operation of the power amplifier circuit (e.g., maintain the APT voltage at the present level and reduce ripple in the APT voltage). As a result, the PMIC can switch the APT voltage frequently and rapidly with reduced inrush current.

[0010] In one aspect, a PMIC is provided. The PMIC includes a voltage output that outputs an APT voltage to a power amplifier circuit for amplifying an RF signal modulated in a plurality of modulation units each comprising a plurality of time intervals. The PMIC also includes an offset circuit. The offset circuit is coupled to the voltage output and configured to change the APT voltage from a present voltage level in a present time interval among the plurality of time intervals to a future voltage level in an upcoming time interval among the plurality of time intervals during a transition interval that falls within one of the present time interval and the upcoming time interval. The PMIC also includes a voltage amplifier. The voltage amplifier is coupled to an input of the offset circuit. The voltage amplifier is activated at a start of the transition interval and deactivated at an end of the transition interval to generate a modulated voltage at the input of the offset circuit based on an amplifier target voltage determined to cause the modulated voltage to be higher than or equal to a headroom voltage at the end of the transition interval.

[0011] In another aspect, a wireless communication circuit is provided. The wireless communication circuit includes a PMIC. The PMIC includes a voltage output that outputs an APT voltage for amplifying an RF signal modulated in a plurality of modulation units each comprising a plurality of time intervals. The PMIC also includes an offset circuit. The offset circuit is coupled to the voltage output and configured to change the APT voltage from a present voltage level in a present time interval among the plurality of time intervals to a future voltage level in an upcoming time interval among the plurality of time intervals during a transition interval that falls within one of the present time interval and the upcoming time interval. The PMIC also includes a voltage amplifier. The voltage amplifier is coupled to an input of the offset circuit. The voltage amplifier is activated at a start of the transition interval and deactivated at an end of the transition interval to generate a modulated voltage at the input of the offset circuit based on an amplifier target voltage determined to cause the modulated voltage to be higher than or equal to a headroom voltage at the end of the transition interval.

[0012] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. Brief Description of the Drawing Fiqures

[0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] Figure 1 is a schematic diagram of an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid illustrating at least one resource block (RB) for physical resource allocation;

[0015] Figure 2 is a schematic diagram of an exemplary power management integrated circuit (PMIC) configured according to embodiments of the present disclosure to support fast average power tracking (APT) voltage switching;

[0016] Figure 3 is a timing diagram providing an exemplary illustration of the PMIC of Figure 2 configured according to an embodiment of the present disclosure to increase the APT voltage from a present voltage level to a future voltage level;

[0017] Figure 4 is a timing diagram providing an exemplary illustration of the PMIC of Figure 2 configured according to an embodiment of the present disclosure to decrease the APT voltage from a present voltage level to a future voltage level;

[0018] Figure 5 is a timing diagram providing an exemplary illustration of the PMIC of Figure 2 configured according to another embodiment of the present disclosure to decrease the APT voltage from a present voltage level to a future voltage level;

[0019] Figures 6A and 6B are block diagrams providing exemplary illustrations of some power profiles that may be used by the PMIC of Figure 2 for enabling fast APT voltage switching; and

[0020] Figure 7 is a schematic diagram of an exemplary user element wherein the PMIC of Figure 2 can be provided.

Detailed

[0021] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0022] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0023] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0024] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0027] Embodiments of the disclosure relate to a fast-switching power management integrated circuit (PMIC). The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying a radio frequency (RF) signal modulated in multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a present voltage level in a present one of the time intervals to a future voltage level in an upcoming one of the time intervals with a very short switching interval (e.g., < 20 nanoseconds). When the APT voltage transitions from the present voltage level to the future voltage level, the PMIC opportunistically activates a voltage amplifier to help ensure proper operation of the power amplifier circuit (e.g., maintain the APT voltage at the present level and reduce ripple in the APT voltage). As a result, the PMIC can switch the APT voltage frequently and rapidly with reduced inrush current.

[0028] In this regard, Figure 2 is a schematic diagram of an exemplary PMIC

24, which is provided in a wireless communication circuit 25 and configured according to embodiments of the present disclosure to support fast APT voltage switching. The PMIC 24 includes a voltage output 26 that outputs an APT voltage Vcc to a power amplifier circuit 28 in the wireless communication circuit

25. The power amplifier circuit 28 is configured to amplify an RF signal 30 based on the APT voltage Vcc. The RF signal 30, which may be generated by a transceiver circuit 31 in the wireless communication circuit 25, is modulated in multiple modulation units, each of which is further divided into multiple time intervals. In the context of the present disclosure, the modulation units are equivalent to time-division duplex (TDD) time slots or mini time slots, and the time intervals inside each of the modulation units are equivalent to orthogonal frequency division multiplexing (OFDM) symbols, such as the OFDM symbols 20(1 )-20(N) in Figure 1 . In this regard, each of the time intervals can be modulated to carry a data payload (referred herein as “a data symbol”) and a reference signal (referred herein as “a reference symbol”), such as a demodulation reference signal (DMRS), a sounding reference signal (SRS), and so on.

[0029] Given that the power amplifier circuit 28 needs to amplify the data symbols and the reference symbols to different power levels, the PMIC 24 may need to adapt (increase or decrease) the APT voltage Vcc on a per-symbol basis. Moreover, as previously described in Figure 1 , the PMIC 24 must complete the APT voltage Vcc within the respective cyclic prefix (CP) in each of the OFDM symbols 20(1 )-20(N).

[0030] The PMIC 24 includes a voltage amplifier 32 (denoted as “VA”) and an offset circuit 34. The voltage amplifier 32 is coupled to an input 36 of the offset circuit 34 and the offset circuit 34 is coupled to the voltage output 26. In the context of the present disclosure, the power amplifier circuit 28 is assumed to have a much higher bandwidth than that of the offset circuit 34. As described in detail below, the offset circuit 34 is configured to change (increase or decrease) the APT voltage Vcc from a present voltage level (denoted as “VCC(N-I)” in Figures 3 to 5) to a future voltage level (denoted as “VCC(N>” in Figures 3 to 5) between a pair of adjacent time intervals (denoted as “SN-I” and “SN” in Figures 3 to 5). For the sake of distinction, the time intervals SN-I and SN are also referred to as a “present time interval” and an “upcoming time interval,” respectively.

[0031] More specifically, the offset circuit 34 will cause the APT voltage Vcc to change from the present voltage level Vcc(N-i) in the present time interval SN-I to the future voltage level Vcc(N) in the upcoming time interval SN during a transition interval (denoted as “TP” in Figures 3 to 5). Depending on whether the APT voltage Vcc is increasing or decreasing from the present time interval SN-I to the upcoming time interval SN, the transition interval TP can be located either in the present time interval SN-I or in the upcoming time interval SN to ensure that the APT voltage Vcc can reach the future voltage level Vcc(N) by the CP of the upcoming time interval SN.

[0032] As further illustrated in Figures 3 to 5, while the APT voltage Vcc transitions from the present voltage level Vcc(N-i) to the future voltage level Vcc(N) during the transition interval TP, the voltage amplifier 32 is activated at a start of the transition interval TP (denoted as “Ti”) and deactivated at an end of the transition interval TP (denoted as “T2”) to ensure proper operation of the power amplifier circuit 28. According to an embodiment of the present disclosure, the voltage amplifier 32 will provide a modulated voltage VAMP at an input 36 of the offset circuit 34. In a non-limiting example, the voltage amplifier 32 is configured to generate the modulated voltage V MP based on an amplifier target voltage VTGT-AMP and one of a lower supply voltage VSUPL and a higher supply voltage VSUPH (VSUPH > VSUPL).

[0033] As discussed in detailed examples in Figures 3 to 5, the amplifier target voltage VTGT-AMP is so determined to ensure that the voltage amplifier 32 can maintain the modulated voltage VAMP at or above a headroom voltage (denoted as “VNHEAD” in Figures 3 to 5), which is greater than 0 V, at the end T2 of the transition interval TP. As a result, the voltage amplifier 32 can maintain the APT voltage Vcc at the present voltage level Vcc(N-i) and suppress ripple in the APT voltage Vcc during the transition interval TP to thereby ensure the proper operation of the power amplifier circuit 28 during the transition interval TP. [0034] According to an embodiment of the present disclosure, the PMIC 24 can include a control circuit 38, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In one aspect, the control circuit 38 may be configured to determine whether the transition interval TP should be within the present time interval SN-I or the upcoming time interval SN based on a differential AVcc between the present voltage level Vcc(N-i) and the future voltage level Vcc(N) ( VCC = Vcc(N--i) - Vcc(N)). Understandably, the differential AVcc will be positive when the present voltage level Vcc(N-i) is higher than the future voltage level Vcc(N) or negative when the present voltage level VCC(N-I) is lower than the future voltage level VCC(N). In a non-limiting example, the control circuit 38 can receive a modulated target voltage VTGT, which indicates the future voltage level Vcc(N) in the upcoming time interval SN, from the transceiver circuit 31 . Accordingly, the control circuit 38 may control the offset circuit 34 (e.g., via a control signal 40) to transition from the present voltage level Vcc(N-i) to the future voltage level Vcc(N) during the transition interval TP.

[0035] In another aspect, the control circuit 38 may also be configured to determine the amplifier target voltage VTGT-AMP based on the determined differential AVcc. In a non-limiting example, when the future voltage level Vcc(N) is higher than the present voltage level Vcc(N-i), as illustrated in Figure 3, the amplifier target voltage VTGT-AMP is equal to a sum of the future voltage level Vcc(N) and a markup voltage (denoted as “VDIFF”), as shown in equation (Eq. 1 ) below. In another non-limiting example, when the future voltage level VCC(N) is lower than the present voltage level VCC(N-I), as illustrated in Figures 4 and 5, the amplifier target voltage VTGT-AMP is equal to a sum of the present voltage level Vcc(N-i) and the markup voltage VDIFF, as shown in equation (Eq. 2) below.

VTGT-A P = VcC(N) + VDIFF (Eq. 1 ) VTGT-AMP = VcC(N-1) + VDIFF (Eq. 2)

[0036] In the equations (Eq. 1 and Eq. 2), the markup voltage VDIFF can be of different values depending on how the APT voltage Vcc will change from the present time interval SN-I to the upcoming time interval SN. In this regard, by changing the amplifier target voltage VTGT-AMP and, more specifically the markup voltage VDIFF, the control circuit 38 can cause the voltage amplifier 32 to generate the modulated voltage VAMP at appropriate levels during the transition interval TP to maintain proper operation of the power amplifier circuit 28.

[0037] In yet another aspect, the control circuit 38 may be further configured to activate the voltage amplifier 32 at the start Ti of the transition interval TP and deactivate the voltage amplifier 32 at the end T2 of the transition interval TP. In a non-limiting example, the control circuit 38 can cause the voltage amplifier 32 to be deactivated in response to receiving the lower supply voltage VSUPL or activated in response to receiving the higher supply voltage VSUPH. By controlling the offset circuit 34 to change the APT voltage Vcc and opportunistically activating/deactivating the voltage amplifier 32 to ensure proper operation of the power amplifier circuit 28 during the transition interval TP, the PMIC 24 can switch the APT voltage Vcc efficiently under the increasingly stringent switching time requirements (e.g., < 20 ns).

[0038] The PMIC 24 also includes a multi-level charge pump (MCP) 42. The MCP 42, which may be a direct current (DC)-DC buck-boost converter, is configured to generate a low-frequency voltage VDC (e.g., DC voltage) based on a battery voltage VBAT. Specifically, the MCP 42 may operate in a buck mode to generate the low-frequency voltage VDC at OXVBAT or 1 XVBAT, or in a boost mode to generate the low-frequency voltage VDC at 2XVBAT. The MCP 42 may be configured to toggle between the buck mode and the boost mode based on a particular duty cycle (e.g., 20%@0XVBAT, 30%@ 1 XVBAT, and 50%@2XVBAT). AS such, the MCP 42 may be controlled to generate the low-frequency voltage VDC at a desired level. [0039] In an embodiment, the control circuit 38 may be further configured to generate an offset target voltage VTGT-OFF based on the modulated target voltage VTGT. The offset target voltage VTGT-OFF may indicate the future voltage level cc(N) of the APT voltage Vcc. Accordingly, the MCP 42 may determine and operate based on a corresponding duty cycle to generate the low-frequency voltage VDC at the desired level as indicated by the offset target voltage VTGT-OFF. [0040] The PMIC 24 also includes a power inductor Lp. The power inductor Lp is coupled between the MCP 42 and the voltage output 26 and is configured to induce a low-frequency current IDC (e.g., a DC current) based on the low- frequency voltage VDC. Understandably, the low-frequency current IDC that may be induced is a function of the low-frequency voltage VDC and an inductance of the power inductor Lp. Accordingly, the control circuit 38 may further change the low-frequency current IDC based on the offset target voltage VTGT-OFF. In an embodiment, the MCP 42 may receive feedback from the APT voltage Vcc. [0041] Herein, the offset circuit 34 includes an offset capacitor COFF and a bypass switch SBYP. The offset capacitor COFF is coupled between the input 36 and the voltage output 26, and the bypass switch SBYP is coupled between the input 36 and a ground (GND).

[0042] Under one operating scenario, the APT voltage Vcc is set to increase from the present voltage level Vcc(N-i) in the present time interval SN-I to the future voltage level Vcc(N) in the upcoming time interval SN (VCC(N-I) < Vcc(N)). In this regard, the control circuit 38 will set the offset target voltage VTGT-OFF to the future voltage level Vcc(N) of the APT voltage Vcc to cause the low-frequency current IDC to be generated at a desired amount to thereby charge the offset capacitor COFF to the future voltage level Vcc(N).

[0043] The control circuit 38 will open the bypass switch SBYP and activate the voltage amplifier 32 at the start of the transition interval TP to generate the amplifier target voltage VTGT-AMP at a level higher than the future voltage level Vcc(N) such that a current ITRAN can flow from the MCP 42 through the offset capacitor COFF and sink in the voltage amplifier 32. In a non-limiting example, the PMIC 24 can include an auxiliary circuit 44, which can provide additional current to help maintain the modulated voltage VAMP in the presence of the current ITRAN. As a result, the current IT AN will gradually charge the offset capacitor COFF to the future voltage level Vcc(N) during the transition interval TP. When the offset capacitor COFF is charged up to the future voltage level Vcc(N) at the end of the transition interval TP, the control circuit 38 deactivates the voltage amplifier 32 and closes the bypass switch SBYP. Thereafter, the offset capacitor COFF and the MCP 42 will maintain the APT voltage Vcc at the future voltage level VCC(N) in the remainder of the upcoming time interval SN.

[0044] The operating scenario described above can be graphically illustrated in Figure 3. Figure 3 is a timing diagram providing an exemplary illustration as to how the PMIC 24 of Figure 2 operates under the above-described operating scenario to increase the APT voltage Vcc. Elements in Figure 2 are referenced in Figure 3 and will not be re-described herein.

[0045] As illustrated, the transition interval TP falls completely within the upcoming time interval SN, wherein the start Ti of the transition interval TP is aligned with a boundary To (a.k.a. a starting time of the CP in the upcoming time interval SN) between the present time interval SN-I and the upcoming time interval SN, and the end T2 of the transition interval TP comes after time Ta (a.k.a. an ending time of the CP in the upcoming time interval SN). Understandably, the CP is typically much shorter than the transition interval TP. Herein, the modulated target voltage VTGT indicates that the APT voltage Vcc will increase from the present voltage level Vcc(N-i) (e.g., 2.3 V) in the present time interval SN-I to the future voltage level Vcc(N) (e.g., 2.9 V) in the upcoming time interval SN.

Accordingly, the control circuit 38 determines the offset target voltage VTGT-OFF to be equal to the future voltage level Vcc(N).

[0046] As for the amplifier target voltage VTGT-AMP, the control circuit 38 is configured to set the markup voltage VDIFF in the equation (Eq. 1 ) to be equal to the headroom voltage VNHEAD (VTGT-AMP = Vcc(N) + VNHEAD). At time T1, the control circuit 38 opens the bypass switch SBYP and activates the voltage amplifier 32 (e.g., by coupling the higher supply voltage VSUPH to the voltage amplifier 32). Accordingly, the voltage amplifier 32 will generate the modulated voltage VAMP at the input 36 in accordance with the amplifier target voltage VTGT-AMP. In a nonlimiting example, the voltage amplifier 32, with assistance from the auxiliary circuit 44, can quickly drive the modulated voltage VAMP from a GND level to the differential AVcc (AVcc < 0) at time T3 to help stabilize the APT voltage Vcc during the transition interval TP. Thereafter, the voltage amplifier 32 gradually decreases the modulated voltage VAMP to the headroom voltage VNHEAD at time T ₂ .

[0047] Starting at time T1, the offset capacitor GOFF is gradually charged up to reach the future voltage level Vcc(N) at time T2. Accordingly, at time T2, the control circuit 38 closes the bypass switch SBYP and deactivates the voltage amplifier 32 to let the modulated voltage VAMP return to the GND level. The APT voltage Vcc, which equals a sum of the modulated voltage VAMP and the offset voltage VOFF, will settle at the future voltage level VCC(N> at time T3. Notably, since the voltage amplifier 32 maintains the modulated voltage VAMP at or above the headroom voltage VNHEAD while the bypass switch SBYP is toggled, the APT voltage Vcc will not drop below the headroom voltage VNHEAD, thus ensuring proper operation of the power amplifier circuit 28.

[0048] With reference back to Figure 2, under another operating scenario, the APT voltage Vcc is set to decrease from the present voltage level Vcc(N-i) in the present time interval SN-I to the future voltage level Vcc(N) in the upcoming time interval SN (VCC(N-I) > Vcc(N)). In this regard, the control circuit 38 will set the offset target voltage VTGT-OFF to the future voltage level Vcc(N) of the APT voltage Vcc to cause the low-frequency current IDC to be generated at a desired amount to thereby cause the offset capacitor GOFF to be discharged to the future voltage level Vcc(N).

[0049] The control circuit 38 will open the bypass switch SBYP and activate the voltage amplifier 32 at the start of the transition interval TP to generate the amplifier target voltage VTGT-AMP at the present voltage level Vcc(N--i) such that the current ITRAN can flow from the voltage amplifier 32 through the offset capacitor GOFF and return to the MCP 42 and/or the power amplifier circuit 28. In a nonlimiting example, the auxiliary circuit 44 can provide additional current to help maintain the modulated voltage AMP in the presence of the current ITRAN. AS a result, the offset capacitor GOFF will be gradually discharged to the future voltage level Vcc(N) during the transition interval TP. When the offset capacitor GOFF is discharged to the future voltage level VCC(NJ at the end of the transition interval TP, the control circuit 38 deactivates the voltage amplifier 32 and closes the bypass switch SBYP. Thereafter, the offset capacitor GOFF and the MCP 42 will maintain the APT voltage Vcc at the future voltage level cc(N) in the remainder of the upcoming time interval SN.

[0050] The operating scenario described above can be graphically illustrated in Figures 4 and 5. Figure 4 is a timing diagram providing an exemplary illustration as to how the PMIC 24 of Figure 2 operates under one possibility of the above-described operating scenario to decrease the APT voltage Vcc. More specifically, Figure 4 illustrates a situation where the headroom voltage VNHEAD (e.g., 0.4 V) is lower than the differential AVcc (e.g., 0.6 V) between the present voltage level Vcc(N-i) and the future voltage level Vcc(N) (VNHEAD < AVcc).

Elements in Figure 2 are referenced in Figure 4 and will not be re-described herein.

[0051] As illustrated, the transition interval TP falls completely within the present time interval SN-I , wherein the start Ti of the transition interval TP begins prior to a boundary To between the present time interval SN-I and the upcoming time interval SN, and the end T2 of the transition interval TP is aligned with the boundary To (a.k.a. a starting time of the CP in the upcoming time interval SN). Understandably, the CP is typically much shorter than the transition interval TP. Herein, the modulated target voltage VTGT indicates that the APT voltage Vcc will decrease from the present voltage level VCC(N-I) (e.g., 2.9 V) in the present time interval SN-I to the future voltage level VCC(N) (e.g., 2.3 V) in the upcoming time interval SN. Accordingly, the control circuit 38 determines the offset target voltage VTGT-OFF to be equal to the future voltage level Vcc(N).

[0052] As for the amplifier target voltage VTGT-AMP, the control circuit 38 is configured to set the markup voltage VDIFF in the equation (Eq. 2) to 0 V (VTGT-AMP = Vcc(N-i) + 0). At time T1, the control circuit 38 opens the bypass switch SBYP and activates the voltage amplifier 32 (e.g., by coupling the higher supply voltage VSUPH to the voltage amplifier 32). Accordingly, the voltage amplifier 32 will generate the modulated voltage VAMP at the input 36 in accordance with the amplifier target voltage VTGT-AMP. In a non-limiting example, the voltage amplifier 32, with assistance from the auxiliary circuit 44, can instantly drive the modulated voltage VAMP from a GND level to the headroom voltage VNHEAD at time Ti. Thereafter, the voltage amplifier 32 will continue to drive the modulated voltage VAMP up to the voltage differential AVcc at time T2.

[0053] Starting at time T1, the offset capacitor GOFF is gradually discharged to reach the future voltage level Vcc(N) at time T2. Accordingly, at time T2, the control circuit 38 closes the bypass switch SBYP and deactivates the voltage amplifier 32 to let the modulated voltage VAMP return to the GND level at time T3. The APT voltage Vcc, which equals a sum of the modulated voltage VAMP and the offset voltage VOFF, will settle at the future voltage level Vcc(N) at time T3.

Notably, since the voltage amplifier 32 maintains the modulated voltage VAMP at or above the headroom voltage VNHEAD while the bypass switch SBYP is toggled, the APT voltage Vcc will not drop below the headroom voltage VNHEAD, thus ensuring proper operation of the power amplifier circuit 28.

[0054] Figure 5 is a timing diagram providing an exemplary illustration as to how the PMIC 24 of Figure 2 operates under another possibility of the abovedescribed operating scenario to decrease the APT voltage Vcc. More specifically, Figure 5 illustrates a situation where the headroom voltage VNHEAD (e.g., 0.4 V) is higher than or equal to the differential AVcc (e.g., 0.1 V) between the present voltage level VCC(N-I) and the future voltage level VCC(NJ (VNHEAD > AVcc). Elements in Figure 2 are referenced in Figure 5 and will not be redescribed herein.

[0055] As illustrated, the transition interval TP falls completely within the present time interval SN-I , wherein the start T1 of the transition interval TP begins prior to a boundary To between the present time interval SN-I and the upcoming time interval SN, and the end T2 of the transition interval TP is aligned with the boundary To (a.k.a. a starting time of the CP in the upcoming time interval SN). Understandably, the CP is typically much shorter than the transition interval TP. Herein, the modulated target voltage VTGT indicates that the APT voltage Vcc will decrease from the present voltage level VCC(N-I) (e.g., 2.9 V) in the present time interval SN-I to the future voltage level Vcc(N) (e.g., 2.8 V) in the upcoming time interval SN. Accordingly, the control circuit 38 determines the offset target voltage VTGT-OFF to be equal to the future voltage level Vcc(N).

[0056] As for the amplifier target voltage VTGT-AMP, the control circuit 38 is configured to set the markup voltage VDIFF in the equation (Eq. 2) to equal the headroom voltage VNHEAD minus the differential AVcc between the present voltage level Vcc(N-i) and the future voltage level VCC(N) (VTGT-AMP = VCC(N-I) + NHEAD - AVcc). At time Ti, the control circuit 38 opens the bypass switch SBYP and activates the voltage amplifier 32 (e.g., by coupling the higher supply voltage VSUPH to the voltage amplifier 32). Accordingly, the voltage amplifier 32 will generate the modulated voltage VAMP at the input 36 in accordance with the amplifier target voltage VTGT-AMP. In a non-limiting example, the voltage amplifier 32, with assistance from the auxiliary circuit 44, can instantly drive the modulated voltage VAMP from a GND level to the differential AVcc at time Ti. Thereafter, the voltage amplifier 32 will continue to drive the modulated voltage VAMP up to the headroom voltage VNHEAD at time T2.

[0057] Starting at time Ti, the offset capacitor COFF is gradually discharged to reach the future voltage level Vcc(N) at time T2. Accordingly, at time T2, the control circuit 38 closes the bypass switch SBYP and deactivates the voltage amplifier 32 to let the modulated voltage VAMP return to the GND level at time T3. The APT voltage Vcc, which equals a sum of the modulated voltage VAMP and the offset voltage VOFF, will settle at the future voltage level Vcc(N) at time T3.

Notably, since the voltage amplifier 32 maintains the modulated voltage VAMP at or above the headroom voltage VNHEAD while the bypass switch SBYP is toggled, the APT voltage Vcc will not drop below the headroom voltage VNHEAD, thus ensuring proper operation of the power amplifier circuit 28.

[0058] With reference back to Figure 2, in examples describe above, the control circuit 38 is configured to receive the modulated target voltage VTGT on a per time interval (a.k.a. per OFDM symbol) basis. In other words, the transceiver circuit 31 must communicate the future voltage level VCC(N) in the upcoming time interval SN during, or even before, the present time interval SN-I . AS previously described in Figure 1 , in a time-division duplex (TDD) system, multiple time intervals (a.k.a. OFDM symbols) can be include in a modulation unit (a.k.a. TDD time slot or mini time slot). As such, it may be possible for the control circuit 38 to receive the modulated target voltage VTGT on a per modulation unit (a.k.a. TDD time slot or mini time slot) basis.

[0059] In this regard, the PMIC 24 may be preconfigured to include multiple power profiles 46(1 )-46(N). In a non-limiting example, the power profiles 46(1 )- 46(N) can be organized into a profile lookup table (LUT) 48 and stored in a memory circuit 50. The power profiles 46(1 )-46(N) may be stored in the memory circuit 50 by the transceiver circuit 31 via, for example, an RF front-end (RFFE) interface (not shown).

[0060] Figures 6A and 6B are block diagrams providing exemplary illustrations of the power profiles 46(1 )-46(N) that may be employed by the PMIC 24 of Figure 2 for enabling fast switching of the APT voltage Vcc. Herein, each of the power profiles 46(1 )-46(N) corresponds to a TDD time slot.

[0061] Figure 6A shows an exemplary power profile 46A among the power profiles 46(1 )-46(N). As shown, the power profile 46A may be determined to indicate the future voltage levels of one or more data symbols and one or more SRS symbols.

[0062] Figure 6B shows an exemplary power profile 46B among the power profiles 46(1 )-46(N). As shown, the power profile 46B may be determined to indicate the future voltage levels of one or more data symbols and one or more DMRS symbols.

[0063] With reference back to Figure 2, in an embodiment, the transceiver circuit 31 may communicate a profile indication 52 to indicate a selected power profile among the power profiles 46(1 )-46(N) to be used for an upcoming modulation unit (e.g., TDD time slot) during, or prior to, a present modulation unit (e.g., TDD time slot). Accordingly, the control circuit 38 may retrieve the selected power profile from the profile LUT 48 based on the received profile indication 52. [0064] The PMIC 24 of Figure 2 can be provided in a user element to enable fast voltage switching. Figure 7 is a schematic diagram of an exemplary user element 100 wherein the PMIC of Figure 2 can be provided.

[0065] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0066] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0067] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0068] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.