FAT CONDUCTOR

WIPO Patent Application WO2002054414

A3

A fat conductor electrically interconnecting between a pair of substantially parallel plates (201, 202) wherein each of the plates (201, 202) has a prearranged pattern of conducting surface coating regions on the central interior face side thereof, and the fat conductor is specifically for use in sandwiched constructions of the plates (201, 202) having encapsulated dielectric film therebetween, the fat conductor including: two thin conductive surface coating pads (206, 207) of substantially complementary size and one of the two pads (206, 207) is located on each facing plate (201, 202) and the pads (206, 207) are situated to face each other when the plates (201, 202) are sandwiched together and each pad (206, 207) has an associated conductive surface coating path on its respective surface; a perimeter wall of adhesive (208) arranged around one of the pads (206, 207); and a conductive paste (209) situated within the perimeter wall (208) such that when the plates (201, 202) are sandwiched together there is formed an electrically conductive connection between the pads (206, 207) via the paste (209).

JP4486770	Flat panel display board
JP3293135	[Title of the Invention] A semiconductor device including a circuit cell array.
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AMIR JACK (IL)
BEN-SHALOM AMIR (IL)

PCT/IL2001/001211

January 03, 2003

December 27, 2001

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MAGIN DISPLAY TECHNOLOGIES LTD (IL)
AMIR JACK (IL)
BEN-SHALOM AMIR (IL)

G02F1/1345; H05K3/46; H01L23/532; H01R4/04; H05K1/03; H05K1/16; H05K3/40; (IPC1-7): G02F1/1343; H05K1/11

US20010006116A1	2001-07-05
US6245696B1	2001-06-12
US5371327A	1994-12-06
US5237130A	1993-08-17
US5179460A	1993-01-12
US4682858A	1987-07-28
US4624529A	1986-11-25
US4469410A	1984-09-04
US4308533A	1981-12-29

See also references of EP 1354237A4

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