Title:
FAULT DETECTION IN DIGITAL SYSTEM
Document Type and Number:
WIPO Patent Application WO2000004449
Kind Code:
A3
Abstract:
The present invention relates to a fault testing in digital systems and devices therefor. A processor unit (2) is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyser (3) is activated and the processor unit (2) generates a set of stimuli, influencing the appropriate logical units. The output response analyser (3) collects responses of the stimuli at different nodes (13) in the digital system (1) and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. Preferably, the present state of the processor (2) and other logical units are stored in a storage means (15) prior to the test and recovered after the testing is finished. The invention functions both at chip and board levels, and on systems with several units.
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Inventors:
HOLMBERG PER ANDERS
HALVORSSON DAN OLOV
JONSSON TOMAS
HALVORSSON DAN OLOV
JONSSON TOMAS
Application Number:
PCT/SE1999/001062
Publication Date:
April 20, 2000
Filing Date:
June 15, 1999
Export Citation:
Assignee:
ERICSSON TELEFON AB L M (SE)
International Classes:
G06F11/277; (IPC1-7): G06F11/26
Foreign References:
| US5051996A | 1991-09-24 | |||
| US5638383A | 1997-06-10 | |||
| US5255208A | 1993-10-19 | |||
| US5475694A | 1995-12-12 | |||
| EP0631235A1 | 1994-12-28 | |||
| US5525971A | 1996-06-11 |
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