TECHNICAL FIELD

[0001] The present subject matter relates, in general, to fault detection in a power system. In particular, the present subject matter relates to fault detection in a shunt capacitor bank.

BACKGROUND

[0002] Shunt Capacitor Banks (SCBs) are used for reactive power compensation in a power system. Typically, SCBs include capacitor elements which contain capacitor groups made of capacitors connected in series and parallel. Reactive power compensation in a power system provides reactive power support which improves the power system capacity, improves the power factor of the system, and provides better voltage stability. However, power systems often suffer from internal or external faults and disturbances, which may result in arcing faults in the SCB. If the arcing faults that occur in a shunt capacitor bank go undetected, it can cause damage to the complete capacitor bank.

BRIEF DESCRIPTION OF DRAWINGS

[0003] The features, aspects, and advantages of the present subject matter will be better understood with regard to the following description and accompanying figures. The use of the same reference number in different figures indicates similar or identical features and components.

[0004] Fig. 1 illustrates an example arrangement of capacitor units in the SCB.

[0005] Fig. 2 illustrates a power system including a device for fault detection in an SCB, in accordance with an embodiment of the present subject matter.

[0006] Fig. 3 illustrates the locus of the impedance angle when a phase arcing fault occurs between phase A and phase B in accordance with the present subject matter.

[0007] Fig. 4 illustrates a method for detecting a fault in a shunt capacitor bank, in accordance with an embodiment of the present subject matter. SUMMARY

[0008] Embodiments of the present invention relate to methods for detecting a fault in a shunt capacitor bank connected to a power system, devices for fault detection, and computer readable storage mediums including instructions for fault detection. Objectives of the embodiments of the invention may be to identify a phase arcing fault within a capacitor bank within a short time interval, thereby avoiding the damage in the capacitor bank by early detection of cascading failure of units.

[0009] According to a first aspect, a method for detecting a fault in a shunt capacitor bank connected in a power system is provided. The method includes obtaining voltage measurements and current measurements at a terminal of the shunt capacitor bank. Based on the voltage and current measurements, an electrical parameter is computed. The electrical parameter computed is an impedance angle or an active power. Further, a difference between a first and a second value of the electrical parameter is calculated based on which a fault is detected.

[0010] According to a second aspect, a device for detecting a fault in a shunt capacitor bank connected to a power system is provided. The device includes a processor and a fault detection module executable by the processor. The fault detection module is configured to obtain voltage measurements and current measurements at a terminal of the shunt capacitor bank. The fault detection module is configured to compute an electrical parameter based on the voltage and current measurements. The electrical parameter computed is an impedance angle or an active power. Further, a difference between a first and a second value of the electrical parameter is calculated, based on which the fault is detected.

[0011] According to a third aspect, a non-transitory computer readable medium containing program instruction is provided, which when executed causes a device to detect a fault in a shunt capacitor bank connected to a power system.

[0012] According to one implementation, voltage measurements and current measurements are obtained in each phase at the terminal of the shunt capacitor bank.

[0013] According to another implementation, the first and the second value of the electrical parameter are consecutive to each other.

[0014] According to another implementation, detecting the fault comprises determining whether a predefined criterion is met, where the predefined criterion comprises an absolute value of sum of the difference between the first and the second value of the electrical parameter of a first one of the phases and the difference between the first and the second value of the electrical parameter of a second one of the phases is greater than the difference between the first and the second value of the electrical parameter of a third one of the phases and the absolute value of difference between the first and the second value of the electrical parameter of the first one of the phases and the absolute value of difference between the first and the second value of the electrical parameter of the second one of the phases are each greater than the respective threshold value.

[0015] According to another implementation, the fault is detected as a phase to phase fault between the first one of the phases and the second one of the phases.

[0016] According to another implementation, the respective threshold value of the electrical parameter is set based on accuracy of the measurement equipment.

[0017] According to another implementation, the shunt capacitor bank is connected to a three-phase transmission line in a double wye configuration.

[0018] According to another implementation, the fault is detected prior to cascading failure of the shunt capacitor bank.

[0019] According to another implementation, to determine the electrical parameter, an arc resistance is computed based on Warrington formula.

DETAILED DESCRIPTION

[0020] The present subject matter relates to fault detection in a shunt capacitor bank connected to a power system. The fault may be an arc-over within the capacitor bank, between the phases.

[0021] During phase arcing faults in an SCB, such as failure of capacitor elements or a flashover within the rack caused by a short circuit over single or multiple series of units of the same phase, a protection scheme may initiate an alarm to notify the operator about a potential shunt capacitor bank failure. Tripping of the bank helps minimize damage and prevent possible rapid cascading of the fault by other failed elements/units. Therefore, it is desirable to detect phase arcing faults within a short duration of time to avoid cascading failure in the SCB.

[0022] Conventionally, in one technique the magnitude of current and its peak are used to detect arcing faults in a shunt capacitor bank. The current-magnitude based method may fail during system disturbances that may occur near the capacitor bank. In another technique, arcing faults with ground are detected based on third order harmonics present in the voltage signal. However, this technique fails to detect the phase arcing faults. In another technique, the arcing faults are detected with the magnitude of negative sequence current. However, this technique is sensitive to external disturbances and needs to be coordinated with other protection systems of the power system which would introduce a delay of 15-20 power cycles. Also, the operation level to setup the negative sequence current based detection technique is complex.

[0023] The most effective protection for an arc-over within the capacitor bank is provided by a fast unbalance relay. Although the unbalance trip relay is the most effective protection for arc detection of a series section, the neutral voltage type of unbalance relay cannot be relied upon for rack fault protection on capacitor banks where all three phases are not well separated. In the present example, an ungrounded single wye capacitor bank with two series groups per phase, where all three phases are installed upon a single steel structure is considered. The individual phases are stacked over each other so that the initial fault may occur as a mid-rack phase-to-phase fault. This fault does not cause an unbalance of the neutral voltage or neutral current if grounded, due to which a neutral unbalance relay does not respond. The initial fault may spread until it becomes severe enough to operate the time or instantaneous overcurrent relays. However, there may be considerable damage involving all three phases before the bank trips.

[0024] With a shunt capacitor bank constructed such that the individual phases are well separated on separate structures, an arc-over within the capacitor bank will begin as an arc- over of a single series group. Such a fault produces very little phase overcurrent. If an unbalance relay protection scheme fails to operate, more and more series groups of the same phase can become involved until the bank overcurrent relays trip the bank or fuses clear. This fault is accompanied by heavy damage to the bank, including many blown fuses and ruptured capacitor units. Instantaneous overcurrent relays are usually not effective for rack faults because of their required high setting.

[0025] For example, a lOMVAr, 52kV externally fused grounded double wye connected capacitor bank with parameters as depicted in Table 1 is analyzed for performance of various protection schemes based on the magnitude of voltages and current.

TABLE 1 : PARAMETERS OF SCB USED FOR FAULT ANALYSIS

[0026] Fig. 1 illustrates an example arrangement of capacitor units 101 in the SCB and the results of the analysis are shown in Table 2, where the fault location in per unit value is denoted by ‘m’. The value of ‘m’ can vary between ‘0’ and ‘1’, where ‘0’ denotes the fault location for a phase arcing fault at the top of the SCB 102 and ‘ 1’ denotes the fault location of a phase arcing fault at the bottom of the SCB 104. In the present example, a phase arcing fault at different fault positions (m) is considered. The primary protection scheme that was employed for tripping of the relay was overvoltage (OV) set to 110% of the rated voltage and the overcurrent (OC) set to 135% of the rated current. [0027] As it can be observed from Table 2 shown below, when a phase arcing fault occurs towards the bottom of the SCB (m=0.875) it is observed that the rise in voltage and the magnitude of fault current is lesser than the pre-set values of the OV and OC to detect. As a result, the value of voltage across the healthy units of the bank continue to rise till they reach 110% of the rated voltage before the protection relay trips which may subsequently lead to a cascading failure in the SCB.

TABLE 2: SIMULATION RESULTS FOR PHASE ARCING FAULT AT DIFFERENT FAULT POSITIONS

[0028] Also, as the fault is a phase arcing fault there will be no neutral current due to the unbalance and hence, a protection scheme based on neutral current will not respond. Further, the negative sequence-based protection will introduce a time delay of 15-20 power cycles for adequate coordination between other protection devices of the power system for faults external to the bank. An arc-over fault between different phases produces very little phase current and phase overvoltage and this fault results in increase in the voltage of healthy units. Hence, there is a need for capacitor bank to be protected from phase arcing faults at the earliest to minimize the damage.

[0029] The present subject matter provides a fast and reliable protection scheme for the shunt capacitor bank connected to a power system against phase arcing faults. Detecting the fault is based on values of three phase voltages and currents measured at the terminal of the SCB. An example method includes obtaining three phase voltages and currents measurements at the SCB terminal as a voltage signal or a current signal respectively, using measurement equipment. The signals are continuously measured to compute an electrical parameter such as impedance angle or active power or both at each phase. Further, a difference between a first and a second value of the electrical parameter is computed and tested for a predefined criterion to detect the fault.

[0030] The proposed methods and devices identify the phase arcing fault within the capacitor bank, also referred to as rack-to-rack faults, within a short time interval, thereby avoiding the damage in the capacitor bank by early detection of cascading failure of units. The proposed method is insensitive to external system disturbances enhancing the response time. Further, no additional sensors or hardware equipment are required for detection of the arcing faults.

[0031] The above and other features, aspects, and advantages of the subject matter will be better explained with regard to the following description and accompanying figures. Wherever possible, the same reference numbers are used in the drawings and the following description to refer to the same or similar parts. While several examples are described, modifications, adaptations, and other implementations are possible.

[0032] Fig. 2 illustrates a power system including a device for fault detection in an SCB, in accordance with an embodiment of the present subject matter. A power system 200 as shown in the figure includes a three-phase transmission line that may be a part of a transmission and a distribution network. While for discussion purposes the SCB is shown as connected to power transmission lines, it will be understood that the teachings of the present subject matter can be applied to SCBs connected to other power lines also. A shunt capacitor bank 202 may be connected to the power system 200 to provide reactive power support. In one example, the SCB may be a double wye configuration connected to the three phases of the transmission line. However, the SCB 202 may have various configurations depending on the manner in which the capacitor units may be connected.

[0033] It will be understood that the power system 200 for fault detection may include a plurality of additional components or devices for monitoring, sensing, and controlling various parameters that may be associated with the shunt capacitor bank and the power system but are not shown for brevity. For example, components such as circuit breakers, sensors, current transformers, voltage transformers, loads connected to the power system, shunt reactors, intelligent electronic devices lEDs, protective relays and the like may be connected.

[0034] The techniques of the present subject matter may be implemented with one or more devices associated with the power system. The devices may include current transformers, voltage transformers, circuit breakers, and devices to detect the fault location. As shown in Fig. 2, a device 204 may be configured to receive voltage and current measurements at the terminal of the shunt capacitor bank. The device 204 may be configured to detect a fault in the SCB due to internal disturbances, such as failure of capacitor elements or a flashover within the rack, and external disturbances, such as increased level of harmonics or sustained over voltages. In response to that the device 204 detects the fault in the SCB, the device 204 may be configured to send a trip signal to the circuit breaker of the shunt capacitor bank 202. In one example, the device 204 may be an intelligent electronic device (TED). In another example, the device 204 may be any computing device, such as a server, a desktop device, a laptop, etc., which may receive the measurements from an IED.

[0035] In an example, the present subject matter may be implemented by one or more modules. The modules may be implemented as instructions stored in non-transitory computer readable medium and executable by one or more processors. For instance, in the example where the device 204 performs the method, the modules are executed by the processors of the device 204. In case the method is implemented in part by the device 204 and in part by a server, the modules (depending on the step) will be distributed accordingly in the device 204 and the server. [0036] In one example, the device 204 may be configured to receive input measurement signals from various measurement equipment connected to the shunt capacitor bank, such as current transformers, potential transformers, Rogowski coils or other measurement sensors. The device 204 may process the measurements obtained with the help of a processor 220. The processor 220 may be implemented as a dedicated processor, a shared processor, or a plurality of individual processors, some of which may be shared. The device 204 may include a memory 226, that may be communicatively connected to the processor 220. Among other capabilities, the processor 220 may fetch and execute computer-readable instructions, stored in the memory 226. In one example, the memory 226 may store a fault detection module 222. In other examples, the fault detection module 222 may be external to the memory 226. The memory 226 may include any non-transitory computer-readable medium including, for example, volatile memory, such as RAM, or non-volatile memory, such as EPROM, flash memory, and the like.

[0037] Further, device 204 may include an output interface 224 to communicate the results obtained from the fault detection module 222, for example, to a server. In one example, when the method is implemented at a server, the device 204 may communicate the current and voltage measurements to the server through the output interface 224. The output interface 224 may include a variety of computer-readable instructions-based interfaces and hardware interfaces that allow interaction with other communication, storage, and computing devices, such as network entities, web servers, databases, and external repositories, and peripheral devices. In one example, the fault detection parameters, current and voltage measurements, and the like may be viewed on a display connected to the output interface 224 or integrated with the device 204.

[0038] In operation, to detect a phase arcing fault in the shunt capacitor bank 202 connected in the power system 200, the processor 220 of the device 204 executes a fault detection module 222 to obtain voltage measurements and current measurements at a terminal of the shunt capacitor bank 202. In one example, the voltage measurements and current measurements are obtained in each phase at the terminal of the shunt capacitor bank 202. The voltage measurements and the current measurements may be obtained with one or more measurement equipment associated with the terminal as may be understood. Based on the voltage and current measurements, the processor 220 may compute an electrical parameter. In one example, the electrical parameter may be an active power. In another example, the electrical parameter be an impedance angle. The fault may be detected based on the computed active power, impedance angle, or both. In one example, the fault detected may be a phase arcing fault.

[0039] In one example, apparent power flow during phase arcing fault, which is a combination of active power and the reactive power, and arc resistance may be first calculated. In one example, the arc resistance during arcing may be considered to be zero. In another example, the arc resistance during arcing may be computed, as will be discussed later. For discussion purpose, a fault between phases A and B is considered as an example and the apparent power on occurrence of a fault may be calculated as explained below. The equations (1) and (2) depict the apparent power in phase A and phase B.

S _A = VA - 1A* (1)

S _B = V _B * r _B (2) where,

SA is the apparent power of phase A, and

SB is the apparent power of phase B.

VA is the voltage measured at phase A

IA is the current measured at phase A. VB is the voltage measured at phase B IB is the current measured at phase B.

Further, the phase angle between VA and IA may be denoted as ‘ 0a’ and the phase angle between VB and IB may be denoted as ‘0b’. A phase arcing fault between phase A and phase B at the m ^th fraction on a capacitor unit may be considered, where ‘m’ denotes the fault location. The values of IA and IB may be calculated by the processor 220 using superposition theorem, a method well known in the art, to give equations (3) and (4): where, m is the fault position, and

X is the reactance of each phase of the capacitor bank.

Further, on Substituting V _A = V < 0° and V _B = V < 120° , where V is the RMS value of phase to ground voltage and the la and Ib in equation 1 and 2 respectively, we get equations (5) and (6) as shown below,

Similarly, if a phase arcing fault between phase B and phase C is considered, the apparent power in phase B and phase C is calculated using equations (7) and (8) respectively, as shown below:

[0040] From the above equations it can be understood that during normal operation of the power system 200, i.e., when the value of m=l, the active power will be 0 and only reactive power, which may be computed using the expression (-V ² /X), flows into the power system 200. Unless there is internal resistance in the SCB, the SCB supplies only reactive power to the power system 200. During any fault, that is when the value of m is lesser than 1, an active power flow between the phases may be observed. Based on this active power flow, a predefined criterion may be set to detect the phase arcing faults. In one example, the predefined criterion may be stored in the memory 226 and the processor 220 may execute the fault detection module 222 to detect a phase arcing fault between the first one of the phases and the second one of the phases based on the predefined criteria.

[0041] An ideal capacitor bank does not consume any active power and supplies only reactive power to the power system 200. In one example, under practical conditions the SCB may consume negligible amount of active power due to contact resistance or due to leakage current through the capacitors. However, when the SCB has phase arcing fault, the amount of active power flowing through the SCB would no longer be negligible. The fault detection module 222 may compute, in one example, the active power flow during pre-fault conditions and on occurrence of a fault to detect the fault. In another example, the fault detection module 222 may compute the impedance angle during pre-fault conditions and on occurrence of a fault to detect the fault. In yet another example, the fault detection module 222 may compute both the active power flow and the impedance angle for fault detection. [0042] In one example method, based on each voltage and current measurement in each phase, the change in the active power flow may be computed by calculating a difference between two consecutive active power computations. In one example, the difference between a first and a second value of the active power computations may be denoted as ‘AP’. The value of AP may be computed for all three phases and verified with the predefined criterion as depicted in Table 3 to detect a phase arcing fault.

TABLE 3 : PREDEFINED CRITERION FOR FAULT DETECTION

[0043] As can be understood from the above table, when the absolute value of sum of the difference between the first and the second value of the active power computations of each of a first one of the phases and a second one of the phases is greater or equal to the difference between the first and the second value of the active power computations of a third one of the phases and the absolute values of the difference between the first and the second value of the active power computations of each of the first one of the phases and the second one of the phases is greater than a threshold value, the fault detection module 222 determines that a phase arcing fault is detected between the first one of the phases and the second one of the phases. The first one of the phases may be any one of A, B, and C phases, the second one of the phases may be a different one of A, B, and C phases, and the third one of the phases may be a third one of the A, B, and C phases. The threshold value may be set based on accuracy of the measurement equipment used.

[0044] Similarly, the fault detection module 222 may be configured to detect the fault based on an impedance angle. When the SCB supplies only reactive power to the system, the impedance angle is always close to 90 degrees under normal operation. Fig. 3 illustrates the locus of the impedance angle when a phase arcing fault occurs between phase A and phase B in accordance with the present subject matter. However, when a phase arcing fault occurs between the capacitor units of a capacitor bank, the impedance angle would no longer be 90 degrees. Continuing with the discussion of Fig. 2, the processor 220 may calculate the impedance angle based on equations (9) or (10) as shown below: 0 = ((< Vph) — (< Iph) or (9) where,

< Vph and < Iph are the phase angles of the voltage and current measurements respectively, and

P _ph and Q _Ph are the phase angles of the active power and the reactive power measured.

[0045] Based on each voltage and current measurement in each phase, the change in an impedance angle between fault and pre-fault conditions may be computed by calculating a difference between a first and a second value of the impedance angles. In one example, the difference between the first and the second value of the impedance angles may be denoted as ‘Ao’. The value of Ao may be computed for all three phases and verified with the predefined criterion as depicted in Table 4 to detect an internal arcing fault.

TABLE 4: PREDEFINED CRITERION FOR FAULT DETECTION

[0046] As can be understood from the above table, when the absolute value of sum of the difference between the first and the second value of the impedance angles of a first one of the phases and the difference between the first and the second value of the impedance angles of a second one of the phases is greater or equal to the difference between the first and the second value of the impedance angles of a third one of the phases, and the absolute values of the difference between the first and the second value of the impedance angles of each of the first one of the phases and the second one of the phases is greater than a threshold value, the fault detection module 222 determines that a phase arcing fault between the first one of the phases and the second one of the phases has been detected. The first one of the phases may be any one of A, B, and C phases, the second one of the phases may be a different one of A, B, and C phases, and the third one of the phases may be a third one of the A, B, and C phases. The threshold value may be set based on accuracy of the measurement equipment used. [0047] While the above computations may be performed considering the arcing resistance to be zero, arc faults are usually accompanied with some resistance and the Warrington formula may be used to formulate the arc resistance as discussed below, for performing the above computations. The arc resistance value may be derived from the Warrington formula as depicted in equation (11). where,

L is the length of the arc, which is the distance between the faulty racks of the phases A and B or phases B and C, and

I is the root mean square RMS value of current flowing through the arc Considering a phase arcing fault to have occurred between the phases AB or phases BC, the current flowing through the arc may be computed using equation (12) as shown below: where,

X is the capacitive reactance per phase

Further, on considering R^rc « (2m * (1 — m) * X) ² and substituting in equation (12) we get:

On substituting equation (13) in equation (11) we get:

Considering Q to be the rated MV AR of the double wye connected capacitor bank, where Q is depicted by the expression:

Further on substituting the above expression in equation (14) we get:

R _arc 28707.35

[0048] The computed arcing resistance can be then used for determining the reactance and computing the fault location as discussed above.

[0049] The present subject matter hence provides an efficient phase arcing fault detection in a shunt capacitor bank connected to a power system. The proposed fault determination technique can be implemented for detecting phase arcing faults between phases of an SCB within a short duration of time before the onset of a cascading failure of the capacitor units.

[0050] Fig. 4 illustrates a method for detecting a fault in a shunt capacitor bank, in accordance with an embodiment of the present subject matter. The order in which a method 400 is described is not intended to be construed as a limitation, and some of the described method blocks may be performed in a different order to implement the method 400 or an alternative method. Furthermore, the method 400 may be implemented in any suitable hardware, computer readable instructions, firmware, or combination thereof. For discussion, the method 400 is described with reference to the implementations illustrated in Fig. 2.

[0051] In the method 400 at block 402, voltage measurements and current measurements are obtained at a terminal of the shunt capacitor bank. The voltage measurements and current measurements are obtained in each phase at the terminal of the shunt capacitor bank. The voltage and current measurements are obtained with one or more measurement equipment associated with the terminal of the shunt capacitor bank. In one example, the voltage and current measurements are fed to the device 204.

[0052] At block 404, an electrical parameter is computed based on the voltage and current measurements. The electrical parameter corresponds to an impedance angle or an active power. The electrical parameter is computed for each new voltage and current measurements.

[0053] At block 406, a difference between a first and a second value of the electrical parameter may be calculated. In one example, the first and the second value of the electrical parameter are consecutive to each other. The difference between the first and the second value of the electrical parameter for each voltage and current measurement in each phase may be calculated and stored in the memory 226.

[0054] At block 408, the fault is detected based on the difference between the first and the second value of the electrical parameter. In one example, the detection of the fault may be based on a predefined criterion. In one example, the predefined criterion may be based on the difference between the first and the second value of the electrical parameter for each voltage and current measurement in each phase, and the predefined criteria may be stored in the memory 226.

[0055] In one example, the predefined criterion may be that when an absolute value of sum of the difference between the first and the second value of the electrical parameter of a first one of the phases and the difference between the first and the second value of the electrical parameter of a second one of the phases is greater than the difference between the first and the second value of the electrical parameter of a third one of the phases, and the absolute value of difference between the first and the second value of the electrical parameter of the first one of the phases and the second one of the phases is each greater than a respective threshold value a fault may be detected.

[0056] The respective threshold values for the predefined criteria may be set based on the accuracy of measurement equipment. Further, on detecting a fault in the SCB, the device 204 may employ a protection scheme to trip the SCB within a short duration of time to avoid cascading failure of capacitor units.

[0057] The above discussed methods can be used to detect phase arcing faults at even at lower units of capacitor banks and thereby avoid initiation of cascading failure of the SCB. Simulation results are provided below for a system with L= 471 mm, VL-L = 52kV and Q= lOMVAr with parameters as considered above in Table 1 and the simulation results are compared with those provided in Table 2. It will be understood that these simulations are provided merely as examples for validation of the present techniques and not as limitations.

EXAMPLE 1

[0058] In a first example, the technique of fault detection was tested for active power as the electrical parameter. Active power flow in different phases for phase arcing faults between phase A and phase B at different fault locations was tested.

[0059] Considering the arc resistance to be zero, the active power flow in different phases with phase A-phase B type phase arcing fault was simulated and has been tabulated in Table 5 as shown below:

TABLE 5: ACTIVE POWER FLOW IN DIFFERENT PHASES WITH PHASE A - PHASE B TYPE ARCING

FAULTS (HAVING RARC=0) AT DIFFERENT FAULT LOCATIONS. [0060] However, as arc faults are usually accompanied with some resistance, the real-life arc may be calculated according to equation (15) and the arc resistance and different fault positions may be computed. Table 6 depicts the arc-resistance at different fault positions having an arc length of 471mm, the system having a line-to-line voltage of 52kV and reactive power of lOMVAr.

TABLE 6: COMPUTATION OF ARC RESISTANCE AT DIFFERENT FAULT POSITIONS.

[0061] Further, the technique of fault detection was tested for active power flow in different phases for phase arcing faults between phase A and phase B at different fault locations with arc resistance as depicted in Table 6. The active power flow in different phases with phase A- phase B type arcing fault and having an arc resistance has been tabulated in Table 7 as shown below:

TABLE 7: ACTIVE POWER FLOW IN DIFFERENT PHASES WITH PHASE A- PHASE B ARCING FAULTS (HAVING RARC AS PER WARRINGTON FORMULA) AT DIFFERENT FAULT LOCATIONS. [0062] As can be observed from Table 5 and 7, for the phase A- phase B arc fault at different fault positions, the active power-based method with the predefined criteria |APA + APB| => APc && (| APA |> Pset) && (|APB | > Pset) helps to accurately detect the fault even at lower fault positions in contrast to Table 2. For this example, the threshold value Pset was set to 2%.

EXAMPLE 2

[0063] In a second example, the technique of fault detection was tested for impedance angle as the electrical parameter. Impedance angle in different phases for rack type faults between phase A and phase B at different fault locations was tested.

[0064] Considering the arc resistance to be zero, the impedance angle in different phases with phase A- phase B type phase arcing fault has been tabulated in Table 8 as shown below:

TABLE 8 : IMPEDANCE ANGLES FOR THE DIFFERENT PHASES WITH PHASE A- PHASE B TYPE ARCING FAULTS (HAVING RARC =0) AT DIFFERENT FAULT POSITIONS.

[0065] Fault detection was also simulated based on computed arc resistance as depicted in Table 6 above. Further, impedance angles for fault detection with arc resistance as depicted in Table 6 for different phases with phase A-phase B type arcing faults has been tabulated in Table 9 as shown below:

TABLE 9 : IMPEDANCE ANGLES FOR THE DIFFERENT PHASES WITH PHASE A- PHASE B TYPE ARCING FAULTS (HAVING RARC AS PER WARRINGTON FORMULA) AT DIFFERENT FAULT POSITIONS.

[0066] As can be observed from Table 8 and 9, for the phase A- phase B arc fault at different fault positions, the impedance angle-based method with the predefined criteria |AOA + AOB| => Aoc && (| AOA | > 0set) && (| AOB | > 0set) helps to accurately detect the fault even at lower fault positions in contrast to Table 2. For this example, the threshold value 0set was set to 1 degree.

[0067] On comparing the results of Examples 1 and 2 for phase arcing fault at different fault positions with the results of protection schemes based on the magnitude of voltages and current as shown in Table 2, it can be observed that when a fault occurs at the lower units of the capacitor bank (m =0.875) it can initiate a cascading failure when using overcurrent or overvoltage. However, the present subject matter can avoid cascading failure using the active power-based method, the impedance angle-based method, or both for fault detection.

[0068] Thus, the methods and devices of the present subject matter detect phase arcing faults in a shunt capacitor bank within a short interval of time and can be reliably performed to avoid cascading failures of capacitor units and subsequent damages to the power system.