Inventors:

Bruce A. Block

Paul B. Fischer

Sansaptak Dasgupta

BACKGROUND

[0001] In the fields of electronic communication and power management, various components can be implemented using solid-state devices, including transistors and capacitors, for example. For instance, such solid-state devices can be formed on an integrated circuit and be used for radio frequency (RF) communication applications, such as for RF front end applications. Film-bulk-acoustic-resonators (FBAR) can provide RF filters that can achieve narrow bandwidth discrimination while minimizing insertion loss. Typical RF front- end technologies employing second generation (2G), third generation (3G), fourth generation (4G), and long-term evolution (LTE) wireless standards utilize multiple RF filters, each with one or more constituent FBARs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 illustrates one embodiment of an FBAR device.

[0003] Figure 2 illustrates one embodiment of an epitaxial layer grown on a substrate.

[0004] Figure 3 illustrates an embodiment of an electrically conductive layer formed on the embodiment of Figure 2.

[0005] Figure 4 illustrates an embodiment of an acoustic isolation region.

[0006] Figure 5 illustrates the embodiment of Figure 3 positioned to be joined to the acoustic isolation region of Figure 5.

[0007] Figure 6 illustrates an embodiment of a device formed by joining the devices of Figures 4 and 5.

[0008] Figure 7 illustrates an embodiment of the device of Figure 6 after removing a substrate layer.

[0009] Figure 8 illustrates an embodiment that includes an electrically conductive layer formed on top of the epitaxial layer of the embodiment shown in Figure 7.

[0010] Figure 9 illustrates an embodiment of an FBAR device that includes an air cavity in the acoustic isolation region.

[0011] Figure 10 illustrates another embodiment of an FBAR device that includes an air cavity in the acoustic isolation region. [0012] Figure 11 illustrates a process embodiment in which an acoustic isolation region is formed in a silicon substrate of an FBAR device.

[0013] Figure 12 illustrates a process embodiment in which an acoustic isolation region is formed in both the substrate and a conductive layer of an FBAR device.

[0014] Figure 13 illustrates a process embodiment of constructing an FBAR device in which an acoustic isolation region is formed in an intermediate layer between the substrate of the FBAR device and a piezoelectric layer.

[0015] Figure 14 illustrates a process embodiment of constructing an FBAR device in which a selectively etchable material is removed from a cavity in the substrate to form an acoustic isolation region.

[0016] Figure 15 illustrates a process embodiment in which an acoustic isolation region is formed in a layer adhered to a piezoelectric layer.

[0017] Figure 16 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with an embodiment of the present disclosure.

[0018] These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

[0019] Techniques are disclosed for fabricating an integrated circuit including one or more film bulk acoustic resonator (FBAR) devices. In accordance with some embodiments, a given FBAR device may include a highly crystalline structure of an epitaxial piezoelectric material, such as aluminum nitride (A1N), gallium nitride (GaN) and any one, or combination, of these and other III-N semiconductor materials. In accordance with some embodiments, the epitaxial layer may be formed via an epitaxial deposition process, allowing for precise control over film crystallinity and thicknesses. For example, the epitaxial layer can exhibit an XRD FWHM of less than 0.5 degrees compared to the 1 to 4 degrees that is typical with sputtered III-N semiconductor materials. Many embodiments of the FBARs described herein can provide RF filters that are capable of delivering superior performance in a variety of communication devices. These devices include those that receive or transmit an RF signal, for example, mobile phones, computers, vehicles, aircraft and radios. In one aspect, the disclosed resonators can use highly crystalline epitaxial films to provide improved performance over FBARs that use polycrystalline materials, such as those formed using sputtering techniques. These improvements can include, for example, increased bandwidth, lower insertion loss and a higher Q value. Numerous configurations and variations will be apparent in light of this disclosure.

General Overview

[0020] Film bulk acoustic resonators (FBARs) have been used in RF filters and provide advantages over surface-acoustic-wave (SAW) filters. These advantages include reduced interference from nearby radio bands as well as reduced insertion losses. RF filters can be most effective when they let the selected band pass while reducing or eliminating the passage of adjacent unwanted frequencies. This can result in high signal strength and minimal interference, thus improving communication and reducing power requirements. Currently used Ill-Nitride (III-N) FBAR devices rely on sputtered III-N materials that result in polycrystalline layers that include a high concentration of crystal defects. The sputtered layers also exhibit inconsistent thicknesses and rougher surfaces. Described herein are methods that use III-N materials of higher crystallinity, even single crystal materials, to provide low-defect, highly crystalline piezoelectric layers that result in RF filters that allow more useful energy to be passed while minimizing losses of that energy. This results in higher Q values, providing, for example, longer battery life and more bars of reception. In one set of embodiments, these highly crystalline III-N materials are formed by epitaxial growth on an appropriate substrate, such as a 300 mm silicon wafer.

[0021] The piezoelectric layers may be used in a variety of FBAR architectures including those with air gaps, stacked crystal filters and coupled resonator filters. FBAR topologies of different embodiments include, for example, trapezoidal, bridge and mixed type. In some instances, the use of techniques described herein may result in III-N semiconductor structures including higher quality piezoelectric layer(s) that provide for higher electromechanical coupling and Q-factor RF devices. As will be appreciated in light of this disclosure, these improvements, in turn, may realize bandwidth increases, reductions in signal losses, and increases in the ability of the host RF filter to reject out-of-band signals. In some cases, FBAR devices fabricated via the disclosed techniques may be utilized in RF filters and other RF devices that may be used in communication technologies that employ any one, or combination, of second generation (2G), third generation (3G), fourth generation (4G), fifth generation (5G), or long-term evolution (LTE) wireless standards, among others. In some instances, use of such devices may realize lower losses and higher signal integrity, from which host wireless communication platforms may benefit.

[0022] In accordance with some embodiments, structures provided as variously described herein may be configured for use, for example, in RF front-end modules in computing devices, mobile or otherwise, and various communication systems, although numerous other applications will be apparent in light of this disclosure. In accordance with some embodiments, structures provided as variously described herein may be configured for use, for example, in base stations, cellular communication towers, and the like. In accordance with some embodiments, use of the disclosed techniques and devices may be detected, for example, by any one, or combination, of x-ray diffraction (XRD), scanning electron microscopy (SEM), transmission electron microscopy (TEM), chemical composition analysis, energy-dispersive X-ray (EDX) spectroscopy, electrocharacterization, and secondary ion mass spectrometry (SFMS) of a given IC or other semiconductor structure having a plurality of resonator devices configured as variously described herein. As used herein, a highly crystallized III-N material is a III-N material that exhibits an XRD FWHM of less than 1.0 degree.

Architecture and Methodology

[0023] Figure 1 provides a cross-sectional schematic view of one embodiment of an FBAR device made using one or more of the methods described herein. Semiconductor substrate 102 includes acoustic isolation region 204 which, as illustrated, includes air gap 104 that has been etched or otherwise formed in the substrate. The upper surface of substrate 102 and air gap 104 are covered with electrode layer 108 which can be a conductive material such as a metal. Second electrode layer 110 can be of the same material as electrode layer 108. Highly crystalline piezoelectric III-N layer 106 is between second electrode layer 110 and electrode layer 108, however another conductive layer, layer 112 is between highly crystallized piezoelectric material 106 and electrode layer 108. Conductive layer 112 can be of the same or different material as electrode 108, as will become evident given the description below.

[0024] As shown, Figures 2-9 illustrate a process flow for forming various embodiments of an FBAR in accordance with the present disclosure. This process flow may be used, for example, to fabricate an integrated circuit including one or more FBAR devices comprised of one or more highly crystalline piezoelectric III-N semiconductor materials, in accordance with some embodiments. These III-N materials can include, for example, epitaxially grown gallium nitride (GaN), aluminum nitride (A1N), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN). In various embodiments, the epitaxially grown III-N materials can, for example, exhibit XRD FWHM numbers of less than 3 degrees, less than 2 degrees, less than 1 degree, less than 0.5 degree or less than 0.4 degree.

[0025] The process flow may begin as in Figure 2, which illustrates a cross-sectional view of one embodiment of an epitaxial layer 106 of A1N that has been grown on crystalline donor substrate 202. Different embodiments can include any of the other III-N materials and combinations thereof. Crystalline substrate 202, which may be a donor substrate, can be selected for its crystal lattice and may be, for example, silicon or silicon carbide. Different crystallographic planes can be used as a surface for growth and include, for example, the [111], [100] or [110] directions. In the embodiment shown, a highly crystalline layer of aluminum nitride has been epitaxially grown on a silicon [111] substrate. III-N semiconductor layer 106 may be formed via any suitable standard, custom, or proprietary techniques, as will be apparent in light of this disclosure. The process can be any method that results in a highly crystalline (FWHM of less than 1.0 degree) semiconductor layer. These processes include those that grow highly crystalline materials via epitaxial growth and methods of deposition include, for example, chemical vapor deposition (CVD) such as metal- organic CVD (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or combinations thereof. In many embodiments, the highly crystalline III-N layer 106 is a piezoelectric material and can exhibit a wurtzite crystalline structure. The thickness (z) of highly crystalline layer 106 can be controlled to any thickness that is appropriate for the final device and may be, for example, between 0.3 and 6.0 μπι, 0.5 and 5.0 μπι, 1.0 and 4.0 μπι. In the same and other embodiments, the thickness may be less than 5.0 μπι, less than 4.0 μπι, less than 3.0 μπι or less than 2.0 μπι. In the same or other embodiments, the thickness may be greater than 0.1 μπι, greater than 0.3 μπι, greater than 0.5 μπι or greater than 1.0 μπι. Compared to a sputtered III-N material, the highly crystalline material can have a smoother surface, can be less textured and often does not require polishing or planarization prior to IC fabrication.

[0026] The process can continue in Figure 3 which illustrates conductive electrode layer 112 formed on highly crystalline A1N layer 106. Electrode layer 112 may be comprised of any of a wide range of electrically conductive materials. For instance, in some cases, electrode layer 112 may be comprised of any one, or any combination, of electrically conductive refractory materials, including oxides such as , indium tin oxide (ITO) and indium zinc oxide (IZO), metals such as tungsten (W), molybdenum (Mo) and titanium (Ti), and nitrides such as tantalum nitride (TaN), titanium nitride (TiN), or an alloy of any thereof, to name a few. In some cases, electrode layer 112 may include a dopant.

[0027] Electrode layer 112 may be formed via any suitable standard, custom, or proprietary techniques, as will be apparent in light of this disclosure. In accordance with some embodiments, electrode layer 112 may be formed via any one, or any combination, of a physical vapor deposition (PVD) process (e.g., sputtering), a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process, among others. The dimensions (e.g., z-thickness in the z-direction) of electrode layer 112 may be customized, as desired for a given target application or end-use. In some cases, electrode layer 112 may have a z-thickness in the range of about 200 nm or less (e.g., about 150 nm or less, about 100 nm or less, about 50 nm or less, or any other sub-range in the range of about 200 nm or less). In other embodiments, electrode layer 112 may have a z thickness of, for example, 50 to 300 nm, 100 to 250 nm, or 100 to 200 nm. Other suitable materials, formation techniques, and dimensions for electrode layer 112 will depend on a given application and will be apparent in light of this disclosure.

[0028] As can be seen in Figure 4, device 300 may include a semiconductor substrate 102, which may have any of a wide range of configurations. For instance, semiconductor substrate 102 may be configured as any one, or combination, of a bulk semiconductor substrate, a silicon-on-insulator (SOI) structure or other semiconductor-on-insulator structure (XOI, where X represents a semiconductor material, such as silicon, germanium, germanium- enriched silicon, and so forth), a semiconductor wafer, and a multi-layered semiconductor structure. In some instances, semiconductor substrate 102 may be configured as a silicon-on- sapphire (SOS) structure.

[0029] Semiconductor substrate 102 may be comprised of any of a wide range of semiconductor materials. For instance, in some cases, semiconductor substrate 102 may be comprised of any one, or combination, of Group IV semiconductor materials, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some instances, semiconductor substrate 102 may be comprised of Si having a crystallographic orientation of [111], [110], or [100], optionally with an offcut towards [110] in the range of about 1-10° (e.g., about 1-4°, about 4-7°, about 7-10°, or any other sub-range in the range of about 1-10°). In some other cases, semiconductor substrate 102 may be comprised of any one, or combination, of Group III-V compound semiconductor materials, such as gallium arsenide (GaAs) or indium phosphide (InP), among others. In some still other cases, semiconductor substrate 102 may be comprised of silicon carbide (SiC) or sapphire (α-Α1 ₂ 0 ₃ ). In some instances, the particular material composition of semiconductor substrate 102 may be chosen, at least in part, based on a target electrical resistivity range suitable for one or more resonator devices formed there over, as described herein. In some cases, semiconductor substrate 102 may have an electrical resistivity of about 1,000 Ω-cm or greater (e.g., about 1,200 Ω-cm or greater, about 1,500 Ω-cm or greater, and so forth).

[0030] It should be noted that semiconductor substrate 102 is not intended to be limited only to configurations and implementations as a substrate for a given host architecture, as in accordance with some other embodiments, semiconductor substrate 102 may be configured or otherwise implemented as an intermediate layer disposed in a given host architecture. Other suitable materials, configurations, and resistivity ranges for semiconductor substrate 102 will depend on a given application and will be apparent in light of this disclosure.

[0031] Device 300 can include one or more acoustic isolation regions 204, with one embodiment being illustrated in Figure 4 that includes dielectric Bragg reflector 132, metal Bragg reflector 134, dielectric Bragg reflector 136 and metal Bragg reflector 138. Any appropriate acoustic isolation region can be used including, for example, free standing cavities, stacked crystals, coupled resonators and reflectors including Bragg reflectors. As shown, device 300 includes two pair of metal/dielectric Bragg reflectors. One, two, three or more pair of reflectors may be used in various embodiments. The reflectors can provide acoustic isolation of the FBAR from the substrate by creating boundary conditions that lead to constructive and destructive interference. In many cases, the metal and the dielectric materials have a large ratio of respective acoustic impedances. For instance, the ratio may be greater than 5: 1, 10: 1 or 20: 1. In some embodiments, the reflectors can withstand high temperatures, exhibit low interfacial roughness and exhibit good adhesion. In one set of embodiments, the metal/dielectric Bragg reflectors are tungsten and silicon oxide (W/Si0 ₂ ) which have been found to provide a wide useful reflection band. Other materials that can be used for Bragg reflectors include, for example, Al, Ti, Au, Mo, Nb, Ni, Pt, Ta, W, Si0 ₂ , A1N, Hf0 ₂ , MgO, Ti0 ₂ and Si ₃ N ₄ .

[0032] In some embodiments, Bragg reflectors 132, 134, 136 and 138 can be formed using thin film deposit techniques. These techniques include, for instance, physical vapor deposition (PVD) (e.g., sputtering) and chemical vapor deposition (CVD). In some embodiments, the Bragg reflectors can be quarter-wave layers, and in other embodiments the layers can be formed at predetermined nominal thicknesses selected to provide acoustic isolation at selected wavelengths. Electrode layer 108 can comprise a conductive material such as a metal or an oxide and may be the same or a different material than that of electrode layer 112, described above. It need not, but may, have composition and dimensions that are similar to electrode layer 112. It may also be produced using the same techniques as described above for electrode layer 112.

[0033] In Figure 5, donor substrate 202, A1N layer 106, and electrode layer 112 are flipped over to prepare for mating with device 300. Donor substrate 202 can optionally be removed prior to mating with device 300. The substrate can be removed through grinding or etching, and any residual portions remaining can be selectively etched. For instance, if donor substrate 202 is a Si substrate or a Si-on-insulator (SOI) of Si-on-sapphire (SOS) substrate, then an etchant comprised of potassium hydroxide (KOH) or tetra-methyl ammonium hydroxide (TMAH) ((CH ₃ ) ₄ NOH) may be utilized in removing Si material from the epitaxial A1N 106, in accordance with some embodiments. The exposed surface of electrode layer 112 can be improved by removing imperfections, for example using chemical-mechanical planarization (CMP) techniques.

[0034] In some embodiments, highly crystalline epitaxial layer 106 can be joined to device 300 as shown in Figures 6A and 6B. As described above, donor substrate 202 can be removed before or after joining electrode layer 112 to electrode layer 108. Prior to joining, one or both of layers 112 and 108 can be cleaned and/or planarized using, for example, solvents or CMP. Recall that layers 112 and 108 may comprise the same or different conductive materials and can be, for example, metals or oxides. In various embodiments the electrode layers may have the same or different shapes in the x-y plane. The exposed surfaces of each of layers 112 and 108 in Figure 6A can be brought together and will adhere via, for instance, van der Waals forces. In some embodiments, such as illustrated in Figure 6B, steps can be taken to further fix the layers together. These steps may include, for example, CVD oxide treatment, in particular when layer 108 is an oxide and not a metal. The embodiment of Figure 6B includes an additional layer, oxide layer 116. Layer 116 can be applied after oxide electrode 108a is deposited and can help join electrode layer 108a to electrode layer 112. In other embodiments, oxide layer 116 can be applied to electrode layer 112 on structure 200 before structures 200 and 300 are joined. In further embodiments, layer 108 may be an oxide layer itself, helping to adhere electrode 112 to substrate 102 or the stack of Bragg reflectors 300. In some embodiments, the materials can be annealed to promote bonding of the adjoining layers. In one embodiment for instance, after the formation of oxide layer 116, annealing can drive the formation of Si0 ₂ on the surface, accompanied by the liberation of water. In some embodiments, layer 112, layer 108, or both can be connected to conductive traces. If donor substrate 202 has not yet been removed, as shown in Figure 6, in some embodiments it can be removed from epitaxial layer 106 using, for example, the grinding, polishing and/or etching techniques described above. Figure 7 illustrates an embodiment of the device after removal of donor substrate 202.

[0035] As shown in Figure 8, embodiments can include the addition of electrode layer 114. Electrode layer 114 can comprise a conductive material such as a metal and may comprise the same or different materials as electrode layers 112 and 108. Electrode layer 114 can be formed using the methods described herein, including deposition processes such as chemical and physical deposition techniques. These include, for example, physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes. Electrode layer 114 can have dimensions that are the same, similar to, or different from electrode layers 108 and 112. Post- deposition processes can be used to refine electrode layer 114. For example, grinding, etching and planarization techniques can be used to reduce the thickness of the layer and to remove surface imperfections. Electrode layer 114 can be conductively joined with other components using, for instance, conductive traces.

[0036] Figure 9 illustrates an alternative embodiment of an FBAR that includes a free standing cavity and does not include the Bragg reflectors of the embodiment of Figure 8. Unlike the FBAR of Figure 1, the free standing cavity is not formed in the substrate, but in a conductive layer 152 which can be comprised of one or more metals. The composition of conductive layer 152 can be the same, but need not be, as that of any of electrode layers 114, 112 and 108. For example, in some embodiments it can be a metal such as tungsten or molybdenum. In one set of embodiments, cavity 154 is formed prior to the deposition of electrode layer 108. In one particular embodiment, conductive layer 152 is deposited on substrate 202 using a physical or chemical deposition method. Cavity 154 can be selectively etched from conductive layer 152. Etching may include dry or wet etching techniques, or both, and can be selected to remove portions of conductive layer 152 without attacking substrate 202. As shown, cavity 154 extends throughout the z thickness of layer 152, but in some embodiments the cavity can extend partially through conductive layer 152. In other embodiments, cavity 154 can be formed during the deposition process by selectively masking or depositing sacrificial material in the region of cavity 154. In some embodiments, electrode layer 108 can be formed on conductive layer 152 after which the sacrificial material can be removed to form cavity 154. Layers 112 and 106 can then be added to the stack, for example, using the techniques described above in reference to Figures 6 and 7. In further embodiments, electrode layer 114 is formed as described above in reference to Figure 8.

[0037] In another set of embodiments, the FBAR of Figure 10 can be formed using methods similar to those of Figure 9, without the inclusion of electrode layer 108. For example, after the formation of cavity 154, electrode layer 112 and highly crystalline layer 106 (and optionally donor substrate 202) can be bonded directly to conductive layer 152. The facing surfaces of conductive layer 152 and electrode layer 112 can be treated, for example by planarization, to render them more amenable to joining. The surfaces can then be joined to together and adhered via van der Waals forces or other adhesion techniques. In some embodiments, the device can be annealed to further secure the adhesion of layers 112 and 152. In further embodiments, electrode layer 114 can be deposited on highly crystalline piezo layer 106 to form a top electrode. The result can be an air gap FBAR with the gap formed in a metal or other conductive layer as opposed to formation in the substrate, as illustrated in Figure 1.

[0038] Figure 11 illustrates a process embodiment in which an air gap FBAR can be constructed by forming an acoustic isolation region 204 directly in substrate 102. Process 11a includes forming cavity 154 in substrate 102 using methods such as dry or wet etching. In some cases, oxide layer 160 can be allowed to naturally form on the upper surface of substrate 102. In other instances, oxide layer 160 can be deposited on the surface, using methods such as CVD. Process l ib includes adhering substrate 102 to a structure that is analogous to structure 200 of Figure 3 and includes high crystallinity layer 106, donor substrate 202 and electrode 108. In cases where electrode 108 is comprised of a conductive oxide, oxide layer 160 can aid in adhering structure 200 to substrate 102. An optional annealing process can drive the formation of Si0 ₂ to further adhere substrate 102 to electrode 108. Process 11c can include the removal of donor layer 202 and the deposition of electrode layer 114 to produce FBAR 1100 that includes acoustic isolation region 204. Note that in other cases, donor layer 202 can be removed prior to attaching highly crystalline layer 106 to substrate 102. Similarly, electrode layer 114 can be deposited prior to attaching highly crystalline layer 106 to substrate 102. In various embodiments, acoustic isolation region 204 can be an air gap or a stack of reflectors such as Bragg reflectors.

[0039] Figure 12 illustrates a process embodiment in which an air gap FBAR is produced by forming cavity 154 in both substrate 102 and conductive layer 170. The process starts with structure 1200a that includes conductive layer 170 that has been deposited on planar substrate 102. Conductive layer 170 can be, for example, a metal, an oxide, or a metal layer on an oxide layer and can be deposited using methods such as CVD or PVD. Process 12a includes forming a cavity in substrate 102 and conductive layer 170 to produce structure 1200b. Conductive layer 170 and substrate 102 can be wet or dry etched to produce cavity 154. Portions of the conductive layer material and portions of the substrate material can be removed in the process. Each of these materials may be removed, in some embodiments, by the same or a different etchant and procedure. In process 12b, a structure including highly crystalline material 106, conductive layer 108 and donor substrate 202 are provided as in the example of Figure 3, above. This structure is combined with structure 1200b to produce structure 1200c. Conductive layers 108 and 170 can be adhered using metal bonding or oxide bonding in various embodiments. In process 12c, FBAR 1200d is produced by removing donor substrate 202, for example, by etching, and depositing conductive layer on the exposed surface of highly crystalline material 106, in this case epitaxial AIN.

[0040] Figure 13 illustrates a process embodiment in which an acoustic isolation region is formed not in substrate 102 (Si) but in conductive layer 172 that can be, for example, a metal, an oxide or a metal on oxide. Conductive layer 172 is deposited on or otherwise attached to substrate 102 using, for example, the CVD or PVD methods described herein to form structure 1300a. Process 13a includes forming cavity 154 in conductive layer 172 to produce structure 1300b. Cavity 154 can be exclusively in conductive layer 172 and may extend through all or a portion of the thickness of conductive layer 172. In the embodiment shown, cavity 154 does not extend into substrate 102. Cavity 154 can be formed, for example, using wet or dry etching processes. Process 13b includes, in this embodiment, adhering epitaxial AIN layer 106 to structure 1300b to produce structure 1300c. Conductive layers 108 and 172 can be joined together using, for example, metal -metal bonding or oxide bonding, to form structure 1300c. Although not the case in all embodiments, as shown, cavity 154 is surrounded completely by conductive material, either layer 172 or layer 108. Process 13c includes removing donor substrate 202 and adding electrode layer 114 to produce FBAR 1300d. Note that in other embodiments, acoustic isolation region 204 can comprise other isolation structures, such as Bragg reflectors.

[0041] Figure 14 illustrates a process embodiment in which cavity 154 is filled with selectively etchable material 144. Selectively etchable material 144 can be, for example, Si0 ₂ . This process can be combined with any of the others described herein to provide an alternative process where the cavity is protected during production. Material is removed from substrate 102, which can be, for example, Si, to produce cavity 154. Process 14a can include filling the cavity with a selectively etchable material such as Si0 ₂ . Si0 ₂ or other selectively etchable material can be deposited, for example, using plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or ion beam deposition (IBD). Other selectively etchable materials can include, for example, nitrides including SiN, SiCN, or amorphous materials such as amorphous Si, organic polymers, and thermally decomposable polymers.

[0042] After etchable material 144 has been deposited in cavity 154, the upper surface of substrate 102 and etchable material 144 can be prepared by, for example, CMP. Next, in process 14c, conductive electrode layer 108 is deposited on both of etchable material 144 and substrate 102. Alternatively, a highly crystalline layer such as epitaxial A1N layer 106, together with conductive electrode layer 108, is adhered to the substrate using the methods described herein, such as oxide bonding. Structure 1400d is provided in both cross-sectional and plan view (bottom). Looking at plan view 1400d, highly crystalline epitaxial material 106 is on top of conductive electrode 108 which in turn is seated on substrate 102, in this case Si. Dotted line 154 represents the location, now covered, of cavity 154 which is filled with selectively etchable material 144, in this case Si0 ₂ . Release holes 156a and 156b are formed in conductive electrode layer 108 and provide communication with etchable material 144. In some embodiments, a wet or dry etchant is provided and accesses etchable material through release holes 156a and 156b to remove etchable material 144 from cavity 154. Other removal techniques, depending on the specific etchable material, can include, for example, vaporization or combustion. This removal process empties, or mostly empties, cavity 154 and provides an air gap for the FBAR. An additional conductive electrode layer can be deposited on highly crystalline material 106 before or after removal of etchable material 144.

[0043] Figure 15 illustrates a process embodiment where an FBAR can be constructed by forming an acoustic isolation region on a highly crystalline piezoelectric layer in contrast to other embodiments that form an acoustic isolation region on a substrate, such as a silicon wafer. Structure 1500a in Figure 15 includes piezoelectric layer 106 that can been epitaxially grown on donor substrate 202. Conductive layer 108 can function as an electrode and can be deposited on piezoelectric layer 106 using the methods described herein, including PVD and CVD. Acoustic isolation layer 303 can be deposited on conductive layer 108 and can comprise, for example, a metal or an insulator. In some embodiments, layers 303 and 108 can be the same material and can be deposited as a single layer. Embodiments similar or identical to that of structure 1500b can be produced by etching of layer 303 to produce cavity 154. Structure 1500b can then be rotated 180° so that cavity 154 is facing downwards, and structure 1500b and be joined to structure 1500c, or similar, to produce structure 1500d where air gap 154 is trapped between layers 108 and 112. Structures 1500b and 1500c can be adhered to each other using, for example, metal-metal bonding or oxide bonding techniques. Structure 1500e illustrates an FBAR device after donor substrate 202 has been removed and replaced with conductive electrode layer 114. In alternative embodiments, this removal/replacement can take place prior to joining structures 1500b and 1500c together.

[0044] As discussed herein, the various constituent layers of IC 100 may have any of a wide range of thicknesses (e.g., z-thicknesses in the z-direction, x-thicknesses in the x- direction, or other designated thickness), as desired for a given target application or end-use. In some instances, a given layer may be provided as a monolayer over an underlying topography. For a given FBAR device configured as described herein, in some cases, a given constituent layer thereof may have a substantially uniform thickness over an underlying topography. In some instances, a given constituent layer may be provided as a substantially conformal layer over an underlying topography. In other instances, a given constituent layer may be provided with a non-uniform or otherwise varying thickness over an underlying topography. For example, in some cases, a first portion of a given layer may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range. In some instances, a given layer may have first and second portions having average thicknesses that are different from one another by about 20% or less, about 15% or less, about 10% or less, or about 5% or less. Numerous configurations and variations will be apparent in light of this disclosure.

[0045] Furthermore, as discussed herein, the various constituent layers of an FBAR device may be disposed over one or more other constituent layers. In some cases, a first constituent layer may be disposed directly on a second constituent layer with no layers intervening. In some other cases, one or more intervening layers may be disposed between a first constituent layer and a second constituent layer underlying. In a more general sense, a given constituent layer may be disposed superjacent to another given constituent layer, optionally with one or more intervening layers, in accordance with some embodiments.

Example System

[0046] Figure 16 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc. Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

[0047] The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0048] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0049] The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

[0050] In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a transceiver, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

[0051] The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

[0052] Example 1 is film bulk acoustic resonator (FBAR) device including a first electrically conductive layer, a second electrically conductive layer, a highly crystalline piezoelectric layer between the first and second electrically conductive layers, the piezoelectric layer having a crystallinity of less than 1.0 degree FWHM by x-ray diffraction, and an acoustic isolation region separated from the piezoelectric layer by at least the first electrically conductive layer.

[0053] Example 2 includes the subject matter of Example 1 wherein the highly crystalline piezoelectric layer includes a Ill-Nitride material.

[0054] Example 3 includes the subject matter of Example 1 or 2 wherein the highly crystalline piezoelectric layer includes at least one material selected from A1N, GaN and InN.

[0055] Example 4 includes the subject matter of any of the preceding Examples wherein the highly crystalline piezoelectric layer includes A1N.

[0056] Example 5 includes the subject matter of any of the preceding Examples wherein the highly crystalline piezoelectric layer has an XRD FWHM peak of less than 0.5 degree.

[0057] Example 6 includes the subject matter of any of the preceding Examples wherein the highly crystalline piezoelectric layer has an XRD FWHM peak of less than 0.4 degree.

[0058] Example 7 includes the subject matter of any of the preceding Examples wherein the highly crystalline piezoelectric layer includes a single crystal.

[0059] Example 8 includes the subject matter of any of the preceding Examples wherein the highly crystalline piezoelectric layer is formed by epitaxial growth.

[0060] Example 9 includes the subject matter of any of the preceding Examples wherein at least one of the first and second conductive layers includes a metal. [0061] Example 10 includes the subject matter of any of the preceding Examples further including a bulk silicon substrate.

[0062] Example 11 includes the subject matter of any of the preceding Examples wherein the acoustic isolation region includes an air gap or a Bragg reflector.

[0063] Example 12 includes the subject matter of any of the preceding Examples wherein the acoustic isolation region includes a plurality of Bragg reflectors.

[0064] Example 13 includes the subject matter of any of the preceding Examples wherein the acoustic isolation region is defined by a conductive layer.

[0065] Example 14 includes the subject matter of any of the preceding Examples wherein the highly crystalline piezoelectric layer exhibits a wurtzite structure.

[0066] Example 15 includes the subject matter of any of the preceding Examples wherein the acoustic isolation region is defined by a non-conductive layer.

[0067] Example 16 includes the subject matter of any of the preceding Examples wherein the acoustic isolation region is defined by at least two layers including an electrode layer and a substrate layer.

[0068] Example 17 includes the subject matter of any of the preceding Examples including a third electrically conductive layer, the third electrically conductive layer in contact with a silicon substrate wherein the third electrically conductive layer defines an air gap.

[0069] Example 18 is a radio frequency (RF) filter device including the film bulk acoustic resonator device of any of the preceding Examples.

[0070] Example 19 is a computing system including the film bulk acoustic resonator device of any of the preceding Examples.

[0071] Example 20 is a mobile phone including the film bulk acoustic resonator device of any of the preceding Examples.

[0072] Example 21 is a method of making a film bulk acoustic resonator (FBAR), the method including epitaxially growing a Ill-Nitride piezoelectric layer on a first substrate, forming a first conductive layer, joining a first surface of the Ill-Nitride piezoelectric layer to a second substrate via the first conductive layer to form an acoustic isolation region, the first conductive layer positioned between the Ill-Nitride piezoelectric layer and the second substrate, and forming a second conductive layer on a second surface of the Ill-Nitride piezoelectric layer.

[0073] Example 22 includes the subject matter of Example 21 wherein the acoustic isolation region includes a stack of Bragg reflectors. [0074] Example 23 includes the subject matter of Example 21 further including forming the acoustic isolation region by forming an air gap or Bragg reflectors in the second substrate, in an insulative layer, or in the first conductive layer.

[0075] Example 24 includes the subject matter of any of Examples 21-23 wherein the first conductive layer is formed on one of the III-Nitride piezoelectric layer and the second substrate.

[0076] Example 25 includes the subject matter of any of Examples 21-24 wherein the acoustic isolation region is formed by etching a selectively etchable material out of a cavity in the second substrate.

[0077] Example 26 includes the subject matter of any of Examples 21-25 wherein the III- Nitride piezoelectric layer includes ΑΓΝ or GaN.

[0078] Example 27 includes the subject matter of any of Examples 21-26 wherein the first conductive layer is formed on a surface of the III-Nitride piezoelectric layer as grown without first polishing or planarizing the surface of the III-Nitride piezoelectric layer.

[0079] Example 28 includes the subject matter of any of Examples 21-27 wherein the first and second conductive layers each include a metal or an oxide.

[0080] Example 29 includes the subject matter of any of Examples 21-28 wherein the III- Nitride piezoelectric layer exhibits an x-ray diffraction FWHM of less than 1.0 degree, less than 0.5 degree or less than 0.4 degree.

[0081] Example 30 includes the subject matter of any of Examples 21-29 wherein at least one of the first and second substrates includes silicon or silicon carbide.

[0082] Example 31 includes the subject matter of any of Examples 21-30 further including joining the first surface of the III-Nitride piezoelectric layer to the second substrate prior to removing the first substrate from the piezoelectric layer.

[0083] Example 32 includes the subject matter of any of Examples 21-30 further including joining the first surface of the III-Nitride piezoelectric layer to the second substrate after removing the first substrate from the piezoelectric layer.

[0084] Example 33 includes the subject matter of any of Examples 21-30 wherein at least one of the first and second substrates has a [111], [100] or [110] orientation. In some such cases, the first substrate has a [111], [100] or [110] orientation.

[0085] Example 34 includes the subject matter of any of Examples 21-33 wherein the first conductive layer is formed on a surface of the III-Nitride piezoelectric layer.

[0086] Example 35 includes the subject matter of any of Examples 21-33 wherein the first conductive layer is formed on the second substrate. [0087] Example 36 includes the subject matter of any of Examples 21-35 wherein the first conductive layer is joined to the second conductive layer.

[0088] Example 37 includes the subject matter of any of Examples 21-36 further including etching a cavity in the second substrate.

[0089] Example 38 includes the subject matter of any of Examples 21-37 wherein the acoustic isolation region includes a cavity, stacked crystals, coupled resonators or Bragg reflectors.

[0090] Example 39 includes the subject matter of any of Examples 21-38 further including depositing alternating layers of metal and dielectric materials to form a series of Bragg reflectors.

[0091] Example 40 includes the subject matter of Example 39 wherein the metal layers include tungsten and the dielectric layers include silicon oxide.

[0092] Example 41 includes the subject matter of any of Examples 21-39 wherein joining a first surface of the III-Nitride piezoelectric layer to a second substrate via the first conductive layer includes using a metal/metal bond or an oxide bond.

[0093] The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.