Title:
FERROELECTRIC FIELD-EFFECT TRANSISTORS FOR 3D MEMORY ARRAYS AND METHODS OF MANUFACTURING THE SAME
Document Type and Number:
WIPO Patent Application WO/2019/139622
Kind Code:
A1
Abstract:
Methods, apparatus, systems and articles of manufacture are disclosed for a gate all around ferroelectric material field-effect transistor. Examples include a ferroelectric memory device that includes a semiconductor substrate, a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate, a ferroelectric gate insulator coating the semiconductor rod and a gate conductor adjacent the semiconductor rod, the ferroelectric gate insulator positioned between the gate conductor and the semiconductor rod.
Inventors:
MAJHI PRASHANT (US)
KARPOV ELIJAH (US)
DOYLE BRIAN (US)
SHARMA ABHISHEK (US)
PILLARISETTY RAVI (US)
KARPOV ELIJAH (US)
DOYLE BRIAN (US)
SHARMA ABHISHEK (US)
PILLARISETTY RAVI (US)
Application Number:
PCT/US2018/013604
Publication Date:
July 18, 2019
Filing Date:
January 12, 2018
Export Citation:
Assignee:
INTEL CORP (US)
International Classes:
H01L27/11514; H01L21/28; H01L27/11507; H01L27/11509; H01L27/11512
Foreign References:
| US20160322368A1 | 2016-11-03 | |||
| US20150310905A1 | 2015-10-29 | |||
| US20160099254A1 | 2016-04-07 | |||
| US20160181259A1 | 2016-06-23 | |||
| US20150097155A1 | 2015-04-09 |
Attorney, Agent or Firm:
GREEN, Blayne D. et al. (US)
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