Title:
FFT PROCESSOR WITH OVERFLOW PREVENTION
Document Type and Number:
WIPO Patent Application WO/2000/073872
Kind Code:
A2
Abstract:
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with an FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio . In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.
Inventors:
NAVEH GIL
WEINGARTEN ERAN
GRANOT HAIM
WEINGARTEN ERAN
GRANOT HAIM
Application Number:
PCT/EP2000/004734
Publication Date:
December 07, 2000
Filing Date:
May 24, 2000
Export Citation:
Assignee:
INFINEON TECHNOLOGIES AG (DE)
International Classes:
G06F5/01; G06F7/57; G06F17/14; (IPC1-7): G06F/
Domestic Patent References:
| WO2000007114A1 | 2000-02-10 |
Foreign References:
| US5481488A | 1996-01-02 | |||
| US4872132A | 1989-10-03 | |||
| EP0155660A2 | 1985-09-25 |
Other References:
ANONYMOUS: "Programmable Storage Address Compare. November 1977." IBM TECHNICAL DISCLOSURE BULLETIN, vol. 20, no. 6, 1 November 1977 (1977-11-01), pages 2382-2390, XP002157199 New York, US
Attorney, Agent or Firm:
REINHARD SKUHRA WEISE & PARTNER (Postfach 44 01 51 München, DE)
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Claims:
WHAT IS CLAIMED IS:
| 1. | A A processor for performing a block floating point FFT on a plurality of data values. the processor executing a program. the processor comprising: (a) an FFT compare register. said FFT compare register operative to containing a programmable comparison constant which can be loaded under control of the program. said programmable comparison constant having a first magnitude; (b) an execution unit having an output data value. said output data value having a second magnitude: (c) a compare absolute value unit for comparing said second magnitude to said first magnitude; (d) a scale down by 2 unit for dividing said output data value by a factor of 2 ; (e) a scalebeforestore mode for activating said scale down by 2 unit; and (f) an FFT sticky status bit for indicating that said second magnitude has exceeded the magnitude of said first magnitude. |
| 2. | The processor of claim 1, wherein the execution unit further comprises: (i) a rounding unit for rounding said output data value substantially before said execution unit outputs said output data value. |
| 3. | An improvement to a processor for performing a block floating point FFT on a plurality of data values, the processor executing a program. the processor includille an execution unit, an FFT block floating point mode, a compare absolute value unit. a scale down by 2 unit, a scalebeforestore mode. and an FFT stickv status bit. the improvement comprising an FFT compare register. said FFT compare register operative to containing a programmable comparison constant which is loadable under control of the program. |
| 4. | A method for performing a block floating point FFT on a plurality of data values having absolute values utilizing a processor executing a program. the processor including an execution unit, a compare absolute value unit, a scale down bv 'unit. a scalebeforestore mode. a userloadable FFT compare register. and an FFT sticky status bit. the method comprising the steps of : (a) activating, if the scalebeforestore mode is enabled. the scale down by 2 unit; (b) comparing each of the plurality of data values with the FFT compare register; (c) setting, if a data value absolute value is not less (or lessorequal) than the FFT compare register the FFT sticky status bit; and (d) enabling, if the FFT sticky status bit is set, the scalebeforestore mode. |
| 5. | The method as in claim 4, wherein the processor further includes a rounding unit for performing a rounding operation and a rounding adjustment. the further steps of the method being performed by the rounding unit. the method further comprising the steps of: (e) adding, if the scalebeforestore mode is not enabled. the rounding adjustment to the data values. and (f) adding, if the scalebeforestore mode is enabled. twice the rounding adjustment to the data values. |
Description:
INTERNATIONAL SEARCH REPORT | Inter nal Application No PCT/EP 00/04734 C. (Continuation) DOCUMENTS CONSIDERED TO BE RELEVANT Category ° Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. A US 4 872 132 A (RETTER REFAEL) 1-5 3 October 1989 (1989-10-03) claim 1 A EP 0 155 660 A (HEWLETT PACKARD CO) 25 September 1985 (1985-09-25) 1 INTERNATIONAL SEARCH REPORT nterr nal Application No ) nter< <naApp! icat! onNo ..ormationonpatentfamilymembers | PCT/EP 00/04734 Patent document Publication Patent family Publication cited in search report date member (s) date WO 0007114 A 10-02-2000 NONE US 5481488 A 02-01-1996 NONE US 4872132 A 03-10-1989 NONE EP 0155660 A 25-09-1985 DE 3585449 A 09-04-1992 JP 1828149 C 28-02-1994 JP 5030327 B 07-05-1993 JP 60210016 A 22-10-1985 US 4750145 A 07-06-1988