Title:
FFT PROCESSOR WITH OVERFLOW PREVENTION
Document Type and Number:
WIPO Patent Application WO2000073872
Kind Code:
A3
Abstract:
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with an FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio . In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.
Inventors:
NAVEH GIL
WEINGARTEN ERAN
GRANOT HAIM
WEINGARTEN ERAN
GRANOT HAIM
Application Number:
PCT/EP2000/004734
Publication Date:
May 03, 2001
Filing Date:
May 24, 2000
Export Citation:
Assignee:
INFINEON TECHNOLOGIES AG (DE)
International Classes:
G06F5/01; G06F7/57; G06F17/14; (IPC1-7): G06F17/14
Domestic Patent References:
| WO2000007114A1 | 2000-02-10 |
Foreign References:
| US5481488A | 1996-01-02 | |||
| US4872132A | 1989-10-03 | |||
| EP0155660A2 | 1985-09-25 |
Other References:
ANONYMOUS: "Programmable Storage Address Compare. November 1977.", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 20, no. 6, 1 November 1977 (1977-11-01), New York, US, pages 2382 - 2390, XP002157199
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