TECHNICAL FIELD

[0001] This disclosure relates generally to Field Effect Transistors (FETs) and more particularly to improved layouts for such FETs.

BACKGROUND

[0002] As is known in the art, Field Effect Transistors (FETs) having a linear array of a plurality of FET cells are used in many applications. Each one of the FET cells has a source, a drain and a gate between the source and the drain to control a flow of carriers along a channel between the source and drain. It should also be understood the source and drain may be reversed in any electrical circuit application; with, in either circuit application, the gate controlling the flow of carriers between a source and a drain.

[0003] As is also known in the art, in some FETs, the gates are finger-like gates interconnected to a common gate contact on the top surface of a substrate. Likewise, the individual drains connected to a common drain contact electrode and the sources are connected to a common source contact using air bridges over the gate fingers and over either the drains, or over the sources, and with air bridges connected to a common drain, or source, contact on the bottom surface of the substrate. A FET with the air bridges over the drains is shown in FIG. 1. Generally, many of these are FET cells are stacked together in a linear array in the output stage of a power amp Monolithic Microwave Integrated Circuit (MMIC), as shown in FIG. 1. The linear stacking of these FET cells determines the linear dimension size of the MMIC.

SUMMARY

[0004] In accordance with the present disclosure, a Field Effect Transistor (FET) is provided having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.

[0005] In one embodiment, the FET gate contact is disposed on a bottom surface of the substrate and an electrically conductive gate via passes through the substrate to electrically connect the gate contact to the gate pad.

[0006] In one embodiment, the gate pad is disposed in an inner region of the loop.

[0007] In one embodiment, the gate projects outwardly from the gate pad.

[0008] In one embodiment, the drain contact is disposed on the upper surface of the substrate.

[0009] In one embodiment, the source contact is a conductor disposed on the bottom surface of the substrate and is connected to the source pad of each one of the FET cells though a corresponding one of a plurality of electrically conductive source vias passing through the substrate.

[0010] In one embodiment, a strip conductor is disposed on the bottom of the substrate, the feed line having one end connected to the gate contact, the feed line being spaced from the conductor disposed on the bottom surface of the substrate and connected to the gate contact through a gate via passing through the substrate.

[001 1] In one embodiment, the strip conductor and the conductor disposed on the bottom surface of the substrate provide a coplanar waveguide transmission line

[0012] In one embodiment, the gate via and the plurality of source vias provide a quasi- coaxial transmission line.

[0013] In one embodiment, the loop configuration is a circle. [0014] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a plan view of a Field Effect Transistor (FET) having a plurality of interconnected FET cells according to the PRIOR ART;

[0016] FIG. 2 is a perspective view of a Field Effect Transistor (FET) having a plurality of interconnected FET cells according to the disclosure;

[0017] FIG. 3 A is a plan view of the FET of FIG. 2;

[0018] FIG. 3B is a plan view of the FET of FIG. 3A with air bridges used in the FET of FIG. 2 removed to more clearly show elements of the FET of FIG. 2 covered by the air bridges;

[0019] FIG. 3C is a cross sectional view of a portion of the FET of FIG. 2, such cross section being taken along line 3C-3C of FIG. 3 A;

[0020] FIG. 3D is a cross sectional view of a portion of the FET of FIG. 2, such cross section being taken along line 3C-3C of FIG. 3 A;

[0021] FIG. 4 is an exploded perspective view of the FET of FIG. 2; and

[0022] FIG. 5 is a perspective view of a FET having a plurality of interconnected FET cells according to another embodiment of the disclosure;

[0023] FIG, 5A is a plane view of the FET of FIG. 5; and

[0024] FIG. 5B is a cross sectional view of the FET of FIG. 5, such cross section being taken along line 5B-5B of FIG. 5 A with the FET mounted to a printed circuit board having an input impedance matching network (IMN) and an output impedance matching network (OMN) coupled to the FET.

[0025] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0026] Referring now to FIG. 2, 3 A, 3B, 3C, 3D and 4, a Field Effect Transistor (FET) 10 is shown here formed using photo-lithographic chemical etching processing. More particularly, the FET 10 includes a plurality of, here eight, FET cells 12ρ12 ₈ , (FIG. 3 A) interconnected by eight air bridges 11 _r 11 ₈ and controlled by a corresponding one of eight gates Gj-Gg, respectively (FIGS. 2 and 3A; FIG. 3B showing the FET 10 with the air bridges 111 - 11 s removed to more clearly show the cells 12^12 ₈ ). Each one of the FET cells 12i-12 ₈ has, on an upper, planar surface 13 of a semiconductor substrate 15, here for example a substrate having gallium nitride (GaN), a corresponding one of eight gates Gi- G ₈ , respectively, in Schottky contact with the surface 13 of the semiconductor substrate 15, as shown in FIG. 1 ; each one of the eight gates Gi-G ₈ being disposed between a source (S) and a drain (D) in a manner to be described in more detail hereinafter to control a flow of carriers along a channel between the source pad (S) and drain pad (D) of each one of the eight, FET cells 12j-12 ₈ . Suffice it to say here; however that each one of the gates Gi- G ₈ is here an elongated, fmger-like gate and extends radially outward from a central, circular shaped gate pad 17, as shown. The gate pad 17 is electrically connected to a gate contact 18, shown more clearly in FIG. 4) disposed on a bottom surface 19 (FIG. 2B) of the semiconductor substrate 17 through an electrically conductive gate via 21 disposed at the center of the gate pad 17 and passing vertically through the substrate 15 between the gate pad 17 and the gate contact 23 (FIGS. 3C and 4). The elongated, finger-like gates Gp G ₈ are regularly spaced about the outer periphery of the common gate pad 17. More particularly, the finger-like gate electrodes GpGg are electrically interconnected to successive, evenly spaced points, P, (FIG. 3B) along an outer edge of the common, circular shaped, gate pad 17. Thus, the here eight elongated, finger-like gates Gi-Gg are separated one from the other by here forty-five degrees. [0027] The FET 10 also includes a drain contact 16 disposed on the upper surface 13 of the substrate 15 and terminating in a circular ring- like structure 18 (FIG. 4) having a plurality of, here four, radially inwardly extending projections 20j-20 ₄ regularly spaced about an outer, circumferential rim of the circular structure 18; each one of the projections 20i-20 ₄ is a drain pad in ohmic contacted with the surface 13 of the semiconductor substrate 15. Each one of the projections 20i-20g provides a drain (D) (FIGS. 2, 3A, 3B) for a pair of adjacent FET cells 12i-12 ₈ , in a manner to be described in more detail hereinafter. The central axis of the circular structure 18 and the center of the circular, common pad 17 are co-axial and are disposed along a common vertical Z axis, such Z axis being perpendicular to the X-Y planar surface 13 (FIG. 3B). Thus, here the surface 13 is in the X-Y plane and the common vertical axis is along the Z-axis. Thus, here the projections 20]-20 ₄ are spaced one from another by ninety degrees. It is noted that the projections 20i-20 ₄ terminate a predetermined distance from the outer periphery of the common gate pad 17 (FIG. 3B). It is also noted that each one of the projections 20i-20 ₄ is disposed between every other adjacent pair of the finger-like gates Gi-G ₈ ; as shown most clearly in FIG. 3B. Thus, each one of the projections 20] - 20 ₄ provides two drains (D) for the FET 10, one radial positioned side region of the projection 20i - 20 ₄ providing a drain for one of the eight FET cells 12]-12 ₈ and the opposite radially positioned side region providing a drain for the adjacent one of the eight FET cells 12i-12 ₈ . Thus, here, projection 20i is disposed between gates G ₂ and G ₃ ; projection 20 ₂ is disposed between gates G ₄ and G ₅ ; projection 20 ₃ is disposed between gates G ₆ and G ₇ ; and projection 20 ₄ is disposed between gates G ₈ and Gi . More particularly, looking vertically downward on the FET 10 and progressing clockwise; one side region of projection 20i provides the drain for FET cell 12 ₂ while the opposite side region of projection 20i provides the drain for FET cell 12 ₃ ; one side region of projection 20 ₂ provides the drain for FET cell 12 while the opposite side region of projection 2 i provides the drain for FET cell 12 ₅ ; one side region of projection 20 ₃ provides the drain for FET cell 12 ₆ while the opposite side region of projection 20 ₃ provides the drain for FET cell 12 ₇ ; and one side region of projection 20 ₄ provides the drain for FET cell 18 ₂ while the opposite side region of projection 20 ₄ provides the drain for FET cell 12i _.

[0028] An annular structure 30 (FIG. 4) having a center coaxial with both the gate pad 17 and the circular ring-like structure 18 (along the Z-axis) has four source pads 221 - 22 ₄ (FIGS. 2, 3A and 3B) regularly spaced circumferentially about the annular structure 30; that is the source pads 221 - 22 ₄ are spaced one from the other by ninety degrees and are disposed on the upper surface 13 (FIGS. 2, 3 A and 3B). Each one of the source pads 22i - 22 ₄ is in ohmic contacted with the surface 13 of the semiconductor substrate 15. The source pads 221 - 22 _{4 (} FIG. 4) are electrically interconnected by the air bridges 11 i-l 1 ₄ (FIGS. 2, 3A and 4; the air bridges 11 i-l 1 ₄ not being shown in FIG. 3B as mentioned above). Thus, the each one of the air bridges 11 i-l 1 ₄ is elevated from the surface 13 and, more particularly, each one of the air bridges 11 _r l 1 is elevated from a corresponding one of the projections 20i-20 ₄ and over a pair of adjacent Gi-Gg on each side of the such corresponding one of the projections; one gate finger on either side of the projection 20i- 20 ₄ . Thus, air bridge 111 is over projection 20i and over gate fingers G ₂ and G ₃ ; air bridge 11 ₂ is over projection 20 ₂ and over gate fingers G ₄ and G ₅ ; air bridge 11 ₃ is over projection 2Ο3 and over gate fingers G and G ₇ ; and air bridge 11 ₄ is over projection 20 ₄ and over gate fingers G ₈ and Gi ; as indicated in FIGS. 2 and 3B. Thus, it is noted that each one of the four source pads 22i - 22 ₄ is disposed between an adjacent pair of the finger-like gates G G ₈ . Thus, source pad 22i is disposed between gates Gi and G ₂ ; source pad 22 ₂ is disposed between gates G ₃ and G ₄ ; source pad 22 ₃ is disposed between gates G ₅ and G ₆ ; and source pad 22 is disposed between gates G ₇ and Gg as shown in FIG. 3B. Thus, each one of the source pads 221 - 22 ₄ provides two sources (S) for the FET 10, one radial positioned side region of the source pad 221 - 22 ₄ providing a source (S) for one of the eight FET cells 12 _r 12g and the opposite radially positioned side region providing a source (S) for the adjacent one of the eight FET cells 12i-12 ₈ . Thus, each one of the gate fingers Gi-Gg is disposed between a source (S) and drain (D), with each one of the fingers Gj-Gg being adjacent one side of one of the source (S) and one side of the drain (D) while an adjacent one of the gate fingers Gi-G ₈ is adjacent the other side of the same drain (D) and one of the source (S). It follows then that each gate finger (G) shares a drain (D) provided by one of the projections or drain pads 20i-20 ₄ and a source (S) provided by an adjacent one of the source pads22] - 22 .

[0029] Referring again to FIG. 4, a source contact 25, here provided by an electrical conductor 25 on the bottom surface 19 of the substrate 17 is electrically connected to the sources pads 22j-22 ₄ of the FET cells 12i-14g through, here four vias 27 (FIGS. 2, 3A and 4) passing vertically through the substrate 15 between the conductor 25 and the four source pads 22]-22 ₄ . Also formed on the bottom surface 19 of the substrate 15 is a conductive feed 32 (FIG. 4) for the gate pad 17. The feed 32 is a strip conductor 34 terminating in the gate contact 23. The gate contact 23 is connected to the gate pad 17 with a gate via 21. It is noted that the gate via 21 is disposed within a circular array of the vias 27 thus forming a vertical quasi coaxial transmission line. It is also noted that the electrical conductor 25 (FIG. 4) and feed 32 are electrically insulated from each other by the portion of the substrate 19 in the space between the feed 32 and the electrical conductor 25, as indicated. Thus, the conductor 25 on the bottom of the substrate 15 is spaced a predetermined distance from the feed line 34, as indicated, to provide a coplanar waveguide (CPW) transmission line feed for the 32. Thus, an RF input signal is fed to the FET 10 through the backside in a quasi-coax approach.

[0030] Thus, the FET cells \2 _\ -\2 _% are disposed in an X-Y plane in a closed loop configuration, here for example, a circular configuration in the X-Y plane (Fig. 3 A and 3B) on the upper surface 13 of the substrate 19. The FET 10 is suitable for flip chip mounting to a printed circuit board.

[0031 ] Referring now to FIG. 5, here the FET 10' has the air bridges 11 i-l 1 ₄ eliminated since each one of the source pads 22i-22 ₄ is connected to ground conductor 25 of the bottom of the substrate 15 with the vias 27. More particularly, it was recognized that because the gates G1-G8 extend radially out from the pad 17, the source pads 22i-22 ₄ are triangular shaped and thus flare out from the center of the pad 17, there is now sufficient space towards the base of the triangle for placement of a via 27 thus eliminating the need for air bridges. To put it another way, the gate to gate spacing spreads out as one moves away from the center of the FET which allows for vias 27 for each source pad without growing the size of the FET.

[0032] Thus, here the FET 10' again includes the plurality of, here eight, FET cells 12i- 12 _g , (FIG. 3 A); here, however they are interconnected by the electrical conductor 25 through the vias 27. More particularly, as described above and shown more clearly in FIG 3B, one side region of projection 20i provides the drain for FET cell 12 ₂ while the opposite side region of projection 201 provides the drain for FET cell 12 ₃ ; one side region of projection 20 ₂ provides the drain for FET cell 12 while the opposite side region of projection 20i provides the drain for FET cell 12 ₅ ; one side region of projection 20 ₃ provides the drain for FET cell 12 ₆ while the opposite side region of projection 20 ₃ provides the drain for FET cell 12 ₇ ; and one side region of projection 20 ₄ provides the drain for FET cell 18 ₂ while the opposite side region of projection 20 ₄ provides the drain for FET cell 12].

[0033] The drain / RF output can be bonded to from the topside of this circular FET as shown in FIG. 5 A. Thus, referring to FIG. 5B the FET 10' mounted to a printed circuit board 30 having an input impedance matching network (IMN) and an output impedance matching network (OMN) coupled to the FET 10'. More particularly, the IMN is coupled to the gate contact 23 through a microstrip transmission line having a strip conductor 36 separated from a ground plane conductor 38. More particularly, the strip conductor 36 is connected to the strip conductor 34 (FIG. 4). The OMN is coupled to the drain contact 16 through a conductor 38 connecting the strip conductor 40 of a microstrip transmission line separated from an underlying portion of the ground plane conductor 38.

[0034] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, other loop configurations may be used such as, for example, an oval or square or rectangular or triangular or other polygon shaped configuration. Further, the source and drain may be reversed in any electrical circuit application; with, in either circuit application, the gate controlling the flow of carriers between a source and a drain.

[0035] It should now be appreciated a Field Effect Transistor (FET) according to the disclosure includes: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate, each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads, a gate contact connected to the gate electrode of each one of the FET cells, a drain contact connected to the drain pad of each one of the FET cells and a source contact connected to source pad of each one of the FET cells; wherein the cells are disposed in a loop configuration. The FET may include one or more of the following features, independently or in combination with another feature, to include: a gate pad disposed on an upper surface of the substrate connected to the plurality of gate electrodes wherein the gate contact is disposed on an bottom surface of the substrate; and wherein an electrically conductive gate via passes through the substrate to electrically connect the gate contact to the gate pad; wherein the gate pad is disposed in an inner region of the loop; wherein the gate electrodes projects outwardly from the gate pad; wherein one of the source contact or the drain contact is disposed on the bottom surface of the substrate; wherein one of the source contact or the drain contact is a conductor disposed on the bottom surface of the substrate and is connected to the corresponding one of the source pad or drain pad of each one of the FET cells though a corresponding one of a plurality of electrically conductive vias passing through the substrate; a strip conductor disposed on the bottom of the substrate, the feed line having one end connected to the gate contact through a gate via passing through the substrate, the feed line being spaced from the conductor disposed on the bottom surface of the substrate; wherein the strip conductor and the conductor disposed on the bottom surface of the substrate provide a coplanar waveguide transmission line; wherein the gate via and the plurality of vias provide a quasi-coaxial transmission line; wherein the loop configuration is a circle; a substrate and a gate pad disposed on an upper surface of the substrate wherein the gate contact is disposed on an bottom surface of the substrate and wherein an electrically conductive gate via passes through the substrate to electrically connect the gate contact to the gate pad; wherein the gate pad is disposed at the center of the circle; wherein the gate pad is disposed at the center of the circle; a strip conductor disposed on the bottom of the substrate, the feed line having one end connected to the gate contact, the feed line being spaced from the conductor disposed on the bottom surface of the substrate; wherein the strip conductor and the conductor disposed on the bottom surface of the substrate provide a coplanar waveguide transmission line; wherein the gate via and the plurality of source vias provide a quasi-coaxial transmission line; a substrate and wherein one of the source pads or drain for each one of the FET cells in the plurality of FET cells is connected to a corresponding source or drain contact on a bottom surface of the substrate.

[0036] It should now be appreciated a Field Effect Transistor (FET) according to the disclosure includes: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells wherein the gate electrode of each one of the plurality of FET cells projects radially outwardly from a center of the FET. The FET may include one or more of the following features, independently or in combination with another feature, to include: wherein one of the source pads or drain pads of each one of the FET cells in the plurality of FET cells is connected to a contact on a bottom surface of the substrate through a corresponding one of a plurality of vias passing through the substrate, and wherein each one of the plurality of vias is disposed between a pair of the gates; a strip conductor disposed on the bottom of the substrate, the feed line having one end connected to the gate contact through a gate via passing through the substrate, the feed line being spaced from the conductor disposed on the bottom surface of the substrate; wherein the strip conductor and the conductor disposed on the bottom surface of the substrate provide a coplanar waveguide transmission line; wherein the gate via and the plurality of vias provide a quasi-coaxial transmission line.

[0037] Accordingly, other embodiments are within the scope of the following claims.