FIELD-EFFECT TRANSISTOR - TOKYO INST TECH

Title:

FIELD-EFFECT TRANSISTOR

Document Type and Number:

WIPO Patent Application WO/2014/108940

Kind Code:

A1

Abstract:

Provided is an FET (2) having a channel region (14) and a superlattice region (12) that are provided between source and drain electrodes. The channel region (14) is formed in a region in contact with one surface of the superlattice region (12). A drain region (16) and a drain electrode (18) are formed in this order adjacent to the channel region (14). An impurity-doped region (10) having an impurity diffused therein is formed around the superlattice region (12).

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Inventors:

MIYAMOTO YASUYUKI (JP)
KANAZAWA TOHRU (JP)
KASHIWANO MASASHI (JP)

Application Number:

PCT/JP2013/001344

Publication Date:

July 17, 2014

Filing Date:

March 05, 2013

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Assignee:

TOKYO INST TECH (JP)

International Classes:

H01L21/336; H01L29/78

Foreign References:

JP2009535861A	2009-10-01
JP2008543053A	2008-11-27
JPS6394682A	1988-04-25

Attorney, Agent or Firm:

MORISHITA, SAKAKI (JP)
Sakaki Morishita (JP)

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