Related subject matter is disclosed in the following pending U. S. patent applications assigned to the same assignee: (1) 08/991,904 filed on 12/17/97; (2) 09/009,097 filed on 01/20/98; and (3) 08/992,519 filed on 12/17/97.

Field of the Invention The present invention pertains to the area of cathodoluminescent devices and, more particularly, to field emission displays.

Background of the Invention It is known in the art to use spacer structures between the cathode and anode of a field emission display. The spacer structures maintain the separation between the cathode and the anode. They must also withstand the potential difference between the cathode and the anode.

However, spacers can adversely affect the flow of electrons toward the anode in the vicinity of the spacer.

Some of the electrons emitted from the cathode can cause electrostatic charging of the surface of the spacer, changing the voltage distribution near the spacer from the desired voltage distribution. The change in voltage distribution near the spacer can result in distortion of the electron flow.

In a field emission display, this distortion of the electron flow proximate to the spacers can result in distortions in the image produced by the display. In particular, the distortions render the spacers"visible"by producing a dark region in the image at the location of each spacer.

Several prior art spacers attempt to solve the problems associated with spacer charging. For example, it is known in the art to provide a spacer having a surface which has a sheet resistance that is low enough to remove the impinging electrons by conduction, yet high enough to keep power loss due to electrical current from the anode to the cathode at a tolerable level. The resistive surface can be realized by coating the spacer with a film having the desired resistance.

However, these films are susceptible to mechanical damage and/or alteration, such as may occur during the handling of the spacers. They are also susceptible to chemical alteration, which may change their resistivity.

It is also known in the art to provide additional, independently controlled electrodes along the height of the spacer for controlling the voltage distribution near the spacer. However, this prior art scheme includes additional processing steps for forming the spacer electrodes, which are also mechanically susceptible to damage. This prior art scheme also uses additional voltage sources for applying potentials to the spacer electrodes, which may greatly increase the complexity and cost of the device.

Accordingly, there exists a need for an improved field emission device, which has spacers that reduce distortion of electron flow and that do not result in excessive power losses.

Brief Description of the Drawing The sole FIGURE is a cross-sectional view of an embodiment of a field emission device in accordance with the invention.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the FIGURE have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to each other.

Description The invention concerns a field emission device having high-capacitance spacers. The invention takes advantage of the fact that matrix-based display devices, including field emission display devices, are generally addressed one line at a time. For example, a field emission display device contains a plurality of gate electrodes and a plurality of cathode conductors, which define an array of individually addressable pixels. Each gate electrode defines one horizontal row, and each cathode conductor defines one vertical column. The

operation of the field emission display device includes activating one row at a time (i. e., all gates in that row are driven positive), while electrical signals appropriate to the desired light distribution in that particular row are applied to the cathode conductors. If the field emission display contains, for example, 240 rows, each row is active during only 1/240 of the total time; the rest of the time it remains inactive. Typically, the active period ranges from about 30 to about 100 microseconds, depending upon the number of rows and upon the frame rate. The inactive period lasts between 13,000 and 20,000 microseconds.

With prior art spacers, the electrostatic charging process previously described produces adverse potential distributions on the spacer surface within the first few microseconds of the active period of each row. During the remainder of the active period, the electron flow remains distorted, and a dark region appears at the location of the spacer.

However, for a high-capacitance spacer in accordance with the invention, it takes a given charge much longer to produce a given potential change, and the growth of an adverse potential distribution is slowed down in inverse relation the capacitance of the spacer. With available high-permittivity materials, the capacitance can be made so large that the growth of electron flow distortion during the active period of 30 to 100 microseconds is small enough to be harmless. When the active period for a given row ends, the charging process also stops, and the full frame time of many thousands of

microseconds becomes available to dispose of the accumulated charge.

Expressed somewhat differently, the large capacitance results in a controlled low rate of increase of the voltage on the surface of the high-capacitance spacer. The controlled rate of increase of the voltage limits the cumulative change in voltage at the high-capacitance spacer during the emission time of the electron emitters proximate to the high- capacitance spacer. The controlled voltage increase results in reduced distortion of the electron flow. In one embodiment of the invention, the field emission device is a field emission display having high-capacitance spacers, which are invisible to a viewer of the field emission display. By controlling the distortion of the electron flow, a field emission display in accordance with the invention maintains the desired activation of phosphors proximate to the spacers.

The sole FIGURE is a cross-sectional view of a field emission display (FED) 100 in accordance with the invention.

FED 100 has a cathode assembly 102, which opposes an anode 104. An evacuated region 106 exists between cathode assembly 102 and anode 104. The pressure within evacuated region 106 is about 10-6 Torr. A high-capacitance spacer 108 extends between cathode assembly 102 and anode 104. High-capacitance spacer 108 provides mechanical support to maintain the separation between cathode assembly 102 and anode 104. High- capacitance spacer 108 has features that ameliorate distortion of the flow of an electron current 132 proximate to high- capacitance spacer 108. In the embodiment of the FIGURE,

high-capacitance spacer 108 further has features that render it invisible to a viewer of FED 100 during its operation.

Cathode assembly 102 includes a substrate 116, which can be made from glass, silicon, and the like. Upon substrate 116 is disposed a cathode conductor 118, which can include a thin layer of molybdenum. A dielectric layer 120 is formed on cathode conductor 118. Dielectric layer 120 can be made from, for example, silicon dioxide. Dielectric layer 120 defines a plurality of emitter wells 122, in which are disposed one each of a plurality of electron emitters 124. In the embodiment of the FIGURE, electron emitters 124 include Spindt tips.

However, a device in accordance with the invention is not limited to Spindt tip electron sources. Electron emitters for use in a device in accordance with the invention include thermionic electron emitters, photocathode electron emitters, field emission electron emitters, and the like. These types of electron emitters are known to one skilled in the art. For example, another useful type of field emission electron emitter is an electron-emissive carbon film. It is desired to be understood that the invention can be embodied by a cathodoluminescent display device having electron emitters other than Spindt tip field emission electron emitters. In general, the cathodoluminescent display device is operated one line at a time so as to define a charging period for each spacer.

Cathode assembly 102 further includes a plurality of gate electrodes. A first gate electrode 126 and a second gate electrode 128 are illustrated in the FIGURE. The gate

electrodes are used to selectively address the electron emitters.

Anode 104 includes a transparent substrate 110, upon which is disposed a transparent anode conductor 112, which can include a thin layer of indium tin oxide. A plurality of phosphors 114 is disposed upon anode conductor 112. Phosphors 114 oppose electron emitters 124.

A first voltage source 136 is connected between anode conductor 112 and ground. A second voltage source 138 is connected between second gate electrode 128 and ground. A third voltage source 140 is connected between first gate electrode 126 and ground, and a fourth voltage source 142 is connected between cathode conductor 118 and ground.

High-capacitance spacer 108 extends between cathode assembly 102 and anode 104. One end of high-capacitance spacer 108 contacts anode 104, at a surface that is not covered by phosphors 114; the opposing end of high-capacitance spacer 108 contacts cathode assembly 102, at a portion that does not define emitter wells 122.

In accordance with the invention, high-capacitance spacer 108 has a capacitance that is selected to reduce the distortion of the trajectory of electron current 132 proximate to high-capacitance spacer 108. In the embodiment of the FIGURE, the capacitance is provided so that the distortion of the trajectory of electron current 132 is controlled to an extent sufficient to render high-capacitance spacer 108 invisible to a viewer of FED 100 during its operation.

In general, the capacitance of high-capacitance spacer 108 is determined by several variables. These variables include the dielectric or permittivity constant of the material of high-capacitance spacer 108 and the geometry of high-capacitance spacer 108. Any combination of these variables can be manipulated to realize the desired capacitance.

In the embodiment of the FIGURE, a charge conductor 130 is provided between high-capacitance spacer 108 and cathode assembly 102. Charge conductor 130 is provided to avoid the occurrence of large electric fields at the base of high- capacitance spacer 108, due to microscopic roughness of the surface of high-capacitance spacer 108 in that region.

Charge conductor 130 is made from a convenient conductive material, such as molybdenum, aluminum, and the like. Charge conductor 130 can be connected to electrical ground or to one of first and second gate electrodes 126,128.

An embodiment of a field emission device in accordance with the invention will now be described with reference to the FIGURE. It is desired to be understood that a device embodying the invention is not limited to this configuration.

This exemplary configuration is useful for operation of FED 100 at a potential difference between cathode assembly 102 and anode 104, which is greater than about 300 volts, and preferably within a range of about 3000-5000 volts. It also includes a VGA configuration.

In the embodiment of the FIGURE, high-capacitance spacer 108 is a rectangular platelet, which has a length (into the

page) of about 5 millimeters, a height (extending between cathode assembly 102 and anode 104) of about 1 millimeter, and a thickness, t, of about 0.07 millimeters. The center-to- center distance between first and second gate electrodes 126, 128 is about 0.3 millimeters.

In general, the aspect ratio (ratio of height to thickness) of high-capacitance spacer 108 is determined by variables such as the potential difference between cathode assembly 102 and anode 104 and by the separation distance between adjacent gate electrodes. The height of high- capacitance spacer 108 is selected to be sufficient to prevent electrical arcing between cathode assembly 102 and anode 104.

The separation distance between adjacent gate electrodes is determined by the desired resolution of the display.

While the geometry of high-capacitance spacer 108 is affected by the above factors, the dielectric or permittivity constant of high-capacitance spacer 108 can be manipulated to provide the desired capacitance. Thus, in the embodiment of the FIGURE, the dielectric constant of high-capacitance spacer 108 is selected to control the potential rise at high- capacitance spacer 108, so that any resulting distortion of the trajectory of electron current 132 due to the electrical charging of high-capacitance spacer 108 is not visibly discernable to a viewer of FED 100.

In the embodiment of the FIGURE, high-capacitance spacer 108 has a dielectric constant, which is greater than 80, preferably greater than 500. To provide the high dielectric constant, high-capacitance spacer 108 is made from a high

permittivity material. Exemplary high permittivity materials for use in the embodiment of the FIGURE include niobate materials, tantalate materials, titanate materials, titania (Ti02), and the like.

For example, useful titanate materials include barium titanate, strontium titanate, strontium calcium titanate ( (Sr, Ca) TiO3), calcium magnesium titanate ( (Ca, Mg) TiO3), rare earth barium titanates, and the like. Exemplary rare earth barium titanates are samarium barium titanate (BaSm2TiO6); neodymium barium titanate; and rare earth barium titanates having the general formula BaRE2Ti4012, wherein RE is a rare earth trivalent cation (eg. La, Sm); and the like. The neodymium barium titanate material can be a mixture of three <BR> <BR> <BR> <BR> phases: a first phase of Nd2BaTisO (.,, 5-X wherein 0 S x S 3.5, a second phase of NdTiO3, and a third phase of Nd2Ti207. Another useful material is a mixture of barium titanate and the titanate of one or more other Group IIA elements of the Periodic Table. Exemplary niobate materials are bismuth-based niobates, such as zinc bismuth niobate (Bi2 (ZnNb2) Og), nickel bismuth niobate (Bi3 (Ni2Nb) Og), and the like.

During the operation of FED 100, potentials are applied to gate electrodes 126,128, cathode conductor 118, and anode conductor 112 to cause selected electron emission at electron emitters 124 and to direct the electrons through evacuated region 106 toward phosphors 114. Phosphors 114 are caused to emit light by the impinging electrons. Typically, the gate electrodes of FED 100 are sequentially addressed. As each gate electrode is addressed, a voltage is applied to each of

the cathode conductors. Each gate electrode is addressed for a period of time referred to as the active period or"line time."The entirety of gate electrodes within FED 100 is addressed during a frame. The time required to address once each of the gate electrodes within FED 100 is referred to as the"frame time." During the frame time, when electron emitters 124 proximate to high-capacitance spacer 108 are caused to emit electrons, some of these electrons impinge upon high- capacitance spacer 108, as indicated by an arrow 134 in the FIGURE. These impinging electrons cause electrostatic charging and changes in the potential at the surface of high- capacitance spacer 108. The impinging electrons indicated in the FIGURE are generated or emitted upon activation of second gate electrode 128. Similar electrostatic charging can also occur when first gate electrode 126 is addressed. In general, during the frame time of FED 100, there is a period of time, the charging period, during which the surfaces of high- capacitance spacer 108 are becoming electrostatically charged, and there is a period of time, the quiescent period, which is equal to the remainder of the frame time, not including the charging period.

The capacitance of high-capacitance spacer 108 is provided to control the rate of change of the potentials at the surface of high-capacitance spacer 108. The controlled rate of change of the surface potentials results in reduced distortion of the trajectory of electron current 132, so that the desired activation of phosphors 114 is maintained. The

controlled rate of change of the surface potentials also results in reduced incremental charge accumulation at high- capacitance spacer 108, which reduces the charge dissipation requirements. Specifically, the capacitance is selected so that the potential changes at the surfaces of high-capacitance spacer 108 during the charging period are low enough to prevent undesirable distortion of the flow of electron current 132 proximate to high-capacitance spacer 108.

In the embodiment of the FIGURE, the selected value of the dielectric constant depends upon the value of the electron current impinging upon high-capacitance spacer 108. In general, the dielectric constant increases with increasing impinging electron current.

For a dielectric constant of about 1000 and a geometry of high-capacitance spacer 108 as described above, the capacitance of high-capacitance spacer 108 from its center to either anode conductor 112 or charge conductor 130, each of which is connected to ground potential for the purpose of this measurement, is about 14 picoFarad. For this configuration, it is believed that the maximum rate of potential rise at the surface of high-capacitance spacer 108 is about 0.36 V/s for operation of FED 100 at an anode-to-cathode potential difference of about 5 kilovolts. For a line time of about 63 ps and assuming both first and second gate electrodes 126,128 are caused to emit over the entirety of the line time, the maximum potential rise at the surface is about 45 volts. This results in an accumulated electrical charge of about 635 picocoulomb per spacer per frame.

After gate electrode 126,128 have been addressed, there is a period of time during the given frame time in which the remaining gate electrodes of FED 100 are addressed, and high- capacitance spacer 108 is not impinged by electrons. During this quiescent time, the accumulated charge is discharged by one of a variety of methods.

For example, the end-to-end resistance of high- capacitance spacer 108 can be selected to provide a slight electrical current, which is sufficient to dissipate during the quiescent time the accumulated charge. The end-to-end resistance is also high enough to control power loss due to current between anode 104 and cathode assembly 102. In the embodiment of the FIGURE, a useful end-to-end resistance for high-capacitance spacer 108 is of the order of 10 gigaohms.

The discharge current flows out of FED 100 through charge conductor 130. High-capacitance spacer 108 can be rendered slightly conductive by, for example, adding a useful concentration of a dopant to the dielectric material of high- capacitance spacer 108.

Alternatively, the accumulated charge at high-capacitance spacer 108 can be neutralized by activating, at the termination of each frame time, some or all of electron emitters 124. In this manner, electrons are emitted into evacuated region 106 and are made available to neutralize the positive charge at high-capacitance spacer 108. During this neutralization step, the potential at anode 104 is dropped to a value substantially below the potential at high-capacitance spacer 108, so that the electrons are attracted toward high-

capacitance spacer 108 and not toward anode 104. The number and configuration of electron emitters 124, which are caused to emit electrons during the neutralization step, are selected to effect the desired neutralization. In an exemplary neutralization step, only electron emitters 124 that are proximate to high-capacitance spacer 108 are activated.

In summary, the invention concerns a field emission device having high-capacitance spacers. The field emission device of the invention ameliorates electron flow distortion due to the presence of spacers. In one embodiment of the invention, a field emission display includes high-capacitance spacers, which are invisible to a viewer of the field emission display.

While we have shown and described specific embodiments of the present invention, further modifications and improvements will occur to those skilled in the art. We desire it to be understood, therefore, that this invention is not limited to the particular forms shown, and we intend in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention.