Holland, Edward Robert (82 Howard Street Oxofrd OX4 3BE, GB)
Yagang LI. (5 St George's Court Bridge Street Witham Essex CM8 1AG, GB)
Wilshaw, Peter Richard c/o Department of Materials University of Oxford Parks Road Oxford OX1 3PH . (GB)
Holland, Edward Robert (82 Howard Street Oxofrd OX4 3BE, GB)
Yagang LI. (5 St George's Court Bridge Street Witham Essex CM8 1AG, GB)
| 1. | A field emitter device which comprises a layer of a nonconducting support material having thereon successive layers of an address electrode, a dielectric anodic metal oxide layer and, optionally, lastly, a grid electrode, the dielectric anodic metal oxide layer possessing an array of pores extending from the surface in contact with the grid electrode to the address electrode, said pores containing wires which extend from the address electrode to the surface of the anodic metal oxide layer remote from the address electrode, at least one section along the wires not in contact with the address electrode being formed of a resistive material. |
| 2. | A device according to claim 1 which comprises a buffer layer between the address electrode layer and the anodic metal oxide layer such that the wires extend to the buffer layer while maintaining electrical contact with the address electrode. |
| 3. | A device according to claim 1 or 2 wherein the wires terminate at the surface of the anodic metal oxide layer in emitter cones. |
| 4. | A device according to claim 3, wherein said resistive material forms a single ballast resistor between the address electrode and the metal at the surface of the anodic metal oxide layer. |
| 5. | A device according to claim 3, wherein said resistive material forms 2 or more sections between the address electrode and the base of the emitter cones. |
| 6. | A device according to any one of claims 1 to 5, wherein the resistive material is iron oxide, tin oxide or zinc oxide. |
| 7. | A device according to any one of the preceding claims wherein the anodic metal oxide is aluminium oxide. |
| 8. | A device according to any one of the preceding claims wherein the address electrode is made of titanium, chromium or aluminium. |
| 9. | A device according to any one of claims 2 to 8 wherein the buffer layer is an amorphous silicon layer. |
| 10. | A device according to any one of the preceding claims wherein the section or sections of the wire above the resistive material is/are of nickel. |
| 11. | A field emitter device according to any one of the preceding claims which comprises a grid electrode. |
| 12. | A field emitter device according to claim 1 substantially as described in Figure 1 or 2. |
| 13. | A process for making a device as claimed in any one of the preceding claims which comprises: (a) providing a nonconductive support layer having thereon an address electrode layer, (b) applying to the address electrode layer a continuous metal layer capable of being anodised to a porous oxide layer, (c) subjecting the arrangement to anodisation sufficient to cause an array of pores to form through said metal layer to the address electrode layer, (d) forming wires in said pores, (e) converting a frontal section of the wires in said pores into a resistive material, extending the wires above said resistive material to the surface of the oxidised metal layer, and, optionally, (g) applying a grid electrode over the surface of the oxidised metal layer. |
| 14. | A process according to claim 13 wherein step (e) is carried out by anodising the frontal section of the metal to a resistive metal oxide. |
| 15. | A process according to claim 14 wherein the metal is zinc and anodisation is carried out using sodium carbonate as electrolyte. |
| 16. | A process according to claim 14 or 15 wherein step (c) is carried out by stepwise increasing the voltage, maintaining the voltage at a given level and then stepwise reducing it :. |
| 17. | A process according to any one of claims 13 to 16 wherein in step the wires are extended over the resistive material with nickel. |
| 18. | A process according to any one of claims 13 to 17 wherein in step emitter cones are formed at the free ends of the wires. |
| 19. | A process according to claim 13 substantially as hereinbefore described. |
| 20. | A field emitter device as defined in any one of claims 1 to 11 whenever made by a process as claimed in any one of claims 13 to 19. |
| 21. | A field emitter device comprising a layer of resistive material which is an oxide which is a wide band gap semiconductor, said oxide being obtained by anodisation of a metal or alloy. |
Prior art field emission devices often suffer from non-uniform electron emission at individual emitter sites. This problem is caused, at least in part, by the different geometry of the individual emitters. It is found that a particularly favourable emitter structure can emit a much higher electrical current than the other emitter structures, for example in displays resulting in an abnormal bright spot on the phosphor faceplate, which constitutes a visual defect and reduces the device lifetime.
Another problem often encountered in the field emission devices is"short- circuiting", involving an electrical contact between the grid electrode and the individual emitter cathodes. Short circuits result in non-functional emitters and, more seriously, an undesirably high electrical current flow between emitter cathodes and grid electrode when grid-cathode potential is typically of the order of tens of volts ; this may cause local damage and, in some instances, lead to destruction of the device.
A ballast resistor approach has been widely adopted to address these problems. A resistive ballast, often in the form of a layer structure, of a highly electrically resistive material, serves two purposes. First, it limits the electrical current flow through the shorted emitter cathodes because the ballast has sufficiently high resistance and the grid cathode voltage is sufficiently low that
large electrical currents do not flow. Thus it provides a means of protection against breakdown or destruction caused by short circuits. Second, the ballast resistor serves a current-limiting function for emitter cathodes, which means that if an excessive electrical current were to flow through an emitter cathode this would result in a larger potential drop across the resistor so lowering the voltage across the emitter and hence the emitted current. In this way the ballast resistor acts to limit the emission current from"good"emitters so that the current does not destroy them. In addition the ballast resistor ensures a large proportion of microtips are emitting instead of only those which are geometrically favourable, or "good"emitters, at that grid-cathode voltage. This improves the emission homogeneity across the display. One disadvantage of adopting a ballast resistor is that the operating voltage (grid-cathode potential) has to be increased.
An almost universally adopted approach to making such arrangements is to use a highly electrically resistive film such as amorphous silicon as the ballast resistor deposited between the emitter tips and the address electrode. For example US patent 4940916 introduces a continuous resistive layer having a resistivity of between approximately 102 and 106 ohms. cm. In one of the embodiments a sputtered Fe203 film is used whilst in the preferred embodiment phosphorus- doped silicon film is vacuum deposited on the network of the cathode conductor layer. The thickness of the resistive film, vertical dimension, together with the diameters of the emitter base and resistivity of the material, determine the resistance. In a slightly different approach disclosed by US patent 5194780 a lateral ballast structure is introduced by using a resistive film, preferably doped silicon film. The lateral ballast resistor approach principally relies on a lateral distance instead of a vertical dimension of the resistive film. A further improvement upon the lateral ballast resistor approach is disclosed in US patent 5507676. An extra conductive plate positioned directly underneath the emitter cathodes is introduced to ensure all of the emitters are substantially at an equal potential.
In W096/06443 we disclose a field emitter device comprising a dielectric anodic metal oxide layer having a front surface and a back surface, an array of
pores extending from the front surface to the back surface, the pores containing metal wires which have the back ends in electrical contact with an address electrode which overlies the back surface of the anodic oxide layer and have the front ends in electrical contact with individual field emitting cathodes while the front surface has a grid electrode. Preferred resistive materials for the ballast resistor which is present as a layer between the back ends of the wires and the address electrode include silicated diamond-like carbon or undoped amorphous or polycrystalline silicon.
It will be noted that most of the aforementioned approaches for providing a ballast resistor use a continuous layer of resistive material, very often a silicon film.
Unfortunately, there are some disadvantages associated with this approach. First, use of a continuous resistive layer is not an ideal solution regardless of the vertical or lateral resistor variation. The reason lies in the fact that a continuous resistive layer with a number of emitters formed on its surface behaves as a complex interconnected resistor network. Very often a short circuit in one emitter can inflict an undesirable influence on the operation of the surrounding emitters since the potential of the surrounding emitters is modified by the excessive current flowing through the layer beneath the defective emitter. Second, a resistive layer is usually formed by physical vapour deposition (vacuum deposition). A thin layer deposited in this way often has"pinholes"or other defects which will cause a breakdown in the homogeneity of the resistive layer and can lead to its failure.
More specifically, with particular reference to a field emitter structure based on a porous alumina layer as described in W096/06443, we have been unable to combat sufficiently the problem of short circuits, which is a dominant obstacle for any further exploitation.
In view of the above, a need exists for a cost-effective, reliable and efficient solution to address the problems associated with the continuous resistive layer approach.
Summary of the Invention
The present invention obviates the disadvantages inherent in using a continuous resistive ballast layer by using a discrete ballast resistor with a discrete, laterally non-connected resistive material underneath individual emitter tips to combat short circuits and emission inhomogeneity problems for optimal field emitter operation. The resistive material can be introduced inside individual emitter cavities other than by vacuum deposition.
According to the present invention there is provided a field emitter device which comprises a layer of a non-conducting support material having thereon successive layers of an address electrode, a dielectric anodic metal oxide layer and, optionally, lastly, a grid electrode, the dielectric anodic metal oxide layer possessing an array of pores extending from the surface in contact with the grid electrode to the address electrode, said pores containing wires which extend from the address electrode to the surface of the anodic metal oxide layer remote from the address electrode, at least one section along the wires not in contact with the address electrode being formed of a resistive material.
The present invention also provides a process for making the device which comprises: (a) providing a non-conductive support layer having thereon an address electrode layer, (b) applying to the address electrode layer a continuous metal layer capable of being anodised to a porous oxide layer, (c) subjecting the arrangement to anodisation sufficient to cause an array of pores to form through said metal layer to the address electrode layer, (d) forming wires in said pores, (e) converting a frontal section of the wires in said pores into a resistive material, extending the wires above said resistive material to the surface of the oxidised metal layer, and, if desired,
(g) applying a grid electrode over the surface of the oxidised metal layer.
Detailed Description of the Preferred Embodiment The invention will now be illustrated, merely by way of example, with reference to the accompanying Figures.
Figure 1 shows a cross-sectional view of a typical field emitter device with integrated ballast structure in accordance with the present invention. The field emitter device comprises a dielectric anodic alumina, 1, layer having a front surface, 2, and a back surface, 3, and an array of pores, 4, extending through the layer from the front surface to the back surface. Reference will be made to alumina although it will be appreciated that other metal oxides can be used. Each pore contains a metal wire, 5, having a back end and a front end, and a resistive metal oxide, 6, positioned on the front end of the metal wire. Each emitter cone, 7, or other emitter end, sits on the top of the individual resistive metal oxide inside the emitter cavity. An optional buffer layer, 8, overlies the back surface, 13, of the porous alumina layer. An address electrode, 9, overlies the buffer layer, 8, which is in electrical contact via the buffer layer with the back ends of the metal wires, together with an arrangement of a grid electrode, 10, overlying the front surface, 2, of the porous alumina layer, performing matrix-addressing for the emitters.
Alternatively the device does not have a grid electrode but in use a grid electrode is positioned a distance away from the front surface, 2, typically from 5Am to 2mm above it. The device also comprises a non-conductive substrate, 11.
A process for producing such a device involves the following stages. It should be noted that there are a number of processing steps in the present invention similar to those already described in W096/06443, to which reference should be made for further details. Here we discuss in detail the steps that are special to the present invention.
a) On a rigid insulating substrate, e. g. glass, a layer of address electrode made of a variety of metals, e. g. Ti, Ag, Cr, W, Nb, Ta Cr, or Al, is deposited, e. g. by electron-beam evaporation or sputtering techniques. The thickness of the address electrode layer is typically in the range of 50 nm to 5 microns, for example 100 nm to 400 nrii, especially 150 to 300 nm. The electrode may be deposited in the form of stripes perpendicular to the stripes of the grid electrode to be deposited at a late stage so that matrix addressing may be performed. al) An optional buffer layer, preferably an amorphous silicon layer, typically with the thickness in the range of 50 nm to 5 microns, for example 0.5 to 2 pm, is deposited, e. g. by electron-beam evaporation or sputtering. The buffer layer serves as a"soft cushion"to accommodate a final anodisation process, described in stage d).
The criteria for selecting materials for a buffer layer are i) that the material is electrically conductive (although the resistivity of the material can be high) and ii) that the material can efficiently stop or absorb the impact of a final anodisation process, e. g. by generating a barrier-type layer, for example of silicon oxide, and subsequently the generated barrier layer can be efficiently removed without damaging or substantially damaging the device structure. In certain circumstances, the metal of the address electrode will itself form an oxide barrier layer in which case a separate buffer layer is unnecessary b) An anodisable metal layer typically 2 to 20, for example 5 to 10, , um thick, is next deposited, e. g. by vacuum deposition. It has been found that the deposition should preferably be performed on a heated substrate with the substrate temperature being in the range of, for example, 150-300 °C in order to ensure a good adherence between the metal layer and the buffer or address layer, which is of
importance in the following high-voltage anodisation process. c) The metal layer is then subjected to an anodisation process to form a porous metal oxide film, which exhibits a generally uniform array of closed packed cells, typically approximately hexagonal, each containing a cylindrical pore perpendicular to the surface. The pore size, cell size and pore density are all governed by the anodisation voltage. The thickness of the porous oxide film is controlled by the current density and anodisation time. Hence, by controlling anodisation conditions, including voltage, current density, time and temperature, an anodic metal oxide film of chosen thickness having a uniform array of a high density of pores of chosen diameter and spacing can be readily manufactured in an established manner, e. g. as described in Rigby et al, Trans. Inst. Metal Finish, 68, 3,1990,95 and EP 0178831A1. The diameter and spacing of the pores depends on the anodising voltage. Using 0.4 M phosphoric acid, when the voltage is X volts, the pore diameter is typically about X nm and the pore spacing about 2.5X nm. In other words by increasing the voltage one increases the size of the pores and vice versa.
In a particular embodiment, a tri-layer Al/Si/Ti structure on a glass substrate with a top layer of 5-10 pLm aluminium on a buffer layer of 0.5-2 u. m amorphous silicon which is on the top of an address layer of 0.2-0.4 cm titanium, is anodised in a suitable electrolyte, usually phosphoric acid (H3PO4), sulphuric acid (H2SO4), or oxalic acid (H2C204), about 0.4 M HP04being preferred for a high-voltage anodisation. In an illustrative and non-limitive manner, an anodisation process on an Al/Si/Ti tri-layer structure using 0.4 M H3PO4 electrolyte is described below.
At the start of the anodisation process, the voltage is gradually increased from zero or a rather small value (e. g. 5 V) to the desired
level, e. g. 160 V, in one preferred embodiment for a period of about 2-3 minutes. It is found that using 0.4 M H3PO4 electrolyte at 15° C with a vigorous stirring of the electrolyte, a voltage of 160 V with a current density of 4-6 mA/cm2 needs to be applied for a period of approximately 30 minutes to produce a porous alumina film of about 5 am thick. The pores are around 0.160 llm in diameter.
It will be appreciated that if the conditions are such that anodising is carried out after pores have formed completely to the buffer layer then the latter itself starts to oxidise. In practice it is difficult to stop anodising at the precise time when all the pores have formed but no attack of the buffer layer has started. If a complete oxidised layer is formed from the buffer layer then the structure is destroyed.
Accordingly, it is necessary to stop the anodisation before this happens.
The applicants have found that this can be determined in advance by monitoring the current flowing through the device with time. It has been found that the current stays fairly constant until the buffer layer starts to be anodised when the current increases to a peak.
Once a complete layer has been formed the current drops off.
Accordingly, if in a sample experiment the time to reach the peak is noted then when the device is being made, using the same anodising conditions, anodisation can be stopped shortly before the peak is reached.
The final voltage needs to be selected with care. If it is too low then not only does it take too long for oxidisation to occur throughout the thickness of the metal layer but also the pores become smaller such that the walls of the pores tend not to retain their integrity. In general, therefore, a final voltage of about 5 volts is too small. In. practice, a final voltage of the order of 40 volts has generally been found to be particularly satisfactory. Generally it is 10 to 50 volts.
To ensure that a high anodisation voltage, e. g. 160 V, does not undesirably hit the underneath buffer layer, if present, a gradual voltage reduction process is designed to step down the voltage in a controllable manner from a high value, e. g. 160 V, to a desired final value, e. g. 40 V. The voltage reduction can be performed by a procedure as described in Rigby et al. 1990 or EP 0178831A1, where a voltage reduction is effected when the rate of current rise falls to a desired fraction of the maximum value. In accordance with the present invention, an efficient and simple voltage reduction procedure can be used. We have found that the film recovery time for a varying anodisation voltage from 160 V to 40 V can be broadly grouped into a number of different time periods. Thus a pre- determined time period may be assigned to individual stepping- down voltages from 160 V to 40 V. This voltage reduction procedure offers simplicity, ease of control and a high degree of efficiency. Typically a voltage reduction from 160 V to 40 V takes 15 minutes. It is generally desired to minimise the inevitable chemical dissolution of the alumina film which takes place all the time.
A final anodisation process at a low voltage, e. g. 40 V, immediately following the aforementioned voltage reduction process, serves to ensure that the final anodisation"front"reaches or passes beyond the interface between the oxide layer and the underneath buffer layer while minimising the collateral anodisation of the buffer layer : In a structure using a silicon buffer layer, it seems very likely that the base of the pores is an insulating silicon oxide barrier"island" formed at the end of the anodisation process, which prohibits a subsequent metal filling of the pores. It will be apparent that timing of the final anodisation needs to be controlled in a satisfactory manner as discussed above and that removal of the silicon oxide
barrier"island"at the base of individual pores is required. This can be achieved using known techniques generally involving a water- based chemical etchant such as Silox which is a mixture of ammonium fluoride and acetic acid. The Silox solution is 15 ml 40% NH4F and 3.2 ml acetic acid made up to 100g with water. The anodised alumina structure is immersed in the solution typically for 10 secs to 10 minutes. The structure should then be rinsed thoroughly with distilled water ready for the next step.
Up to this stage an anodic alumina layer with the pores of a desirable pore size and spacing extending from the front surface of the layer to the top surface of the silicon buffer layer is formed. The thickness of the formed porous alumina layer is determined by the thickness of the starting aluminium layer and the anodisation conditions. A procedure can be developed to monitor/estimate the anodic alumina growth by recording the amount of electric charge passed during the anodisation whilst taking account of the actual current efficiency at the anodisation conditions; this represents a fraction of the total electric charge passed through the electrolytic cell that is used to form aluminium oxide. In one example, a 10-20 , um thick porous alumina layer is formed from a 5-10 llm thick starting aluminium layer.
Due to the nature of the porous oxide layer formed by anodisation of metal, a period of settling time should be allowed to ensure a steady-state formation of a uniform array of parallel through pores perpendicular to the surface of the layer has been reached. The region in the oxide layer formed before a settling time or a steady- state anodisation has been reached is designated as a"transition region". It is recognised that the pore size, distribution &
parallelism in the transition region are far from desirable to enable the pores to serve as device sites for emitter cathodes. Consequently the transition region should be removed, as discussed below so that all the pores are regularly spaced and of more uniform diameter.
Therefore the initial metal film should be thick enough to accommodate this requirement. d) Wires are formed in the pores. The criteria for choosing a suitable metal to fill the pores are essentially two-fold. First, it should be capable of being readily placed into the pores using an efficient and uncomplicated method. Second, it must be possible to convert the metal wires formed into a resistive material with the desired electrical resistance. It will be appreciated that the formed resistive material in each pore is to serve as the"in-pore"ballast resistor for each emitter.
Filling of the pores with a metal may be achieved by a standard electroplating process; a negative potential can be applied to the address electrode whilst the pores are immersed in a suitable electrolyte. Suitable metals include Sn and Zn and alloys thereof, since these are capable of being readily converted into a resistive material. Suitable electrolytes therefore include inorganic salts of these metals such as zinc sulphate. Essentially any metal or alloy can be used which can be converted into an oxide which is a wide band gap semiconductor. i. e. an oxide having a band gap from 1 to 4 eV, for example 3 to 4 eV. By way of comparison, silicon has a value of 1.1 eV. ZnO has a value of 3.4 eV and SnO2 3. 5.
It will be appreciated that this conversion from metal or alloy into an oxide which is a wide band gap semiconductor is of general applicability. Accordingly the present invention also provides a field emitter device comprising a layer of resistive material which is
an oxide which is a wide band gap semiconductor, said oxide being obtained by anodisation of a metal or alloy. Thus this aspect of the invention also applies to the conventional emitters possessing a resistive ballast layer discussed in the introduction.
One preferred electroplating system uses a zinc sulphate plating solution that is made from 250 g/1 ZnSO4, 20 g/1 NH4Cl, 27 g/1 Al2 (SO4) 3 and 100 g/1 glucose with pH 3-4. The Zn plating can be operated with the electrolyte temperature maintained at, say, 20-30° C at a current density of 10-20 mA/cm2. The Zn plating should be performed in such a way that Zn fills in all or nearly all the pores up to the top surface of the oxide layer and forms a continuous layer across the surface. This is generally followed by mechanical polishing of the front surface of the porous oxide (or other metal oxide) layer as described in W096/06443. This process serves two purposes. First, it removes any over-filled metal (e. g. Zn) layer on the top of the alumina layer to reveal a flat surface comprising metal (e. g. Zn) wires embedded in the alumina matrix. Second, it can remove the top region of the alumina layer to ensure uniform distribution of the pores with a desired pore size, spacing and good parallelism. The amount of alumina removed is not critical; however it is preferred that there remains an about 2-10 pLm thick alumina layer to accommodate the following processes.
The metal wires are then etched back from the front surface to form a recess with a desired depth. This recessing process can be performed by a variety of techniques, e. g. reactive-ion etching or selective chemical etching. An electrochemical polishing technique is preferred, where the front surface of the layer comprising the metal wires is immersed in a suitable electrolyte, such as phosphoric acid, and a positive potential is applied to the address electrode that
is in electrical contact with the metal"wires".
In a specific embodiment to recess Zn wires 3 volumes of ethanol is added to 2 volumes of phosphoric acid to produce the electrolyte used for electropolishing. The electropolishing of Zn wires can be performed with the electrolyte temperature maintained at 20° C and at a current density of 5-7 mA/cm for a required period of time to remove uniformly a pre-determined depth of Zn wires. For typical pore sizes of 0.16 to 0.2 micron diameter in zinc, this depth is suitably 0.16 to 0.5 micron. The actual amount removed should be greater than this due to the swelling which occurs on oxidation.
The actual amount is typically 0.2 to 1.5 microns. e) The ends or frontal parts of the metal wires in the pores are then converted into resistive material with a suitable electrical resistivity and dielectric strength. These serve as ballast resistors. It will be appreciated that since they are positioned on the ends or frontal parts of the metal wires (with the lower parts of the wires remaining) the resistors will not be in contact with the address electrode. It will be apparent that the ballast resistors provided by this way are isolated from one emitter site to another thus obviating the cross-talking problem that occurs with laterally continuous ballast resistor layers. The formation of the resistive material may be achieved by oxidation of the metal or other suitable techniques.
An anodisation technique is the preferred method to produce a resistive anodic metal oxide suitable as a ballast resistor. Suitable resistive metal oxides serving as a ballast material produced by anodisation include anodic tin oxide, iron oxide and zinc oxide.
Anodic zinc oxide is preferred, partially because Zn has the advantages of being able to be electroplated and controllable electropolishing. It has also been found that a suitable anodic ZnO can be obtained by repeated anodisation processes in an appropriate
electrolyte such as sodium carbonate. One electrolyte that we have used is 0.5 M Na2C03 solution. The anodisation process is performed in 0.5 M Na2CO3 solution typically with the electrolyte temperature maintained at 15-20 °C. In one embodiment, the first anodisation is performed by stepping up the voltage by a ratio of 1.1-1.2 from an initial voltage of 2-5 V until the voltage reaches 35 V and dwelling after each rise in voltage for 40-50 seconds; the second anodisation is performed in such a way that the voltage is gradually stepped up in the same manner as the first anodisation except that a final voltage is 25 V instead of 35 V, and thereafter the anodisation at the final voltage of 25 V is maintained for a period of 10-15 minutes; the third anodisation is carried out in the same way as the second anodisation. It appears important that a low current density typically 1-2 mA/cm2 at the final voltage of 25 V in the third anodisation process should be observed. Preliminary results show that ZnO obtained from pure Zn substrates can withstand a voltage up to 70V and has a resistance of up to approximately 1 Mohm for an area of 1 mm2, which leads to a current density of about 4 mA/cm2 or more when operated at 40 V. It will be noted that the resistance of the anodic ZnO may be tuned by varying the anodisation conditions, e. g. anodisation voltage and time. Thus the anodic ZnO produced is suitable as a ballast resistor for emitters operated at the required voltage range, typically 20-60 V. Work performed on Zn electroplated in individual pores, mechanically polished, electrochemically etched, and then anodised, has shown. that resistances of 109-10to ohms per pore can be obtained at 50V with a breakdown strength sufficient to withstand 50V and, typically, 70V. In this connection it will be appreciated that the volume of the oxide is greater than that of the metal from which it is derived. Thus the height of the oxide layer in the pore is greater
than that of the metal. This has to be taken into account when determining the height of the metal in the pore. Typically each step is 1.05 to 1.25 times that of the previous step. For example once the voltage has reached 10V that voltage is maintained for, say, 40 seconds and then raised to 10.5 to 12.5V. Typical dwell times at each voltage are 10 secs. to 5 minutes.
It will be understood that up to this stage resistive material is individually positioned down each pore on the top of the metal wire which remains and which is in electrical contact with the address electrode via a buffer layer if present. The depth in the pores after the formation of the resistive material should be suitable for a metal tip to be produced on top. This tip can be shaped and/or be in the form of a cone. The metal for the tip is typically molybdenum.
The following processing steps, such as grid layer deposition (step pore wall undercutting, emitter cone formation and capping layer removal, can be carried out largely as in W096/06443. A brief description is given here for the sake of completeness: g) If desired, deposition of a thin metal layer as a grid layer on the front surface of the metal oxide layer. The preferred grid metals include Nb and Ni although a similar metal (e. g. Ti, Cr) may be used. The grid layer can be deposited by vacuum deposition, e. g. electron-beam evaporation. The thickness of the grid layer is typically 15 to 100, for example 30 to 50, nm; it can be deposited in stripes perpendicular to the address electrode stripes (if present) for matrix addressing. h) Pore wall undercutting, e. g. 10 to 30 nm for a 160-200 nm pore-see step 6 of W096/06443. The structure is typically immersed in a solution of 2 g KOH in 100 ml water for a pre-determined period of
time, typically 5 to 10 minutes, to etch away a small amount of pore wall creating an undercut beneath the grid layer. This processing step is designed to minimise/eliminate unwanted metal deposition on the device cavity wall during the grid layer deposition and a following emitter cone formation process. i) Formation of the Spindt-type emitter cone-see step 7 of W096/06443. Emitter cones can be fabricated in the pore cavities via a well-established Spindt process. Electron-beam evaporation technique is can be used. In one example, for an aperture size of 160 nm, a 400-600 nm Mo capping layer is sufficient to form the emitter cones. j) Removal of metal capping layer. The metal capping layer (e. g. Mo) deposited on the grid surface during emitter cone formation can be removed to reveal the emitter cones. In one preferred embodiment, the removal is performed using anodic dissolution in an electrolyte made from 4 volumes sulphuric acid and 3 volumes water via an electrical contact to the grid layer.
Sometimes, it may be desirable to add further processing steps to clean the pore walls in order to reduce the incidence of short circuits.
In another embodiment of the present invention stacked, multiple ballast resistors that are connected in series are formed instead of a single ballast resistor, for each field emitter. With particular reference to the field emitter devices based on a porous alumina layer, a multiple ballast resistor structure can be obtained by using repeated metal electroplating into the pores and anodising the metal into resistive metal oxide after each electrodeposition. In this way the structure shown in Figure 2 can be produced i. e. with two ballast resistors, 6, formed in each pore.
More than two ballast resistors can be formed if desired. It should be noted that in this embodiment the electropolishing step should remove enough metal so that after subsequent anodisation there is still sufficient space at the top of the pore to
a) fill the pore by electroplating, b) mechanically polish the surface, c) etch back a portion of the metal, d) anodise the metal and e) fabricate the Spindt microtip emitter. The purpose of having more than one ballast resistor is to reduce still further the chance of short circuiting. Alternatively, for this purpose, after forming the resistive layer a plug of metal, for example nickel, may be deposited on top of it so as to put the resistive oxide layer somewhere in the depth of the pore covered by another metal. This can be done so that the metal acts as a barrier, stopping attack of the oxide during subsequent processing, or because the top layer of metal is more amenable to further processing, or because the plug stops Zn vapour leaving the pore if high temperature processing is required. Ni, for example, has a significantly lower vapour pressure at the likely processing temperatures than zinc.
The improved ballast resistor structure for field emitters in accordance with the present invention offers the advantages of minimising/eliminating short circuits hence reducing breakdown risks, coupled with good homogenisation of the electron emission. It will be appreciated that it is a"self-healing"process in that any of the metal used to form the ballast resistor exposed to the electrolyte during processing will be anodised thereby limiting current flow and thus making the process far less susceptible to"pin holes".