FIFO BUFFER AND METHOD OF CONTROLLING FIFO BUFFER

WIPO Patent Application WO/2011/058659

A1

A FIFO buffer (1) comprises a packet storage buffer (10), a bank switch (17), a packet write control circuit (15), and a packet write start bank holding FIFO queue (19). The packet storage buffer (10) is capable of writing and reading data within one cycle by combining a plurality of memories which perform either writing or reading of data within one cycle. The bank switch (17) outputs a W_Bank signal indicating a memory which is included in the packet storage buffer (10) and capable of writing data therein. The packet write control circuit (15) controls the memory indicated by the W_Bank signal at the input of data to be written to write the data to be written. The packet write start bank holding FIFO queue (19) holds the W_Bank signal which is outputted from the bank switch (17) in response to the queue write signal of "1" from the packet write control circuit (15) and indicates the memory in which the first one of the data to be written is written.

JP52047641	CONTROL DEVICE OF DATA BUFFER
JP09167076	METHOD AND DEVICE FOR OUTPUT SYNCHRONIZATION
JP01228229	FRAME SYNCHRONIZING SYSTEM

TANEDA, Masahiro (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)

JP2009/069454

May 19, 2011

November 16, 2009

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FUJITSU LIMITED (1-1 Kamikodanaka 4-chome, Nakahara-ku Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
富士通株式会社 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 Kanagawa, 〒2118588, JP)

G06F5/12

KATAYAMA, Shuhei (Mitsui Sumitomo Marine Tepco Building, 6-1 Kyobashi 1-chome, Chuo-ku, Tokyo 31, 〒1040031, JP)

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