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Patent Searching and Data


Title:
FIFO CLOCK DOMAIN CHANGE
Document Type and Number:
WIPO Patent Application WO2004019202
Kind Code:
A3
Abstract:
A data retiming arrangement applies data to be retimed to a delay line. The data is applied concurrently with a data clock applied to a clock multiplexer and to a data counter, and a second clock applied to the clock multiplexer. The counter counts a number of clock cycles equal to the capacity of the delay line, and produces a FULL signal at the incoming data clock rate. The FULL signal is retimed to the reclock rate by a cascade of registers, which produce a retimed FULL Flag. The FULL Flag resets the clock multiplexer to provide the delay line with the retimed clock, and also switches the delay line to read the retimed data at the retime clock rate.

Inventors:
SCHULTZ MARK ALAN (US)
DUFFIELD DAVID JAY (US)
CHIDAMBARAM DINAKARAN (US)
DUNCAN CHRISTOPHER DALE (US)
Application Number:
PCT/US2003/023906
Publication Date:
May 21, 2004
Filing Date:
July 31, 2003
Export Citation:
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Assignee:
THOMSON LICENSING SA (FR)
SCHULTZ MARK ALAN (US)
DUFFIELD DAVID JAY (US)
CHIDAMBARAM DINAKARAN (US)
DUNCAN CHRISTOPHER DALE (US)
International Classes:
G06F5/00; G06F5/06; G06F5/08; (IPC1-7): G06F5/06
Foreign References:
US5592658A1997-01-07
US6209047B12001-03-27
US4771426A1988-09-13
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