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Title:
FILTER FOR HIGH-VOLTAGE POWER CONVERTERS
Document Type and Number:
WIPO Patent Application WO/2018/177532
Kind Code:
A1
Abstract:
The present disclosure relates to a converter arrangement comprising a valve hall 1, a high-voltage power converter 2 contained in the valve hall, a bushing 4 through a wall of the valve hall, a bus-bar 7 connecting the converter to the outside of the valve hall via the bushing, and a high dv/dt filter arrangement 3 connected to the bus-bar inside the valve hall.

Inventors:
ZELAYA DE LA PARRA, Hector (Pingstliljegatan 39, Västerås, 722 46, SE)
SVENSSON, Jan (Tallbackagatan 1A, Västerås, 72346, SE)
DAVIDSSON, Mikael (Råsegelgatan 12, Västerås, 723 48, SE)
CHEN, Nan (Kopparbergsvägen 22 A, Västerås, 722 13, SE)
ALVES, Roberto (Spinnfiskargatan 51, Västerås, 723 49, SE)
Application Number:
EP2017/057680
Publication Date:
October 04, 2018
Filing Date:
March 31, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
ABB SCHWEIZ AG (Brown Boveri Strasse 6, 5400 Baden, 5400, CH)
International Classes:
H02M1/12; H02M7/00; H05K7/14
Foreign References:
US20040120166A12004-06-24
US20140268888A12014-09-18
EP0419230A21991-03-27
CN201878020U2011-06-22
CN203352475U2013-12-18
Other References:
None
Attorney, Agent or Firm:
SAVELA, Reino (ABB AB, Intellectual PropertyForskargränd 7, Västerås, 721 78, SE)
Download PDF:
Claims:
CLAIMS

1. A converter arrangement comprising: a valve hall (l); a power converter (2) contained in the valve hall; a bushing (4) through a wall of the valve hall; a bus-bar (7) connecting the converter to the outside of the valve hall via the bushing; and a high dv/dt filter arrangement (3), connected to the bus-bar inside the valve hall.

2. The converter arrangement of claim 1, wherein the high dv/dt filter arrangement (3) is configured to handle a dv/dt of at least 20 kV^s, e.g. of at least 50 kV^s.

3. The converter arrangement of any preceding claim, further comprising: a low dv/dt filter arrangement (5) connected to the bus-bar (7).

4. The converter arrangement of claim 3, wherein the low dv/dt filter arrangement (5) is positioned inside the valve hall (1).

5. The converter arrangement of claim 4, wherein the low dv/dt filter arrangement (5) is integrated with the high dv/dt filter arrangement (3).

6. The converter arrangement of claim 3, wherein the low dv/dt filter arrangement (5) is positioned outside of the valve hall (1).

7. The converter arrangement of any preceding claim , further comprising an RI reactor (6) connected to the bus-bar (7).

8. The converter arrangement of any preceding claim, wherein the high dv/dt filter arrangement (3) comprises an LRC filter.

9. The converter arrangement of any preceding claim, wherein the converter has an MMC topology, e.g. for FACTS applications such as comprising a STATCOM.

10. The converter arrangement of claim 9, wherein the high dv/dt filter arrangement (3) comprises a plurality of sub-reactors (1), whereby each converter cell (61), comprising a plurality of valves (62) and a capacitor arrangement (63), of the MMC (2) is connected in series with at least one of said sub-reactors on each side of the cell.

11. The converter arrangement of claim 10, wherein the high dv/dt filter arrangement (3) comprises a plurality of sub-capacitors (c) and a plurality of sub-resistors (r), whereby for each of the converter cells (61) at least one of the sub-capacitors and at least one of the sub-resistors is connected across the at least one of said sub-reactors on each side of the cell.

12. The converter arrangement of claim 11, wherein the at least one of the sub-capacitors (c) and at least one of the sub-resistors (r) is connected across the capacitor arrangement (63) of the cell (61).

13. The converter arrangement of claim 11, wherein the at least one of the sub-capacitors (c) and at least one of the sub-resistors (r) is connected across each other and across each half cell of the cell (61).

Description:
FILTER FOR HIGH-VOLTAGE POWER CONVERTERS

TECHNICAL FIELD

The present disclosure relates to a voltage filter arrangement for high-voltage power converters, especially for FACTS applications. BACKGROUND

High-power high-voltage converters commonly use the well-known topology of Modular Multilevel Converters (MMC). In this configuration a series connection of converter cells are used to build up the voltage that is required at the Point of Common Coupling (PCC). For high-voltage high-power converters, like Static Synchronous

Compensator (STATCOM) in Flexible Alternating Current Transmission System (FACTS) applications, using silicon (Si) semiconductors, the converter B2 (valves and capacitors) is located in a valve hall Bi as illustrated in figure l. The converter B2 of figure ι is illustrated by a single phase leg, comprising an upper arm B2a and a lower arm B2b, but typically three such phase legs are present, in a three-phase converter. The three-phase bus-bars By out from the converter are connected to the phase reactors B5 outside the valve hall in the AC yard. Wall bushings B4 are used to connect the bus-bars in the valve hall with the bus-bars in the AC yard. Normally, to reduce the Electro-Magnetic Interference (EMI), a radio-interference (RI) reactor/filter B6 is added to the reactor B5 to limit the EMI. Although only one bus-bar By, bushing B4, RI reactor B6 and reactor B5 are shown schematically in the figure, it is understood that for a three-phase converter B2 there are three of each, one for each phase. SUMMARY

High-power high-voltage converters are usually located in a valve hall and efforts are made to avoid any electro-magnetic disturbances coming out of the valve hall (either by radiation or by conduction), e.g. by means of RI reactors. As the switching speed of silicon carbide (SiC) semiconductors becomes much faster compared with Si semiconductors, the expected dv/dt (voltage change per unit of time) will reach higher values, resulting in higher electro-magnetic interference (EMI).

To manage the standards of allowed EMI, the electro-magnetic disturbances utilizing SiC semiconductors in the converter valves need to be mitigated from a higher disturbance level compared with utilizing Si semiconductors.

The high dv/dt due to use of SiC semiconductors will affect the whole converter with its parts and the devices connected to the converter. For instance, the high dv/dt values will affect the design of the phase reactors as these will have to be designed to cope with the very short rise- and fall-times of each switching instant of the converter. High dv/dt will stress the wall bushing connecting the valve hall with the AC yard. Furthermore, the accepted levels in the EMI standards is difficult to reach when the reactor is located in the AC yard.

The present invention provides embodiments for limiting the challenging high dv/dt stress to the proposed filter arrangement. Thus, in addition to the high dv/dt capable filter arrangement, the conventional phase reactors and wall bushings may still be used without changing their design to a higher cost version.

According to an aspect of the present invention, there is provided a converter arrangement comprising a valve hall, a high-voltage power converter contained in the valve hall, a bushing through a wall of the valve hall, a busbar connecting the converter to the outside of the valve hall via the bushing, and a high dv/dt filter arrangement connected to the bus-bar inside the valve hall. By means of the high dv/dt filter arrangement being arranged inside of the valve hall, the EMI outside of the valve hall, e.g. in an Alternating Current (AC) yard, is reduced. The filter is typically designed to damp the amplitude of high frequency components to fulfil requirements of standards. It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of "first", "second" etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

Fig 1 is a schematic block diagram of an embodiment of a converter arrangement according to prior art.

Fig 2 is a schematic block diagram of an embodiment of a converter arrangement according to the present invention. Fig 3 is a schematic illustration of an embodiment of a reactor having a part configured for high dv/dt and another part configured for low dv/dt, in accordance with embodiments of the present invention.

Fig 4 is a schematic block diagram of another embodiment of a converter arrangement according to the present invention. Fig 5 is a schematic circuit diagram of an embodiment of a three-phase filter arrangement for high dv/dt, in accordance with the present invention.

Fig 6 is a schematic illustration of an embodiment of a high dv/dt filter arrangement applied to an MMC phase leg, in accordance with the present invention.

Fig 7 is a schematic illustration of another embodiment of a high dv/dt filter arrangement applied to an MMC phase leg, in accordance with the present invention.

Fig 8 is a schematic illustration of another embodiment of a high dv/dt filter arrangement applied to an MMC phase leg, in accordance with the present invention.

DETAILED DESCRIPTION

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description. With reference to figure 2, embodiments of a converter arrangement of the present invention include use of a filter arrangement 3, typically being or comprising a reactor, adapted to handle voltage pulses with high dv/dt that is physically placed within the valve hall 1, preferably as close as possible to the converter 2. The converter 2 may be any high- or medium-voltage converter, e.g. an AC-AC converter and/or an MMC, for instance for FACTS applications e.g. including a STATCOM. A high/medium- voltage converter of the present disclosure implies that it has a voltage rating of at least 1 kV, typically at least 10 kV or at least 50 kV, e.g. up to yokV. The converter may e.g. be a

STATCOM for FACTS, but any other suitable converter type may beneficially be used with embodiments of the present invention, e.g. a medium voltage drive. In the embodiment of figure 2, the converter 2 may be an MMC

STATCOM in which one of three phase legs is schematically shown, each phase leg comprising an upper phase arm 2a and a lower phase arm 2b. A bus-bar 7, typically one per phase leg of the converter, connects the converter 2 to the outside of the valve hall 1, e.g. an AC yard, via a bushing 4 through a wall of the valve hall. The filter arrangement takes care of damping the high rate of changes in the voltage pulses produced by SiC semiconductors in the valves of the converter. The filter arrangement 3, especially the reactor therein, needs to handle high dv/dt in order not to break down (insulation failure).

Placing the dv/dt filter arrangement 3 inside the valve hall may result in a need for a larger valve hall 1 since the filter/reactor with its clearance distance will be placed inside the valve hall. Thus, there may be a trade-off between the beneficial effects of placing the filter arrangement inside the valve hall and the higher cost of the larger valve hall.

In order to reduce the cost of the filter arrangement, only a part of the filter arrangement for the converter 2 may need to handle the high dv/dt without damaging the insulation of the filter arrangement. The other part, a low dv/dt filter arrangement 5, may have lower dv/dt requirements. Herein, a high dv/dt may be at least 20 kV^s, e.g. at least 50 kV^s such as within the range of 50-100 kV^s which may be typical for SiC semiconductor switches, while a low dv/dt may be below 20 kV^s, e.g. 5-10 kV^s. Thus, in some

embodiments, the filter arrangement of the converter arrangement may comprise a high dv/dt filter arrangement 3, e.g. consisting of or comprising a reactor, and a low dv/dt filter arrangement 5, e.g. consisting of or comprising a reactor, connected in series with the high dv/dt filter arrangement to and along the bus-bar 7.

The two series connected filter arrangements 3 and 5, of which one handles high dv/dt and the other has a lower dv/dt capability, may in some

embodiments be integrated with each other, e.g. to reduce its bulkiness. For instance, a reactor of the low dv/dt filter arrangement 5 may be integrated with a reactor of the high dv/dt filter arrangement 3, essentially being designed as one combined reactor L, as illustrated in figure 3. This reactor L has a part that handles high dv/dt, having a different design than the low dv/dt filter to avoid insulation failure, e.g. having a relatively less dense winding. To design reactors L, including reactor windings, for different dv/dt requirements is in itself a standard procedure for persons skilled in the art.

In some embodiments, e.g. if the high dv/dt filter arrangement 3 is able to reduce the EMI of the bus-bar 7 to levels which are similar to those produced when using regular Si semiconductors instead of SiC semiconductors in the converter 2, the low dv/dt filter arrangement 5 may be a filter arrangement, e.g. a reactor, which is conventionally used today as phase reactor. In some embodiments, the low dv/dt filter arrangement 5 may be positioned outside of the valve hall 1 (e.g. in the AC yard), as shown in figure 4, which would reduce the size requirement of the valve hall (reducing cost). To increase the attenuation of electromagnetic compatibility (EMC) and EMI, and to damp out oscillations due to resonances, the high dv/dt reactor L of the filter arrangement 3 may in some embodiments be complemented with passive resistor R and capacitor C filter components (L, R, C), e.g. as shown in figure 5, illustrating an embodiment of a high dv/dt LRC filter

arrangement 3 for a three-phase system, connected between each of the three bus-bars 7a, 7b and 7c and ground to damp high dv/dt waveforms inside the valve hall 1. In the embodiment of figure 5, the capacitor arrangement C of the high dv/dt filter arrangement 3 comprises at least one capacitor element Ca, Cb and Cc, respectively, connected in series with at least one resistor element, Ra, Rb and Rc, respectively, between respective bus-bars (7a, 7b and 7c) and ground at respective reactor elements La, Lb and Lc of the bus-bars. An LRC filter 3 is herein defined as a filter comprising a reactor element L as well as a resistor element R and a capacitor element C, typically at least one per phase, each of which may in some embodiments be divided into a plurality of sub-elements, such as sub-reactors, sub-resistors and sub- capacitors. Note that the displayed filter configuration is an example of possible layouts. The filter 3 may be any combination of the L, R and C elements connected between the bus-bars 7 and ground.

As mentioned above and with reference to figure 6, embodiments of the present invention may preferably be used with a converter comprising an MMC topology. An MMC comprises a plurality of series-connected (also called cascaded or chain-linked) converter cells 61, each cell comprising a plurality of semiconductor switches (valves) 62 and a capacitor arrangement 63 (or other energy storage arrangement). The switches 62 of each cell 61 may e.g. form a half-bridge topology by means of two switches or a full-bridge topology by means of four switches as in the example of figure 6 in which an MMC phase leg of a STATCOM is schematically shown. The phase leg is connected via two bus-bars 7 (the number of bus-bars depends on the topology of the MMC in question, which is obvious to a person skilled in the art). In the embodiment of figure 6 and in conformity with the preceding discussion, a high dv/dt filter arrangement 3 in the form of an LRC filter is connected to each of the bus-bars 7 between the converter 2 and the respective the bushing 4. Again, the filter 3 may be any combination of L, R and C elements. An optional low dv/dt filter arrangement 5 (e.g. a

conventional phase reactor) may be connected to each bus-bar 7, in series with and on the far side from the converter 2 of the high dv/dt filter arrangement 3. The low dv/dt filter arrangement 5 may also be located within the valve hall 1, separate from or integrated with the high dv/dt filter arrangement 3, but preferably the low dv/dt filter arrangement may be positioned outside of the valve hall, as shown in figure 6, to reduce the size requirement of the valve hall, especially if the high dv/dt filter arrangement 3 has been able to reduce the levels of EMI to the regular levels produced by a conventional Si-based converter, as also discussed above. Further, a conventional RI reactor 6 may be connected to each bus-bar 7, in series with the high dv/dt filter arrangement 3, typically outside of the valve hall 1, e.g. between the high dv/dt filter arrangement and the low dv/dt filter

arrangement 5 such as between the bushing 4 and the low dv/dt filter arrangement 5. Although typically each bus-bar 7 of a converter arrangement is provided with a high dv/dt filter arrangement 3, as well as any low dv/dt filter arrangement 5 and/or RI filter 6, there may be embodiments where at least one, but less than all, bus-bars 7 is such provided. An MMC 2 has, as mentioned above, a number of (any suitable number of) series-connected converter cells 61. Each of the cells has two phase legs (if it is a full-bridge cell) that produces voltage pulses. For SiC semiconductors, the rise- and fall-time of the voltage pulses creates high dv/dt. In some

embodiments, the high dv/dt filter arrangement 3 may be integrated with each cell 61, rather than being a discrete unit connected between the converter 2 and the bushing 4, while still preferably also being connected to the bus-bar 7 at one end of the filter arrangement 3. When inserting a filter arrangement 3 in each converter cell to damp the high dv/dt pulses, a low dv/dt filter arrangement 5 ( e.g. a phase reactor with lower dv/dt capability) may be used in the same way as discussed above for embodiments where the high dv/dt filter arrangement is not integrated with each converter cell.

Figures 7 and 8 illustrates two different example embodiments of the high dv/dt filter arrangement 3 integrated with the converter cells 61. Note that different filter configurations may be used and the ones in figure 7 and 8 are mere examples of how embodiments of the high dv/dt filter arrangement 3 may be implemented.

In the embodiments of figures 7 and 8, the high dv/dt filter arrangement 3 is distributed and integrated with the cells 61 of the MMC 2 phase leg such that it is connected to the two bus-bars 7, one at each respective end of the filter arrangement 3 (a first end of the filter arrangement 3 is connected to a first of the two bus-bars 7, and a second end of the filter arrangement 3 is connected to a second of the two bus-bars 7. In the distributed filter arrangement 3, the reactor element L comprises a plurality of sub-reactors 1, the resistor element R comprises a plurality of sub-resistors r, and the capacitor element C comprises a plurality of sub-capacitors c. The sub-reactors 1 are connected in series with the converter cells 61 such that each cell 61 of the MMC 2 phase leg has at least one of said sub-reactors connected to either side of the cell (between the cell and its neighbouring cell, if there is another cell connected in series to that side of the cell, or to a bus-bar 7, if the cell is an end cell in the phase leg and does not have another cell connected in series to that side of the cell). There is thus at least one sub-reactor 1 connected in series between each two neighbouring chain-linked cells 61, as well as at either end of the chain-link. In the embodiments of figures 7 and 8, each cell 61 in the chain link of series connected cells has one sub-reactor 1 series connected on either side of the cell which are exclusively associated with the cell, whereby there are two series connected sub-reactors 1 connected in series with and between every two neighbouring (adjacent) cells in the chain -link. The sequence of series connected cells 61 and sub-reactors 1 along the chain- linked MMC phase leg may thus be: bus-bar - 1 - 61 - 1 - 1 - 61- 1 - ... - 1 - 61 - 1 - 1 - 61 - 1 - bus-bar

In the embodiment of figure 7, the LRC filter arrangement is connected in series at the output of each half-cell of the converter leg, such that at least one of the sub-resistors r and at least one of the sub-capacitors c is connected in parallel with (across) each other and across each half cell, a half cell typically comprising two of the four semiconductor switches forming the full-bridge topology of the cell, or (put another way) one of the two semiconductor legs forming the full-bridge topology of the cell.

Alternatively, as shown in figure 8, at least one of the sub-resistors r and at least one of the sub-capacitors c may be connected in parallel with (across) each other and across each of the cells 61 (each whole cell, in contrast to each half cell as in figure 7) in the MMC phase leg chain-link. Thus, said at least one sub-resistor r and at least one sub-capacitor c may for each cell 61 be connected to the chain-link on the distal sides (i.e. the sides facing away from the cell) of the sub-reactors 1 associated with the cell, to either side of the cell, whereby said at least one sub-resistor r and at least one sub-capacitor c are connected across also said sub-reactors 1 associated with the cell. The embodiments of figures 7 and 8 are examples of a distributed filter design. In one case (figure 8) the filter components are connected across the complete cell and in the other (figure 7) the filters are divided on each half of the cell. Below follow some embodiments of the present invention

In some embodiments of the present invention, the high dv/dt filter arrangement 3 is configured to handle a dv/dt of at least 20 kV^s, e.g. of at least 50 kV^s.

In some embodiments of the present invention, the converter arrangement further comprises a low dv/dt filter arrangement 5 connected to the bus-bar 7. In some embodiments, the low dv/dt filter arrangement 5 is positioned inside the valve hall 1. In some embodiments, the low dv/dt filter

arrangement 5 is integrated with the high dv/dt filter arrangement 3. In some other embodiments, the low dv/dt filter arrangement 5 is positioned outside of the valve hall 1.

In some embodiments of the present invention, the converter arrangement further comprises an RI reactor 6 connected to the bus-bar 7.

In some embodiments of the present invention, the high dv/dt filter arrangement 3 comprises an LRC filter. In some embodiments of the present invention, the converter has an MMC topology, e.g. for FACTS applications such as comprising a STATCOM. In some embodiments, the high dv/dt filter arrangement 3 comprises a plurality of sub-reactors 1, whereby each converter cell 61, comprising a plurality of valves 62 and a capacitor arrangement 63, of the MMC 2 is connected in series with at least one of said sub-reactors 1 on each side of the cell.

In some embodiments of the present invention, the high dv/dt filter arrangement 3 comprises a plurality of sub-capacitors c and a plurality of sub-resistors r, whereby for each of the converter cells 61 of the MMC 2 at least one of the sub-capacitors c and at least one of the sub-resistors r is connected across the at least one of said sub-reactors 1 on each side of the cell. In some embodiments, the at least one of the sub -capacitors c and at least one of the sub-resistors r is connected across the capacitor arrangement 63 of the cell 61. In some other embodiments, the at least one of the sub- capacitors c and at least one of the sub-resistors r is connected across each other and across each half cell of the cell 61.

The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.