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Title:
FILTER LAYER FOR AN IN-PLANE TOP SYNTHETIC ANTIFERROMAGNET (SAF) STACK FOR A SPIN ORBIT TORQUE (SOT) MEMORY
Document Type and Number:
WIPO Patent Application WO/2019/135743
Kind Code:
A1
Abstract:
A memory device comprises an interconnect having a spin orbit torque (SOT) material. A magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet. A material stack is on the MTJ device, wherein the material stack comprises a spacer material, a pinned fixed magnet, an antiferromagnet, and a multilayer filter located within the material stack, wherein the multilayer filter is configured to reduce effects of manganese diffusion from the antiferromagnet.

Inventors:
OGUZ, Kaan (210 NW 209th Avenue, Beaverton, Oregon, 97006, US)
O'BRIEN, Kevin P. (1314 NW Irving Street #503, Portland, Oregon, 97209, US)
DOCZY, Mark (16985 SW Ledgestone Drive, Beaverton, Oregon, 97007, US)
KUO, Charles C. (33224 Arizona Street, Union City, California, 94587, US)
ALLEN, Gary (13952 NW Meadowridge Dirve, Portland, Oregon, 97229, US)
Application Number:
US2018/012240
Publication Date:
July 11, 2019
Filing Date:
January 03, 2018
Export Citation:
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Assignee:
INTEL CORPORATION (2200 Mission College Boulevard, Santa Clara, California, 95054, US)
OGUZ, Kaan (210 NW 209th Avenue, Beaverton, Oregon, 97006, US)
O'BRIEN, Kevin P. (1314 NW Irving Street #503, Portland, Oregon, 97209, US)
DOCZY, Mark (16985 SW Ledgestone Drive, Beaverton, Oregon, 97007, US)
KUO, Charles C. (33224 Arizona Street, Union City, California, 94587, US)
ALLEN, Gary (13952 NW Meadowridge Dirve, Portland, Oregon, 97229, US)
International Classes:
G11C11/16; H01L43/08
Attorney, Agent or Firm:
SULLIVAN, Stephen, G. et al. (Schwabe, Williamson & Wyatt P.C.,1211 SW 5th Avenue, Suite 190, Portland Oregon, 97204, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. A memory device, comprising:

an interconnect having a spin orbit torque (SOT) material;

a magnetic tunnel junction (MTJ) device having a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet; and

a material stack on the MTJ device, the material stack comprising:

a spacer material,

a pinned fixed magnet,

an antiferromagnet, and

a multilayer filter located within the material stack, the multilayer filter configured to reduce effects of manganese diffusion from the antiferromagnet.

2. The memory device of claim 1, wherein the pinned fixed magnet comprises a first pinned fixed magnet and a second pinned fixed magnet, the multilayer filter comprises:

a first diffusion barrier on the first pinned fixed magnet;

a ferromagnetic cobalt-based alloy on the first diffusion barrier; and

a second diffusion barrier on the cobalt-based alloy.

3. The memory device of claim 2, wherein the multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet.

4. The memory device of claim 2, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet, and the spacer material is located between the first the pinned fixed magnet and the second pinned fixed magnet.

5. The memory device of claim 2, wherein the multilayer barrier filter comprises a first multilayer barrier filter, the memory device further comprising a second multilayer barrier filter, wherein the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet, and the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.

6. The memory device of claim 2, wherein the first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 1 nm.

7. The memory device of claim 2, wherein the first diffusion barrier and the second diffusion barrier comprise any heavy metal that acts as a barrier to manganese diffusion.

8. The memory device of claim 7, wherein the heavy metal comprises at least one of tantalum, tantalum oxide, tungsten, iridium, and molybdenum, and the first diffusion barrier and the second diffusion barrier have a thickness of approximately .1 to .5 nm.

9. The memory device of claim 2, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.

10. The memory device of claim 1, wherein the multilayer barrier filter comprises a ferromagnetic cobalt-based alloy and a diffusion barrier on the multilayer barrier filter.

11. The memory device of claim 10, wherein the multilayer barrier filter is located between the spacer material and the pinned fixed magnet.

12. The memory device of claim 10, wherein the diffusion barrier comprises tantalum or tantalum oxide, and the spacer material comprises ruthenium or iridium.

13. The memory device of claim 10, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to 3 nm.

14. A memory device, comprising:

an interconnect having a spin orbit torque (SOT) material and a write electrode;

a magnetic tunnel junction (MTJ) device having a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet; and

a material stack on the MTJ device, the material stack comprising:

a spacer material,

a first pinned fixed magnet,

a second pinned fixed magnet; and

an antiferromagnet, and

a multilayer filter located within the material stack, the multilayer filter comprising;

a first diffusion barrier on the first pinned fixed magnet;

a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.

15. The memory device of claim 14 wherein multilayer filter is located between the first pinned fixed magnet and the second pinned fixed magnet.

16. The memory device of claim 14, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet, and the spacer material is located between the first pinned fixed magnet and the second pinned fixed magnet.

17. The memory device of claim 14, wherein the multilayer barrier filter comprises a first multilayer barrier filter, the memory device further comprising a second multilayer barrier filter, wherein the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet, and the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.

18. The memory device of claim 14, wherein the first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 1 nm.

19. The memory device of claim 14, wherein the first diffusion barrier and second diffusion barrier comprise any heavy metal that acts as a barrier to manganese diffusion.

20. The memory device of claim 19, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.

21. The memory device of claim 14, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.

22. A method of fabricating an integrated circuit device, the method comprising:

forming a SOT interconnect with a write electrode in an opening in a dielectric layer; forming a MTJ material stack on the SOT interconnect, and forming a material layer stack having a multilayer barrier filter over the MTJ material stack; performing a lithography step that forms a photoresist mask on an uppermost surface of the material layer stack;

patterning the material layer stack and the MTJ material stack in alignment with the photoresist mask to form a memory device; and

depositing a second dielectric layer over the memory device and patterning another interconnect line over the second dielectric layer.

23. The method of claim 22, further comprises forming the multilayer barrier filter with: a first diffusion barrier;

a ferromagnetic cobalt-based alloy on the first diffusion barrier; and

a second diffusion barrier on the cobalt-based alloy.

24. The method of claim 23, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.

25. The method of claim 23, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.

Description:
FILTER LAYER FOR AN IN-PLANE TOP SYNTHETIC ANTIFERROMAGNET (SAF) STACK FOR A SPIN ORBIT TORQUE (SOT) MEMORY

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, a filter layer for an in-plane top SAF stack for a SOT memory.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

Non-volatile embedded memory, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, leading embedded memory options such as spin torque transfer magnetoresistive random access memory (STT-MRAM) can suffer from high voltage and high current-density problems during the programming (writing) of the cell. Furthermore, the density limitations of STT-MRAM may be due to large write switching current and select transistor requirements. Specifically, traditional STT-MRAM has a cell size limitation due to the drive transistor requirement to provide sufficient spin current. Furthermore, such memory is associated with large write current (>100 mA) and voltage (>0.7 V) requirements of conventional magnetic tunnel junction (MTJ) based devices.

As such, significant improvements are still needed in the area of non-volatile memory arrays based on MTJs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A illustrates a typical material stack for a SOT (spin orbit torque) based MTJ (Magnetic Tunnel Junction) MRAM having a top synthetic anti-Ferro-magnet (SAF) stack with in-plane anisotropy, according to one embodiment.

FIG. 1B is a top view of the device of FIG. 1A.

FIG. 1C is a cross-section of the SOT layer that shows direction of spin currents and charge currents as decided by SOT in metals. FIG. 2 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a first embodiment.

FIG. 3 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a second embodiment.

FIG. 4 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a third embodiment.

FIG. 5 illustrates a material stack for a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a fourth embodiment.

FIG. 6 is a flow diagram representing various operations in a method of fabricating a SOT MTJ memory device with a multilayer barrier filter in accordance with the embodiments disclosed herein.

FIGS. 7A and 7B illustrate a wafer composed of semiconductor material and that includes one or more dies having integrated circuit (IC) structures formed on a surface of the wafer.

FIG. 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter.

FIG. 9 illustrates a computing device in accordance with one implementation of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

Embodiments for a filter layer for an in-plane top SAF stack for a SOT memory are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well- known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the FIGS are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”,“below,”“botom,” and“top” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL)

semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are paterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL)

semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modem IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or embodiments of the present invention is directed to one or more filter layers for an in-plane top SAF MJT stack for a Spin Orbit Torque (SOT) MRAM. General applications of such an array include, but are not limited to, embedded memory, magnetic tunnel junction architectures, MRAM, non-volatile memory, spin hall effects, spin torque memory, and embedded memory using magnetic memory devices. In one embodiment, MTJ based SOT MRAM utilizing the disclosed filter layers reduces diffusion of elements in the SAF stack.

More specifically, one or more embodiments target the use or application of a SOT MRAM having a filter layer comprising one or more layers. In a first aspect, a memory device comprises an interconnect having a spin orbit torque (SOT) material. A magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet. A material stack is on the MTJ device, wherein the material stack comprises a spacer material, a pinned fixed magnet, and an antiferromagnent. A multilayer filter is located within the material stack, wherein the multilayer filter is configured to reduce effects of diffusion of an element, such as manganese, from the antiferromagnet.

In order to provide context, FIG. 1 A illustrates a typical material stack for a SOT (spin orbit torque) based MTJ (Magnetic Tunnel Junction) MRAM having a top synthetic anti-Ferro- magnet (SAF) stack with in-plane anisotropy, according to one embodiment. As is well known, the MTJ device stack stores data as a resistance state value. The MTJ device stack comprises two independent ferromagnetic layers referred to as a free layer nanomagnet (FM1) and a reference fixed magnet (FM2) that are separated by an insulating tunneling barrier material. The barrier material should be sufficiently thin (e.g., < 1 nm) such that electrons can tunnel there through. The magnetic field of the fee layer magnet FM1 is free to rotate based on a direction of a current, i.e., the spin of the electrons, flowing through the MTJ device stack. In contrast, the reference fixed magnet FM2 has a fixed magnetization, and is therefore referred to as a fixed or reference layer.

In certain aspects and in at least some embodiments of the present invention, certain terms hold certain definable meanings. For example, the“free” layer magnetic layer is a magnetic layer storing a computational variable. A“fixed” magnetic layer is a magnetic layer with fixed magnetization (magnetically harder than the free magnetic layer). A barrier material, such as a tunneling dielectric or oxide layer (e.g., MgO), is one located between free and fixed magnetic layers. The free layer and the fixed layer may be ferromagnetic layers.

In an embodiment, the MTJ functions essentially as a resistor, where the resistance of an electrical path through the MTJ may exist in two resistive states, either“high” or“low,” depending on the direction or orientation of magnetization in the free layer magnet FM1 and in the fixed magnet FM2. In the case that the directions of magnetization in the free layer magnet FM1 and the fixed magnet FM2 closest to it are substantially opposed or anti-parallel with one another, a high resistive state exists. In the case that the directions of magnetization in the coupled free magnetic layers and the fixed layer magnet FM1 closest to it are substantially aligned or parallel with one another, a low resistive state exists. It is to be understood that the terms“low” and“high” with regard to the resistive state of the MTJ are relative to one another.

In other words, the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa. Thus, with a detectible difference in resistance, the low and high resistive states can represent different bits of information (i.e. a“0” or a“1”). The top synthetic antiferromagnet (SAF) stack includes a non-magnetic spacer material (Ruthenium or Iridium) and a pinned fixed magnet (FM3). The material stack further includes and an antiferromagnetic (AFM). The magnetization of the pinned fixed magnet FM3 is fixed through exchange coupling with the antiferromagnetic AFM. The SAF stack allows for cancelling the dipole fields around the free layer FM1. A top electrode completes the material stack.

A wide combination of materials can be used for material stacking of the MTJ device and SAF stack. For example, in one embodiment, the free layer magnet FM1, the reference fixed magnet FM2, and the pinned fixed magnet FM3 may comprise Co x FeyB z (Cobalt, Iron, Boron), where‘x,’‘y,’ and‘z’ are integers. The barrier material typically comprises an oxide layer such as magnesium oxide (MgO), and the spacer material typically comprises RU (Ruthenium) or IR (Iridium). The antiferromagnet (AFM) is manganese based and may comprise IrMn (iridium manganese) or PtMn (platinum manganese). The free layer magnet FM1 may have a thickness of approximately 2 to 3 nanometers, while the spacer Ru layer may have a thickness of

approximately .9 nanometers, for example. In other embodiments, other materials may be used to form the MTJ device.

The free layer magnet FM1 of the material stack is in direct contact with an SOT interconnect having a write electrode. Both the SOT interconnect and the write electrode may comprises a Giant Spin Hall Effect (GSHE) metal made of b-Tantalum (b-Ta), b-Tungsten (b- W), Pt, Copper (Cu) doped with elements such as Iridum, bisumuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table. In one embodiment, the write electrode transitions into a normal high conductivity metal (e.g., Cu) to minimize write electrode resistance.

FIG. 1B is a top view of the device of FIG. 1A. In FIG. 1B, the magnet is oriented along the width of the write electrode for appropriate spin injection. The magnetic cell is written by applying a charge current via the write electrode. The direction of the magnetic writing is decided by the direction of the applied charge current. Positive currents (along+y) produce a spin injection current with transport direction (along+z) and spins pointing to (+x) direction.

Because what is known as the Spin Hall Effect may be responsible for the current- induced magnetization switch in the MTJ device, an SOT- MRAM may also be referred to as a Giant Spin Hall Effect (GSPHE) MRAM.

FIG. 1C is a cross-section 240 of the SOT layer that shows direction of spin currents and charge currents as decided by SOT in metals. The injected spin current in-tum produces spin torque to align the magnet in the +x or -x direction. The transverse spin current for a charge current in the write electrode is provided in equation (1): Is = Pshe(w,t, sf,OsHE)(oxIc) (1) where PSHE is the spin hall injection efficiency, which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of the GSHE metal electrode, Sf is the spin flip length in the GSHE metal, OGSHE is the spin hall angle for the GSHE-metal to FM1 interface. The injected spin angular momentum responsible for spin torque can be determined by first solving equation 1.

While the SOT stack offers several advantages over devices such as a spin transfer torque (STT) MRAM, the SOT stack has a problem with manganese diffusion when the stack is annealed above 300 C. Manganese typically starts to defuse at 300 C, and the diffusion becomes problematic in the SOT stack at 350 C. If the SOT stack is to be implemented in a CMOS process, then the SOT stack needs to survive temperatures approaching 400 C. Once the manganese starts to diffuse, the magnetic properties of the material stack from the AFM to the reference layer FM2 starts to deteriorate. Consequently, high annealing temperatures cause the top SAF stack to suffer from low exchange bias between the AFM and the SAF and a reduction in tunnel magnetoresistance (TMR) due to high magnesium diffusion from the AFM. For example, the manganese diffusion may result in a low exchange bias in terms of yield of approximately 500 oersted and low TMR of less than 100%.

In accordance with various embodiments of the present disclosure, an improved SOT MRAM memory is described below. More specifically, the problem of manganese diffusion is mitigated through the use of a filter layer placed in various locations in the SOT stack of the memory devices comprising the SOT MRAM, as shown in FIG. 2.

FIG. 2 illustrates a material stack for a SOT MTJ memory device 200 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a first embodiment. In one embodiment, the SOT MTJ memory device 200 comprises an interconnect 202 having a SOT material, and a MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.

A material stack 206 is on the MTJ device 204. In one embodiment, the material stack 202 comprises a spacer material, an antiferromagnet (AFM), and a top electrode, as described above. However, according to the second embodiment shown in FIG. 2, the pinned fixed magnet FM3 (of FIG. 1A) in the material stack 206 is divided into two halves, a pinned fixed magnet 1 and a pinned fixed magnet 2.

In accordance with various embodiments of the present disclosure, the material stack 206 is further provided with a multilayer barrier filter 208 located within the material stack 206 configured to reduce effects of magnesium diffusion from the antiferromagnet during high temperatures. In one embodiment, the multilayer barrier filter 208 comprises three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy.

The location of the multilayer barrier filter 208 may vary within the material stack 206.

In the first embodiment, the multilayer barrier filter 208 is located between the pinned fixed magnet 1 and the pinned fixed magnet 2, as shown. In this embodiment, the multilayer barrier filter 208 reduces magnesium diffusion, while maintaining a strong coupling between pinned fixed magnets 1 and 2.

The original pinned fixed magnet is divided in two in order to reduce the thickness of the pinned fixed magnets 1 and 2. In one embodiment, the pinned fixed magnets 1 and 2 may each have a thickness of approximately .5 to 1 nm. In one embodiment, the diffusion barrier 1 and diffusion barrier 2 comprise any heavy metal that acts as a barrier to manganese diffusion such as tantalum, tungsten, iridium, and molybdenum. In one embodiment the diffusion barriers 1 and 2 comprise tantalum (Ta) or tantalum oxide (TaO), and may have a thickness of approximately .1 to .5 nm. In one embodiment the ferromagnetic cobalt-based alloy may comprise Co, Co x Fey, or CoxFeyBz (Cobalt, Iron, Boron), where‘x,’‘y,’ and‘z’ are integers. The ferromagnetic cobalt- based alloy may have a thickness of approximately .2 to 3 nm. In another embodiment, the ferromagnetic cobalt-based alloy may comprise binary elements of cobalt with any other transition metal, such as cobalt/tungsten, cobalt/palladium, cobalt/tantalum, and cobalt/platinum, and the like, and alloys thereof.

In this embodiment, the tantalum diffusion barriers 1 and 2 are sufficiently thin so that the pinned fixed magnet 2 magnetically couples to the cobalt-based ferromagnet, and the cobalt- based ferromagnet magnetically couples to the pinned layer 1. The three magnets, the pinned layers 1 and 2 and the cobalt-based ferromagnet, are parallel, while the reference magnet FM2 is antiparallel.

Ideally, the multilayer barrier filter 208 of the present embodiments should enable the MTJ device 204 to handle temperatures up to 400 to 450 C without debilitating magnesium diffusion damage.

FIG. 3 illustrates a material stack for a SOT MTJ memory device 300 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a second embodiment, where like components from FIG. 1 have like reference numerals. In the second embodiment, the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2. A material stack 302 is on the MTJ device 204. In one embodiment, the material stack 302 comprises a spacer material, a pinned fixed magnet FM3, an antiferromagnet (AFM), and a top electrode, as described above.

In accordance with the second embodiment, the multilayer barrier filter 304 comprises two layers of material, a diffusion barrier and a ferromagnetic cobalt-based alloy on the diffusion barrier, and the multilayer barrier filter 304 is located between the spacer material and the pinned fixed magnet FM3. The multilayer barrier filter 304 drops the first pinned fixed magnet and the first diffusion barrier of the second embodiment, and instead places the ferromagnetic cobalt- based alloy directly on the spacer material. In one embodiment, the spacer material comprises ruthenium (RU) or iridium (Ir) and the diffusion barrier comprises tantalum (Ta) or tantalum oxide (TaO). In one embodiment, the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to 1 nm.

FIG. 4 illustrates a material stack for a SOT MTJ memory device 400 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a third embodiment, where like components from FIG. 1 have like reference numerals. In the second embodiment, the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2.

Similar to the first embodiment, a material stack 402 is on the MTJ device 204 where the material stack 402 comprises a spacer material, a pinned fixed magnet 1 a pinned fixed magnet 2, an antiferromagnet (AFM), and a top electrode.

In accordance with the third embodiment, the multilayer barrier filter 404 comprises three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy. However, in this third embodiment, the multilayer barrier filter 404 is located further down the material stack 402 between the reference magnet FM2 and the pinned fixed magnet 1 so that the multilayer barrier filter 404 is in closer proximity to the reference magnet FM2.

FIG. 5 illustrates a material stack for a SOT MTJ memory device 500 having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with a fourth embodiment, where like components from FIG. 1 have like reference numerals. In the second embodiment, the SOT MTJ memory device 200 comprises the interconnect 202 having a SOT material, and the MTJ device 204 having a free layer magnet FM1 coupled to the interconnect 202, a reference fixed magnet FM2, and a barrier material between the free layer magnet FM1 and the reference fixed magnet FM2. Similar to the first embodiment, a material stack 502 is on the MTJ device 204 where the material stack 302 comprises a spacer material, a split pinned fixed magnet comprising pinned fixed magnet 1 and a pinned fixed magnet 2, an antiferromagnet (AFM), and a top electrode.

In accordance with the fourth embodiment, the material stack 502 includes more than one barrier filter, and more particularly, the material stack 502 includes double multilayer barrier filters 504 and 506. Each of the multilayer barrier filters 504 and 506 comprise three layers of material, a diffusion barrier 1, a ferromagnetic cobalt-based alloy on the diffusion barrier 1, and a diffusion barrier 2 on the cobalt-based alloy. According to the fourth embodiment, the first multilayer barrier filter 504 is located in the material stack 502 between the pinned fixed magnet 1 and pinned fixed magnet 2, and the second multilayer barrier filter 506 is located between the reference magnet FM2 and the spacer material, as shown.

In the embodiment where the diffusion barriers 1 and 2 comprise tantalum (Ta) or tantalum oxide (TaO), and may have a thickness of approximately .1 to .5 nm. The

ferromagnetic cobalt-based alloy may have a thickness of approximately .2 to 3 nm. The advantage of the double multilayer barrier filters 504 and 506 is that it may allow the memory device 500 to handle even higher temperatures. Ideally, the use of double multilayer barrier filters 504 and 506 should enable the memory device to handle temperatures up to 400 to 450 C without degrading manganese diffusion.

FIG. 6 is a flow diagram representing various operations in a method of fabricating a SOT MTJ memory device having a top SAF stack with in-plane anisotropy and a multilayer barrier filter in accordance with the embodiments disclosed herein. The process may include forming an SOT interconnect with a write electrode in an opening in a dielectric layer (block 500). In an embodiment, the SOT interconnect is formed in an opening in the dielectric layer above a substrate. The substrate may include a suitable semiconductor material such as but not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI). In another embodiment, the substrate may include other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

In an embodiment, the SOT interconnect is formed in the dielectric layer by a damascene or a dual damascene process that is well known in the art. In an embodiment, both the SOT interconnect and the write electrode may comprise a Giant Spin Hall Effect (GSHE) metal made of b-Tantalum (b-Ta), b-Tungsten (b-W), Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the periodic table. In an embodiment, the SOT interconnect is electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory. A MTJ material stack is formed on the SOT interconnect, and a material layer stack having a multilayer barrier filter is formed over the MTJ material stack (block 502). In one embodiment, the multilayer barrier filter may be placed in various locations within the material layer stack, as described with reference to FIGS. 2-5. In one embodiment, the MTJ material stack and the material layer stack are blanket deposited. The layers of the MTJ stack may be formed by sputter-deposition techniques with deposition rates in the Angstrom-per-second range. The techniques include physical vapor deposition (PVD), specifically planar magnetron sputtering, and ion-beam deposition. In an embodiment, the MTJ stack may be subjected to an annealing process performed at a temperature between 300-400 degrees Celsius. In an embodiment, layers of the material layer stack may be respectively blanket deposited by an evaporation process, an atomic layer deposition (ALD) process or by chemical vapor deposition (CVD) process. In an embodiment, the chemical vapor deposition process is enhanced by plasma techniques such as RF glow discharge (plasma enhanced CVD) to increase the density and uniformity of the film. In an embodiment, an uppermost layer of material layer stack may include the top electrode layer that ultimately acts as a hardmask.

The deposition process can be configured to control the magnetic properties of the magnetic layers. For example, the direction of the magnetic anisotropy of the ferromagnetic materials can be set during the deposition of the layer by applying a magnetic field across the wafer. The resulting uniaxial anisotropy is observed as magnetic easy and hard directions in the magnetization of the layer. Since the anisotropy axis affects the switching behavior of the material, the deposition system must be capable of projecting a uniform magnetic field across the wafer, typically in the 20-100 Oe range, during deposition. The deposition process can control other magnetic properties, such as coercivity and magnetorestriction, by the choice of magnetic alloy and deposition conditions. Because the switching field of a patterned bit depends directly on the thickness of the free layer magnet, the thickness uniformity and repeatability must meet strict requirements.

A lithography step is performed that forms a photoresist mask on an uppermost surface of the material layer stack (block 504). In an embodiment, the photoresist mask is formed at a minimum size required for the memory element MTJ material stack, which is self-aligned with the material layer stack, and defines a location where a memory cell will be subsequently formed. In one embodiment, example minimum sizes for the resist could be in the range of 10 nm - 100 nm.

The material layer stack and the MTJ material stack is then patterned in alignment with the photoresist mask to form an active memory device/cell (block 506). In an embodiment, a plasma etch process is utilized to pattern the material layer stack and the MTJ stack down to the SOT interconnect 202.

A second dielectric layer is deposited over the memory device and other interconnect lines (e.g. a bit line) are patterned over the second dielectric layer (block 508). The memory cell may be completed by removing the photoresist mask and then forming the second dielectric layer on the bit line and on the active memory device (on the hardmask, on sidewalls of the memory device, resistive element and memory element). The second dielectric letter is planarized to expose an uppermost surface of the top electrode. Thereafter, the bit line is patterned on the uppermost surface of the top electrode and on the uppermost surface of the second dielectric layer to complete formation of the memory cell. In an embodiment, the bit line may comprise conductive material such as W, TiN, TaN or Ru. In an embodiment, the bit line is formed by using a dual damascene process (not shown) and includes a barrier layer such as Ru, Ta or Ti and a fill metal such as W or Cu.

It is to be appreciated that the layers and materials described in association with embodiments herein are typically formed on or above an underlying semiconductor substrate, e.g., as FEOL layer(s). In other embodiments, the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s). In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The

semiconductor substrate often includes a wafer or other piece of silicon or another

semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, structures described herein may be fabricated on underlying lower level back end of line (BEOL) interconnect layers. For example, in one embodiment, an embedded non-volatile memory structure is formed on a material composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy -nitride, silicon nitride, or carbon-doped silicon nitride. In a particular embodiment, an embedded non-volatile memory structure is formed on a low-k dielectric layer of an underlying BEOL layer.

Referring to FIGS. 7A and 7B, a wafer 700 may be composed of semiconductor material and may include one or more dies 702 having integrated circuit (IC) structures formed on a surface of the wafer 700. Each of the dies 702 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, such as described above. After the fabrication of the semiconductor product is complete, the wafer 700 may undergo a singulation process in which each of the dies 702 is separated from one another to provide discrete“chips” of the semiconductor product. In particular, structures that include embedded non-volatile memory structures having SOT MTJ memory devices with a multilayer barrier filters as disclosed herein may take the form of the wafer 700 (e.g., not singulated) or the form of the die 702 (e.g., singulated). The die 702 may include one or more embedded non volatile memory structures based on a SOT MTJ memory device with a multilayer barrier filter and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer 700 or the die 702 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 702. For example, a memory array formed by multiple memory devices may be formed on a same die 702 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

FIG. 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with one or more of the embodiments disclosed herein.

Referring to FIG. 8, an IC device assembly 800 includes components having one or more integrated circuit structures described herein. The IC device assembly 800 includes a number of components disposed on a circuit board 802 (which may be, e.g., a motherboard). The IC device assembly 800 includes components disposed on a first face 840 of the circuit board 802 and an opposing second face 842 of the circuit board 802. Generally, components may be disposed on one or both faces 840 and 842. In particular, any suitable ones of the components of the IC device assembly 800 may include a number of embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, such as disclosed herein.

In some embodiments, the circuit board 802 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 802. In other embodiments, the circuit board 802 may be a non-PCB substrate.

The IC device assembly 800 illustrated in FIG. 8 includes a package-on-interposer structure 836 coupled to the first face 840 of the circuit board 802 by coupling components 816. The coupling components 816 may electrically and mechanically couple the package-on- interposer structure 836 to the circuit board 802, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 836 may include an IC package 820 coupled to an interposer 804 by coupling components 818. The coupling components 818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 816. Although a single IC package 820 is shown in FIG. 8, multiple IC packages may be coupled to the interposer 804. It is to be appreciated that additional interposers may be coupled to the interposer 804. The interposer 804 may provide an intervening substrate used to bridge the circuit board 802 and the IC package 820. The IC package 820 may be or include, for example, a die (the die 702 of FIG. 7B), or any other suitable component.

Generally, the interposer 804 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 804 may couple the IC package 820 (e.g., a die) to a ball grid array (BGA) of the coupling components 816 for coupling to the circuit board 802. In the embodiment illustrated in FIG. 8, the IC package 820 and the circuit board 802 are attached to opposing sides of the interposer 804. In other embodiments, the IC package 820 and the circuit board 802 may be attached to a same side of the interposer 804. In some

embodiments, three or more components may be interconnected by way of the interposer 804.

The interposer 804 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 804 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 804 may include metal interconnects 810 and vias 808, including but not limited to through-silicon vias (TSVs) 806. The interposer 804 may further include embedded devices 814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 804. The package-on-interposer structure 836 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 800 may include an IC package 824 coupled to the first face 840 of the circuit board 802 by coupling components 822. The coupling components 822 may take the form of any of the embodiments discussed above with reference to the coupling components 816, and the IC package 824 may take the form of any of the embodiments discussed above with reference to the IC package 820.

The IC device assembly 800 illustrated in FIG. 8 includes a package-on-package structure 834 coupled to the second face 842 of the circuit board 802 by coupling components 828. The package-on-package structure 834 may include an IC package 826 and an IC package 832 coupled together by coupling components 830 such that the IC package 826 is disposed between the circuit board 802 and the IC package 832. The coupling components 828 and 830 may take the form of any of the embodiments of the coupling components 816 discussed above, and the IC packages 826 and 832 may take the form of any of the embodiments of the IC package 820 discussed above. The package-on-package structure 834 may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 9 illustrates a computing device 900 in accordance with one implementation of the disclosure. The computing device 900 houses a board 902. The board 902 may include a number of components, including but not limited to a processor 904 and at least one

communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 900 may contain an integrated circuit die that includes one or more embedded non-volatile memory structures having a SOT MTJ memory device with a multilayer barrier filter, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Thus, embodiments described herein include embedded non-volatile memory structures having SOT MTJ memory device with a multilayer barrier filter elements.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

Example embodiment 1 : A memory device comprises an interconnect having a spin orbit torque (SOT) material. A magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet. A material stack is on the MTJ device, wherein the material stack comprises a spacer material, a pinned fixed magnet, an antiferromagnet, and a multilayer filter located within the material stack, wherein the multilayer filter is configured to reduce effects of manganese diffusion from the antiferromagnet.

Example embodiment 2: the memory device of example embodiment 1, wherein the pinned fixed magnet comprises a first pinned fixed magnet and a second pinned fixed magnet, the multilayer filter comprises: a first diffusion barrier on the first pinned fixed magnet; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.

Example embodiment 3: the memory device of example embodiment 2, wherein the multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet. Example embodiment 4: the memory device of example embodiment 2, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet, and the spacer material is located between the first the pinned fixed magnet and the second pinned fixed magnet.

Example embodiment 5: the memory device of example embodiment 2, wherein the multilayer barrier filter comprises a first multilayer barrier filter, the memory device further comprising a second multilayer barrier filter, wherein the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet, and the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.

Example embodiment 6: the memory device of example embodiment 2, 3, 4, or 5, wherein the first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 1 nm.

Example embodiment 7: the memory device of example embodiment 2, 3, 4, or 5, wherein the first diffusion barrier and the second diffusion barrier comprise any heavy metal that acts as a barrier to manganese diffusion.

Example embodiment 8: the memory device of example embodiment 7, wherein the heavy metal comprises at least one of tantalum, tantalum oxide, tungsten, iridium, and molybdenum, and the first diffusion barrier and the second diffusion barrier have a thickness of approximately .1 to .5 nm.

Example embodiment 9: the memory device of example embodiment 2, 3, 4, or 5, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.

Example embodiment 10: the memory device of example embodiment 1, wherein the multilayer barrier filter comprises a ferromagnetic cobalt-based alloy and a diffusion barrier on the multilayer barrier filter.

Example embodiment 11 : the memory device of example embodiment 10, wherein the multilayer barrier filter is located between the spacer material and the pinned fixed magnet.

Example embodiment 12: the memory device of example embodiment 10, or 11, wherein the diffusion barrier comprises tantalum or tantalum oxide, and the spacer material comprises ruthenium or iridium.

Example embodiment 13 : the memory device of example embodiment 10, or 11 , wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .3 to .4 nm.

Example embodiment 14: A memory device comprises an interconnect having a spin orbit torque (SOT) material. A magnetic tunnel junction (MTJ) device comprises a free layer magnet coupled to the interconnect, a reference fixed magnet, and a barrier material between the free layer magnet and the reference fixed magnet. A material stack is on the MTJ device, wherein the material stack comprises a spacer material, a first pinned fixed magnet, a second pinned magnet, an antiferromagnet, and a multilayer filter located within the material stack, wherein the multilayer filter comprises a first diffusion barrier on the first pinned fixed magnet; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.

Example embodiment 15: The memory device of claim 14, wherein multilayer filter is located between the first pinned fixed magnet and the second pinned fixed magnet.

Example embodiment 16: The memory device of claim 14, wherein the multilayer barrier filter is located between the reference fixed magnet and the first pinned fixed magnet, and the spacer material is located between the first pinned fixed magnet and the second pinned fixed magnet.

Example embodiment 17: The memory device of claim 14, wherein the multilayer barrier filter comprises a first multilayer barrier filter, the memory device further comprising a second multilayer barrier filter, wherein the first multilayer barrier filter is located between the first pinned fixed magnet and the second pinned fixed magnet, and the second multilayer barrier filter is located between the reference fixed magnet and the spacer material.

Example embodiment 18: The memory device of claim 14, 15, 16, or 17, wherein the first pinned fixed magnet and the second pinned fixed magnet each have a thickness of approximately .5 to 1 nm.

Example embodiment 19: The memory device of claim 14, 15, 16, or 17, wherein the first diffusion barrier and second diffusion barrier comprise any heavy metal that acts as a barrier to manganese diffusion.

Example embodiment 20: The memory device of claim 19, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.

Example embodiment 21 : The memory device of claim 14, 15, 16, or 17, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.

Example embodiment 22: A method of fabricating an integrated circuit device comprises forming a SOT interconnect with a write electrode in an opening in a dielectric layer. A MTJ material stack is formed on the SOT interconnect, and a material layer stack having a multilayer barrier filter is formed over the MTJ material stack. A lithography step is performed that forms a photoresist mask on an uppermost surface of the material layer stack. The material layer stack and the MTJ material stack are patterned in alignment with the photoresist mask to form a memory device. A second dielectric layer is deposited over the memory device and patterning another interconnect line over the second dielectric layer. Example embodiment 23 : The method of claim 22, further comprises forming the multilayer barrier filter with: a first diffusion barrier; a ferromagnetic cobalt-based alloy on the first diffusion barrier; and a second diffusion barrier on the cobalt-based alloy.

Example embodiment 24: The method of claim 23, wherein the first diffusion barrier and the second diffusion barrier comprise tantalum or tantalum oxide having a thickness of approximately .1 to .5 nm.

Example embodiment 25 : The method of claim 23 or 24, wherein the ferromagnetic cobalt-based alloy has a thickness of approximately .2 to 3 nm.