Hereinafter, a semiconductor device and a manufacturing method thereof according to a first example embodiment of the present invention will be described with reference to the accompanying drawings.

Figs. 1A, 1B, 1C, 1D, and 1E are diagrams showing a structure of a semiconductor device according to a first example embodiment of the present invention, and more specifically, a semiconductor device having fin-type FETs. Fig. 1A is a plan view, Fig. 1B is a cross-sectional view taken along line A-A in Fig. 1A, Fig. 1C is a cross-sectional view taken along line B-B in Fig. 1A, Fig. 1D is a cross-sectional view taken along line C-C in Fig. 1A, and Fig. 1E is a cross-sectional view taken along line D-D in Fig. 1A.

As shown in Figs. 1A thorough 1E, the fin-type FETs of the present example embodiment includes a support substrate 11, an insulating layer 12, fin-type semiconductor regions 13a through 13d, gate insulating films 14a through 14d, a gate electrode 15, insulating sidewall spacers 16, extension regions 17, and source/drain regions 27. The support substrate 11 is made of, for example, silicon. The insulating layer 12 is formed on the support substrate 11 and made of, for example, silicon oxide. The fin-type semiconductor regions 13a through 13d are formed on the insulating layer 12. The gate insulating films 14a through 14d are made of, for example, a silicon oxynitride film and are formed so as to cover the upper surface and both side surfaces of predetermined portions of the fin-type semiconductor regions 13a through 13d, respectively. The gate electrode 15 is formed on the gate insulating films 14a through 14d. The insulating sidewall spacers 16 are formed on the side surfaces of the gate electrode 15. The extension regions 17 are formed on both sides of the gate electrode 15 in each fin-type semiconductor region 13a through 13d. The source/drain regions 27 are formed on both sides of the gate electrode 15 and the insulating sidewall spacers 16 in each fin-type semiconductor region 13a through 13d.

Each fin-type semiconductor region 13a through 13d has a length "a" of, for example, about 22 nm in the gate width direction, a length "b" of, for example, about 350 nm in the gate length direction, and a height (thickness) "c" of, for example, about 65 nm. The fin-type semiconductor regions 13a through 13d are arranged on the insulating layer 12 at a pitch "d" (e.g., about 30 nm) in the gate width direction. Note that the upper surface and the side surfaces of each fin-type semiconductor region 13a through 13d may be, but not necessarily, perpendicular to each other.

For convenience of the description, it is herein assumed that gate insulating films 14au through 14du are respectively formed on the upper surface of the fin-type semiconductor regions 13a through 13d, gate insulating films 14as through 14ds are respectively formed on the side surfaces of the fin-type semiconductor regions 13a through 13d, and each of the gate insulating films 14a through 14d is formed by a corresponding one of the gate insulating films 14au through 14du and a corresponding one of the gate insulating films 14as through 14ds. However, the gate insulating films 14au, 14as, the gate insulating films 14bu, 14bs, the gate insulating films 14cu, 14cs, and the gate insulating films 14du, 14ds are actually formed integrally. The gate electrode 15 is formed so as to extend across the fin-type semiconductor regions 13a through 13d in the gate width direction. Note that description and illustration of pocket regions will be omitted.

The present example embodiment is characterized in that protruding portions 15a are formed on both sides of the gate electrode 15 over the upper surface of the fin-type semiconductor regions 13a through 13d, respectively. No protruding portion 15a of the gate electrode 15 is formed in regions between fin-type semiconductor regions 13a through 13d. Each protruding portion 15a has a length of about 18 nm in the gate width direction, which is smaller than the length "a" (about 22 nm) of each fin-type semiconductor region 13a through 13d in the gate width direction. Each protruding portion 15a has a protruding length of about 5 nm in the gate length direction, and has a thickness of about 60 nm, which is the same as that of the gate electrode 15.

Note that the gate insulating films 14au through 14du are respectively present under the protruding portions 15a of the gate electrode 15 on the upper surface of the fin-type semiconductor regions 13a through 13d. In other words, the gate insulating films 14au through 14du formed on the upper surface of the fin-type semiconductor regions 13a through 13d have a larger length in the gate length direction than the length in the gate direction of the gate insulating films 14as through 14ds formed on the side surfaces of the fin-type semiconductor regions 13a through 13d. For example, the gate insulating films 14as through 14ds have a length of about 38 nm in the gate length direction, which is the same as the gate length of the gate electrode 15 excluding the protruding portions 15a. The gate insulating films 14au through 14du have a length of about 48 nm which is the sum of the gate length (38 nm) and the protruding length on both sides (5 nm x 2). The insulating sidewall spacers 16 are formed also on the side surfaces of the protruding portions 15a of the gate electrode 15.

In the example embodiment described above, the protruding portions 15a are formed as impurity blocking portions on both sides of the gate electrode 15 over the upper surface of the fin-type semiconductor regions 13a through 13d. Impurity regions formed in the middle regions of the upper parts of the fin-type semiconductor region 13a through 13d in a doping process can thus be separated from the gate electrode 15. Impurities in the impurity regions can therefore be prevented from diffusing into a region under the gate electrode 15 in an annealing process. In other words, the distance between source-side and drain-side extension regions 17 can be prevented from being reduced in the middle region of the upper part of each fin-type semiconductor region 13a through 13d due to intensive diffusion of impurities caused in an annealing process. The distance between the source-side and drain-side extension regions 17 is thus about the same in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d and in the upper corners and both sides of the fin-type semiconductor regions 13a through 13d. Accordingly, degradation in characteristics such as generation of a leakage current can be prevented even if the fin-type semiconductor regions 13a through 13d have a smaller length in the gate width direction.

In the present example embodiment, the gate length of the gate electrode 15 is set to 45 nm or less and the fin-type semiconductor regions 13a through 13d have a larger height than their length in the gate width direction. The above effect of preventing degradation in characteristics becomes significant especially in the case where a three-dimensional device such as a fin-type FET is reduced in dimensions by using such a gate electrode 15 and such fin-type semiconductor regions 13a through 13d.

Fig. 2A is a plan view showing, as a comparative example, a structure of a semiconductor device having fin-type FETs with no protruding portion 15a of the gate electrode 15 of the present invention. Fig. 2B is a cross-sectional view taken along line D-D in Fig. 2A. Note that the semiconductor device of Fig. 2A has the same cross-sectional view as that of Fig. 1B along line A-A, and has the same cross-sectional view as that of Fig. 1C along lines B-B and C-C. As shown in Figs. 2A and 2B, when the gate electrode 15 has no protruding portion 15a as an impurity blocking portion, impurity regions formed in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d in a doping process become adjacent to the gate electrode 15. Impurities in these impurity regions therefore diffuse into a region under the gate electrode 15 in an annealing process. In other words, the distance between the source-side and drain-side extension regions 17 becomes shorter in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d due to the intensive diffusion in the anneal process than in the remaining part of the fin-type semiconductor regions 13a through 13d, thereby causing degradation in characteristics such as generation of a leakage current.

Note that, in the first example embodiment, the gate electrode 15 has the protruding portions 15a as the impurity blocking portions. The manufacturing process can therefore be simplified as compared to the case where the impurity blocking portions are formed by using a material other than the gate electrode material.

In the first example embodiment, the length of the protruding portions 15a of the gate electrode 15 in the gate width direction is smaller than the length of the fin-type semiconductor regions 13a through 13d in the gate width direction. The protruding portions 15a as the impurity blocking portions can therefore be reliably formed only over the upper surface of the fin-type semiconductor regions 13a through 13d even if misalignment occurs in a lithography process for forming the gate electrode 15 (including the protruding portions 15a).

In the first example embodiment, the fin-type semiconductor regions 13a through 13d are formed on the support substrate 11 with the insulating layer 12 interposed therebetween. However, a semiconductor substrate may alternatively be patterned to form protrusions as fin-type semiconductor regions.

Hereinafter, a manufacturing method of the semiconductor device according to the first example embodiment of the present invention will be described with reference to the figures.

Figs. 3A through 3D, Figs. 4A through 4C, and Figs. 5A and 5B are perspective views sequentially illustrating the manufacturing method of the semiconductor device of the first example embodiment. Note that, in Figs. 3A through 3D, Figs. 4A through 4C, and Figs. 5A and 5B, the same components as those in Figs. 1A through 1E are denoted by the same reference numerals and characters, and overlapping description will be omitted.

First, an SOI (Semiconductor On Insulator) substrate is prepared as shown in Fig. 3A. The SOI substrate has a support substrate 11, an insulating layer 12 formed on the support substrate 11, and a semiconductor layer 13 formed on the insulating layer 12. The support substrate 11 has a thickness of about 775 micrometers and is made of, for example, silicon. The insulating layer 12 has a thickness of about 150 nm and is made of, for example, silicon oxide. The semiconductor layer 13 has a thickness of about 65 nm and is made of, for example, silicon.

As shown in Fig. 3B, a resist pattern 41 is then formed on the semiconductor layer 13 so as to cover fin-type-semiconductor-region formation regions (regions where fin-type semiconductor regions are to be formed). As shown in Fig. 3C, by using the resist pattern 41 as a mask, the semiconductor layer 13 is patterned to form n-type fin-type semiconductor regions 13a through 13d to be used as active regions. The resist pattern 41 is then removed as shown in Fig. 3D. Each fin-type semiconductor region 13a through 13d has a length "a" of, for example, about 22 nm in the gate width direction, a length "b" of, for example, about 350 nm in the gate length direction, and a height (thickness) "c" of, for example, about 65 nm. The fin-type semiconductor regions 13a through 13d are arranged on the insulating layer 12 at a pitch "d" (e.g., about 30 nm) in the gate width direction.

As shown in Fig. 4A, gate insulating films 14a through 14d having a thickness of 3 nm are then formed on the respective surfaces of the fin-type semiconductor regions 13a through 13d. The gate insulating films 14a through 14d are made of, for example, a silicon oxynitride film. As shown in Fig. 4B, a polysilicon film 15A having a thickness of, for example, 60 nm is then formed over the whole surface of the support substrate 11.

As shown in Fig. 4C, a resist pattern 42 is then formed on the polysilicon film 15A by, for example, double patterning technology so as to cover a gate-electrode formation region and impurity-introduction-blocking-portion formation regions located on both sides (in the gate length direction) of the gate-electrode formation region. The gate-electrode formation region is a region where a gate electrode is to be formed, and the impurity-introduction-blocking-portion formation regions are regions where impurity blocking portions are to be formed (regions where protruding portions are to be formed). The resist pattern 42 has a longer length in the gate length direction in the regions located above the respective upper surfaces of the fin-type semiconductor regions 13a through 13d than in the regions located above the insulating layer 12 (regions located between the fin-type semiconductor regions).

As shown in Fig. 5A, by using the resist pattern 42 as a mask, the polysilicon film 15A is then etched to form a gate electrode 15 having protruding portions 15a over the respective upper surfaces of the fin-type semiconductor regions 13a through 13d. In this etching, the gate insulating films 14a through 14d are also etched away in the regions which are not covered by the gate electrode 15 including the protruding portions 15a. Note that the gate electrode 15 (including the protruding portions 15a) has a length of about 48 nm in the gate length direction above the upper surfaces of the fin-type semiconductor regions 13a through 13d. The gate electrode 15 (excluding the protruding portions 15a) has a length of about 38 nm in the gate length direction above the side surfaces of the fin-type semiconductor regions 13a through 13d. The protruding portions 15a have a length of about 18 nm in the gate width direction, which is smaller than the length "a" (about 22 nm) of the fin-type semiconductor regions 13a through 13d in the gate width direction. The protruding portions 15a have a protruding length of about 5 nm in the gate length direction. The resist pattern 42 is then removed as shown in Fig. 5B.

Although not shown in the figure, by using the gate electrode 15 as a mask, the fin-type semiconductor regions 13a through 13d are then doped with p-type impurities by a plasma doping method at a pressure of 0.6 Pa or less. As a result, p-type extension regions 17 (see Figs. 1A through 1E) are formed on both sides of the gate electrode 15 in the fin-type semiconductor regions 13a through 13d. In the present example embodiment, by using a pressure of 0.6 Pa or less in the plasma doping method as described above, an implantation dose in the sides of the fin-type semiconductor regions 13a through 13d can be made to be about 80% or more of that in the upper parts of the fin-type semiconductor regions 13a through 13d. For example, the plasma doping method may be performed under the following conditions: source gas: B ₂ H ₆ (diborane) diluted with He (helium); B ₂ H ₆ concentration in the source gas: 0.5 mass%; total flow rate of the source gas: 100 cm ³ /min (normal state); pressure in a chamber: 0.35 Pa; source power (plasma generating high-frequency power): 500 W; bias voltage (Vpp): 250 V; substrate temperature: 30 C; and plasma doping time: 60 seconds. Although not shown in the figure, by using the gate electrode 15 as a mask, impurity ions are then implanted into the fin-type semiconductor regions 13a through 13d to form n-type pocket regions.

Although not shown in the figure, an insulating film having a thickness of, for example, 60 nm is then formed over the whole surface of the support substrate 11. The insulating film is then etched back by anisotropic dry etching to form insulating sidewall spacers 16 (see Figs. 1A through 1E) on the side surfaces of the gate electrode 15 (including the protruding portions 15a). Although not shown in the figure, by using the gate electrode 15 and the insulating sidewall spacers 16 as a mask, the fin-type semiconductor regions 13a through 13d are then doped with p-type impurities by a plasma doping method at a pressure of, for example, 0.6 Pa or less for about 60 seconds to form p-type source/drain regions 27 (see Figs. 1A through 1E) in the fin-type semiconductor regions 13a through 13d. The p-type source/drain regions 27 are formed on both sides of the insulating sidewall spacers 16 when viewed from the gate electrode 15. In the present example embodiment, by using a pressure of 0.6 Pa or less in the plasma doping method as described above, an implantation dose in the sides of the fin-type semiconductor regions 13a through 13d can be made to be about 80% or more of that in the upper parts of the fin-type semiconductor regions 13a through 13d.

Note that an annealing process for electrically activating impurities implanted in the fin-type semiconductor regions 13a through 13d to form the extension regions 17 may be performed, for example, after formation of the insulating sidewall spacers 16 and before impurity implantation for forming the source/drain regions 27. This annealing process may alternatively be performed after the impurity implantation for forming the source/drain regions 27. In the former case, another annealing process for electrically activating the implanted impurities is performed after the impurity implantation for forming the source/drain regions 27.

The manufacturing method of the present example embodiment is characterized in that the resist pattern 42 is formed in the step of Fig. 4C so as to cover the gate-electrode formation region and the protruding-portion formation regions located on both sides of the gate-electrode formation region, and the gate electrode 15 having the protruding portions 15a as the impurity blocking portions are thus formed over the upper surfaces of the fin-type semiconductor regions 13a through 13d. In other words, the manufacturing method of the present example embodiment is characterized in that the length of the gate electrode 15 in the gate length direction is larger over the upper surfaces of the fin-type semiconductor regions 13a through 13d than over the side surfaces of the fin-type semiconductor regions 13a through 13d. The distance between the source-side and drain-side extension regions 17 is therefore about the same in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d and in the upper corners and both sides of the fin-type semiconductor regions 13a through 13d. Degradation in characteristics such as generation of a leakage current can therefore be prevented even if the fin-type semiconductor regions 13a through 13d have a smaller length in the gate width direction.

Note that it is preferable in the present example embodiment that, in the impurity implantation processes for forming the extension regions 17 and the source/drain regions 27, the implantation dose in the sides of the fin-type semiconductor regions 13a through 13d is 50% or more (more preferably, 80% or more) of that in the upper parts of the fin-type semiconductor regions 13a through 13d. In this case, the specific resistance (or the sheet resistance or the spreading resistance instead of the specific resistance; the same applies to the description below) of the extension regions 17 and the source/drain regions 27 formed in the sides of the fin-type semiconductor regions 13a through 13d can be made at most twice (at most 1.25 times when the above implantation dose is 80% or more) the specific resistance of the extension regions 17 and the source/drain regions 27 formed in the upper parts of the fin-type semiconductor regions 13a through 13d. Accordingly, excellent transistor characteristics can be obtained in fin-type FETs in which the length of the fin-type semiconductor regions 13a through 13d in the gate width direction is smaller than the height of the fin-type semiconductor regions 13a through 13d. In other words, excellent transistor characteristics can be obtained in fin-type FETs whose transistor characteristics are significantly affected by the impurity regions formed in the sides of the fin-type semiconductor regions.

In the present example embodiment, the n-type fin-type semiconductor regions 13a through 13d are doped with p-type impurities by a plasma doping method to form the p-type extension regions 17 and the p-type source/drain regions 27 (i.e., p-type MIS (Metal Insulator Semiconductor) FETs. However, p-type fin-type semiconductor regions may alternatively be doped with n-type impurities to form n-type extension regions and n-type source/drain regions (i.e., n-type MIS-FETs).

It is to be understood that, in the present example embodiment, parameters other than the pressure, such as a gas concentration, source power, or bias power, may be adjusted in order to increase the implantation dose in the plasma doping processes for forming the extension regions 17 and the source/drain regions 27.

In the present example embodiment, B ₂ H ₆ diluted with He was used as a source gas of the plasma doping method. However, the source gas is not specifically limited as long as it contains impurities to be implanted to the fin-type semiconductor regions. For example, instead of B ₂ H ₆ , other kinds of molecules containing boron atoms (e.g., BF ₃ ) may be used, or other kinds of molecules formed by boron atoms and hydrogen atoms may be used. Alternatively, AsH ₄ , PH ₃ , or the like may be used. A gas containing impurities may be, but not necessarily, diluted with a rare gas such as He. However, in the case where B ₂ H ₆ diluted with He is used as a source gas of the plasma doping method as in the present example embodiment, the mass concentration of B ₂ H ₆ in the source gas is preferably 0.01% to 1%. This is more desirable because this mass concentration facilitates introduction of boron into silicon. More specifically, a sufficient amount of boron is less likely to be introduced at a B ₂ H ₆ gas concentration of 0.01% or less. At a B ₂ H ₆ gas concentration of 1% or more, on the other hand, a deposit containing boron is more likely to be formed on the substrate surface.

Hereinafter, a mechanism of how the above effects are obtained by the impurity blocking portions of the present invention (the protruding portions 15a of the gate electrode 15 in the first example embodiment) will be described with reference to the figures. Figs. 6A and 6B are conceptual diagrams illustrating the impurity implantation process for forming the extension regions in the manufacturing method of the present example embodiment. Fig. 6A corresponds to a cross-sectional structure taken along line A-A in Fig. 5B, and Fig. 6B corresponds to a cross-sectional structure taken along line B-B in Fig. 5B.

As shown in Fig. 6A, the upper surfaces and the side surfaces of the fin-type semiconductor regions 13a through 13d are partially covered by the gate electrode 15 (including the protruding portions 15a) and the remaining region of the upper surfaces and the side surfaces of the fin-type semiconductor regions 13a through 13d is exposed at the time the impurity implantation for forming the extension regions is performed (before formation of the insulating sidewall spacers 16). By doping such fin-type semiconductor regions 13a through 13d with p-type impurities by a plasma doping method, impurity regions 50a are formed in the upper parts of the fin-type semiconductor regions 13a through 13d and impurity regions 50b are formed in the sides of the fin-type semiconductor regions 13a through 13d, respectively. The impurity regions 50a have an implantation dose which is determined by the balance of implanted ions 18a, adsorbed species (neutral species such as gas molecules and radicals) 18b, and impurities 18c which are desorbed from the fin-type semiconductor regions 13a through 13d by sputtering (hereinafter, referred to as desorbed impurities 18c). The impurity regions 50b have an implantation dose which is determined mainly by the adsorbed species (neutral species such as gas molecules and radicals) 18b. Note that since some ions are incident obliquely on the side surfaces of the fin-type semiconductor regions 13a through 13d, there are implanted ions 18a and desorbed impurities 18c which affect the implantation dose of the impurity regions 50b. However, since the influence of the implanted ions 18a and the desorbed impurities 18c is much smaller than that of the absorbed species 18b, doping with the adsorbed species 18b is dominant in the side surfaces of the fin-type semiconductor regions 13a through 13d. In other words, the amount of implanted ions 18a which are implanted into the sides of the fin-type semiconductor regions 13a through 13d and the amount of desorbed impurities 18c which are desorbed from the sides of the fin-type semiconductor regions 13a through 13d by sputtering are much smaller than the amount of implanted ions 18a which are implanted into the upper parts of the fin-type semiconductor regions 13a through 13d and the amount of desorbed impurities 18c which are desorbed from the upper parts of the fin-type semiconductor regions 13a through 13d by sputtering.

As described above, the difference in doping between the upper part and the side of each fin-type semiconductor region 13a through 13d is caused by the fact that the implanted ions 18a and the desorbed impurities 18c significantly affect the upper parts of the fin-type semiconductor regions 13a through 13d, while the implanted ions 18a and the desorbed impurities 18c very slightly affect the sides of the fin-type semiconductor regions 13a through 13d. The amount of implanted ions 18a and the implantation energy also affect the amount of desorbed impurities 18c which are desorbed from the fin-type semiconductor regions 13a through 13d by sputtering. A fundamental difference in doping between the upper part and the side of each fin-type semiconductor region 13a through 13d is therefore caused by the significant difference between the amount of implanted ions 18a which is directed to the upper surfaces of the fin-type semiconductor regions 13a through 13d and the amount of implanted ions 18a which is directed to the side surfaces of the fin-type semiconductor regions 13a through 13d. In other words, the difference in doping between the upper part and the side of each fin-type semiconductor region 13a through 13d is caused by the fact that the amount of implanted ions 18a which is directed to the upper surfaces of the fin-type semiconductor regions 13a through 13d is much larger than the amount of implanted ions 18a which is directed to the side surfaces of the fin-type semiconductor regions 13a through 13d.

Accordingly, the above fundamental difference in doping between the upper part and the side of each fin-type semiconductor region 13a through 13d can be almost completely eliminated by directing an extremely small amount of implanted ions 18a to the upper surfaces of the fin-type semiconductor regions 13a through 13d. In other words, when an extremely small amount of implanted ions 18a is directed to the upper surfaces of the fin-type semiconductor regions 13a through 13d, an extremely small amount of implanted ions 18a are implanted to the upper parts of the fin-type semiconductor regions 13a through 13d and an extremely small amount of impurities 18c are desorbed from the upper parts of the fin-type semiconductor regions 13a through 13d. As a result, the influence of the implanted ions 18a on the implantation dose becomes relatively smaller than the influence of the adsorbed species 18b on the implantation dose in the upper parts of the fin-type semiconductor regions 13a through 13d. Doping with the adsorbent species 18b therefore dominantly affects the implantation dose in the upper parts of the fin-type semiconductor regions 13a through 13d. On the other hand, doping with the adsorbed species 18b is originally dominant in the sides of the fin-type semiconductor regions 13a through 13d. In both the upper parts and the sides of the fin-type semiconductor regions 13a through 13d, the implantation dose is therefore determined almost only by the amount of doping with the adsorbed species 18b. The amount of doping with the adsorbed species 18b is determined by adsorption of neutral species (such as gas molecules and radicals) having a random traveling direction that is not affected by electric fields. The amount of doping with the adsorbed species 18b is therefore about the same both in the upper parts and the sides of the fin-type semiconductor regions 13a to 13d. As a result, the same implantation dose can be obtained both in the impurity regions 50a and the impurity regions 50b.

As shown in Fig. 6B, the upper surfaces of the fin-type semiconductor regions 13a through 13d are partially covered by the protruding portions 15a while the side surfaces thereof are exposed at the time when the impurity implantation process for forming the extension regions is performed (before formation of the insulating sidewall spacers 16). When such fin-type semiconductor regions 13a through 13d are doped with p-type impurities by a plasma doping method, impurities are neither implanted nor adsorbed to the upper parts of the fin-type semiconductor regions 13a through 13d. No impurity region is therefore formed in the upper parts of the fin-type semiconductor regions 13a through 13d. On the other hand, impurity regions 50b (corresponding to the second impurity regions 50b in Fig. 6A) are formed in the sides of the fin-type semiconductor regions 13a through 13d. The implantation dose of the impurity regions 50b is determined mainly by the adsorbed species (neutral species such as gas molecules and radicals) 18b.

Hereinafter, how impurities implanted to the fin-type semiconductor regions 13a through 13d to form the extension regions 17 diffuse in an annealing process will be described based on the impurity distribution before and after the annealing process. Description is herein given to the fin-type semiconductor region 13b in the structure of Fig. 5B. Fig. 7 is a perspective view showing only the fin-type semiconductor region 13b in the structure of Fig. 5B, and the gate insulating film 14b and the gate electrode 15 which are formed over the fin-type semiconductor region 13b. Fig. 8A shows an impurity distribution before the annealing process in a cross-sectional structure taken along line A-A in Fig. 7. Fig. 8B shows an impurity distribution before the annealing process in a cross-sectional structure taken along line B-B in Fig. 7. Fig. 8C shows an impurity distribution before the annealing process in a cross-sectional structure taken along line C-C in Fig. 7. Fig. 9A shows an impurity distribution after the annealing process in the cross-sectional structure taken along line A-A in Fig. 7. Fig. 9B shows an impurity distribution after the annealing process in the cross-sectional structure taken along line B-B in Fig. 7. Fig. 9C shows an impurity distribution after the annealing process in the cross-sectional structure taken along line C-C in Fig. 7.

First, description will be given to impurity distribution before and after the annealing process in the cross-sectional structure taken along line A-A in Fig. 7. As shown in Fig. 8A, in the cross-sectional structure taken along line A-A in Fig. 7 (the cross-sectional structure of the fin-type semiconductor region 13b which is not covered by the gate electrode 15 (including the protruding portions 15a)), an impurity region 50a is formed in the upper part, and an impurity region 50bl is formed in the left side, and an impurity region 50br is formed in the right side. It is herein assumed that the impurity regions 50a, 50bl, and 50br have approximately the same implantation dose. When this fin-type semiconductor region 13b is subjected to the annealing process, impurities in the impurity regions 50a, 50bl, and 50br in Fig. 8A diffuse in a wider range to form an extension region 17 as shown in Fig. 9A. A portion 17a in Fig. 9A located in the middle region of the upper part of the fin-type semiconductor region 13b was originally the impurity region 50a. Although the portion 17a already had a high impurity concentration before the annealing process, impurities in the impurity region 50bl and the impurity region 50br of the fin-type semiconductor region 13b further diffuse into the portion 17a by the annealing, thereby causing concentration of impurities in the portion 17a. In annealing processes, impurities generally diffuse from a highly doped region to a lightly doped region. Since the portion 17a located in the middle region of the upper part of the fin-type semiconductor region 13b was originally the impurity region 50a, the portion 17a has the highest impurity concentration in the cross-sectional structure of Fig. 9A. The largest amount of impurities therefore attempt to diffuse from the portion 17a to the fin-type semiconductor region 13b under the gate electrode 15 where the impurity concentration is the lowest. In other words, the portion which was originally the impurity region 50a supplies the largest amount of impurities as a diffusion source into a region under the gate electrode 15. Note that, as shown in Fig. 9A, other impurity regions are formed in addition to the potion 17a. More specifically, an impurity region is formed in a left side 17b of the fin-type semiconductor region 13b by the impurities diffused from the impurity region 50bl in Fig. 8A. An impurity region is formed in a right side 17c of the fin-type semiconductor region 13b by the impurities diffused from the impurity region 50br of Fig. 8A. An impurity region is formed in a middle part 17f of the fin-type semiconductor region 13b by the impurities diffused from the impurity regions 50bl and 50br of Fig. 8A. An impurity region is formed in an upper left corner 17d of the fin-type semiconductor region 13b by the impurities diffused from the impurity regions 50a and 50bl of Fig. 8A. An impurity region is formed in an upper right corner 17e of the fin-type semiconductor region 13b by the impurities diffused from the impurity regions 50a and 50br of Fig. 8A. However, each of the above impurity regions has a lower impurity concentration than that of the middle region of the upper part of the fin-type impurity region 13b (i.e., the portion 17a).

Fig. 10 shows an SIMS measurement result of the relation between the implantation depth and the boron concentration when boron was implanted to a semiconductor region (silicon region) by a plasma doping method. As shown in Fig. 10, the impurity concentration is the highest at the topmost surface of the semiconductor region and decreases toward the inside of the semiconductor region. Accordingly, the impurity region 50a of Fig. 8A has a highest impurity concentration at the topmost surface (upper surface) of the fin-type semiconductor region 13b before the annealing process. As described before, impurities in the impurity regions 50bl and 50br in the left and right sides of the fin-type semiconductor region 13b also diffuse into the topmost surface of the fin-type semiconductor region 13b in the impurity region 50a, thereby causing concentration of impurities at the topmost surface of the impurity region 50a. As a result, the topmost surface of the impurity region 50a in Fig. 8A is likely to be a diffusion source of impurities which diffuse into the fin-type semiconductor region 13b under the gate electrode 15.

In the present example embodiment, however, as shown in Fig. 7, the protruding portions 15a are formed on both sides of the gate electrode 15 over the upper surface of the fin-type semiconductor region 13b. In other words, the gate electrode 15 (including the protruding portions 15a) formed over the upper surface of the fin-type semiconductor region 13b has a longer length in the gate length direction than that of the gate electrode 15 formed over the side surfaces of the fin-type semiconductor region 13b. Therefore, in the upper surface of the fin-type semiconductor region 13b, the region that is not covered by the gate electrode 15 as shown in Fig. 8A (i.e., an impurity introducing region) can be separated from the gate electrode 15 excluding the protruding portions 15a (the gate electrode 15 formed over the side surface of the fin-type semiconductor region 13b). In this way, in the present example embodiment, it is anticipated that the topmost surface of the impurity region 50a in Fig. 8A is likely to be a diffusion source of impurities into the region under the gate electrode 15, whereby the impurity introducing region is separated from the gate electrode 15 (excluding the protruding portions 15a) by the excessive diffusion length of impurities. More specifically, in the first example embodiment, the protruding portions 15a on both sides of the gate electrode 15 have a protruding length of about 5 nm in the gate length direction. In other words, the gate electrode 15 (including the protruding portions 15a) formed over the upper surface of the fin-type semiconductor region 13b is longer in the gate length direction by about 10 nm (5 nm x 2) than the gate electrode 15 formed on the side surfaces of the fin-type semiconductor region 13b. In the annealing process, impurities may diffuse from the impurity regions 50bl and 50br in the left and right sides of the fin-type semiconductor region 13b into the portion that was originally the impurity region 50a (see Fig. 8A) located in the middle region of the upper part of the fin-type semiconductor region 13b, thereby causing concentration of the impurities in this portion. In the structure of the present example embodiment, however, the impurity introducing region is separated in advance from the gate electrode 15 (excluding the protruding portions 15a) by about 5 nm. Accordingly, even if such concentration of the impurities happens in the above portion and the diffusion length of the impurities into a region under the gate electrode 15 is increased by about 5 nm than in the case where no such concentration of impurities occurs, the distance between the source-side and drain-side extension regions 17 in the middle region of the upper part of the fin-type semiconductor region 13b becomes the same as the distance between the source-side and drain-side extension regions 17 in both sides of the fin-type semiconductor region 13b where neither diffusion nor concentration of impurities occurs from the left and right sides of the fin-type semiconductor region 13b.

Hereinafter, description will be given to impurity distribution before and after the annealing process in the cross-sectional structure taken along line B-B in Fig. 7. As shown in Fig. 8B, in the cross-sectional structure taken along line B-B in Fig. 7 (the cross-sectional structure of the fin-type semiconductor region 13b having the protruding portion 15a of the gate electrode 15), no impurity region is formed in the upper part, while impurity regions 50bl and 50br are formed in the left and right sides, respectively. It is herein assumed that the impurity regions 50bl and 50br have approximately the same implantation dose as that of the impurity region 50a in Fig. 8A. When this fin-type semiconductor region 13b is subjected to the annealing process, impurities in the impurity regions 50bl and 50br in Fig. 8B diffuse in a wider range to form an extension region 17 as shown in Fig. 9A. Although not shown in the figure, impurities in the impurity region 50a (see Fig. 8A) located in the upper part of the fin-type semiconductor region 13b adjacent to the protruding portion 15a also diffuse into a region under the protruding portion 15a. As a result, the impurity concentration in the extension region 17 formed in the upper part of the fin-type semiconductor region 13b becomes approximately the same as that of the extension region 17 formed in the side of the fin-type semiconductor region 13b.

Note that, in the annealing process, impurities in the impurity regions 50bl, 50br shown in Fig. 8B intensively diffuse to a middle part 17h of the fin-type semiconductor region 13b. However, the middle part 17h of the fin-type semiconductor region 13b is a portion located inside the semiconductor (silicon) substrate, and has an extremely low impurity concentration before the annealing process. Accordingly, the above-mentioned phenomenon of the annealing process, in which impurities intensively diffuse into a region which has been already highly doped before the annealing process, does not occur in the middle part 17h of the fin-type semiconductor region 13b. A depth profile of the impurity concentration cannot be measured by SMIS in an uneven semiconductor region such as a side of a fin-type semiconductor region. As described above, however, doping with adsorbed species is dominant in the impurity implantation to the side of the fin-type semiconductor region, as compared to the impurity implantation to the upper part of the fin-type semiconductor region. It can therefore be assumed that, for example, as in the case of the depth profile of the impurity concentration in Fig. 10 (the depth profile of the impurity concentration in a flat semiconductor region), the impurity concentration in the side of the fin-type semiconductor region is also higher at the surface than in the inside. For example, in the first example embodiment, the fin-type semiconductor region 13b has a width (length in the gate width direction) of 22 nm. Therefore, the middle of the fin-type semiconductor region 13b is located at a depth of 11 nm from the semiconductor (silicon) surface. Referring to Fig. 10, the impurity concentration is about 1 x 10 ²³ cm ^-3 at the topmost surface (implantation depth: 0 nm), while the impurity concentration decreases to about 1 x 10 ¹⁹ cm ^-3 or less at a depth of 11 nm from the topmost surface, which is at least four digits smaller than the impurity concentration at the topmost surface of the semiconductor region.

Accordingly, impurities intensively diffuse into the middle part 17h of the fin-type-semiconductor region 13b of Fig. 9B in the anneal process. Before the annealing process, however, the impurity concentration in the middle part 17h of the fin-type semiconductor region 13b was at least four digits smaller than that at the topmost surface of the impurity regions 50bl, 50br on both sides (see Fig. 8B). Therefore, even if impurities intensively diffuse into the middle part 17 of the fin-type semiconductor region 13b, the middle part 17 does not become a portion having the highest impurity concentration after the annealing process. In other words, the middle part 17h of the fin-type semiconductor region 13b has a lower impurity concentration than that of the upper part and both sides (collectively, a portion 17g) of the fin-type semiconductor region 13b.

In the fin-type semiconductor region 13b of Fig. 9B, it is the topmost surface portions of the impurity regions 50bl, 50br which have the highest impurity concentration and which therefore serve as a diffusion source of impurities which diffuse into a region under the gate electrode 15 (excluding the protruding portions 15a). As can be seen from Fig. 9B, however, the above-mentioned phenomenon, in which impurities are more concentrated than before the annealing process due to the impurity diffusion in the annealing process, does not occur in the regions which were originally the topmost surfaces of the impurity regions 50bl, 50br before the annealing process. Therefore, impurities do not excessively diffuse from the topmost surface portions of the impurity regions 50bl, 50br into a region under the gate electrode 15 (excluding the protruding portions 15a).

As has been described above, in the cross-sectional structure taken along line A-A in Fig. 7 (the cross-sectional structure of the fin-type semiconductor region 13b which is not covered by the gate electrode 15 (including the protruding portion 15a), the impurity concentration is the highest near the topmost surface in the middle region of the upper part of the fin-type semiconductor region 13b at the time the implantation process is performed. In addition, impurities are likely to be concentrated in the topmost surface of the middle region of the upper part of the fin-type semiconductor region 13b in the annealing process. The topmost surface of the middle region of the upper part of the fin-type semiconductor region 13b therefore serves as a diffusion source which supplies a large amount of impurities into a region under the gate electrode 15. The impurities diffusing from the middle region of the upper part of the fin-type semiconductor region 13b to the region under the gate electrode 15 thus has an increased diffusion length.

The cross-sectional structure taken along line B-B in Fig. 7 (the cross-sectional structure of the fin-type semiconductor region 13b having the protruding portion 15a of the gate electrode 15), on the other hand, does not have such a diffusion source (a diffusion source that causes concentration of impurities in the annealing process) as that in the cross-sectional structure taken along line A-A in Fig. 7. In the cross-sectional structure taken along line B-B in Fig. 7, the topmost surfaces of the sides of the fin-type semiconductor region 13b therefore have the largest diffusion length of impurities into a region under the gate electrode 15. However, the diffusion length of the impurities diffusing from the sides of the fin-type semiconductor region 13b into the region under the gate electrode 15 is shorter than that of the impurities diffusing from the middle region of the upper part of the fin-type semiconductor region 13b into the region under the gate electrode 15 in the cross-sectional structure taken along line A-A in Fig. 7.

In the cross-sectional structure taken along line A-A in Fig. 7, a portion of the fin-type semiconductor region 13b which is not covered by the gate electrode 15, that is, a portion of the fin-type semiconductor region 13b which is to be doped with impurities in an implantation process, is formed away from the gate electrode 15 by the protruding portion 15a of the present invention in the middle region of the upper part of the fin-type semiconductor region 13b. No such protruding portion 15a is formed in the sides of the fin-type semiconductor region 13b. Accordingly, the distance between the source-side and drain-side extension regions becomes about the same in the middle region of the upper part of the fin-type semiconductor region 13b and the sides of the fin-type semiconductor region 13b.

Finally, description will be given to impurity distribution before and after the annealing process in the cross-sectional structure taken along line C-C in Fig. 7. As shown in Fig. 8C, in the cross-sectional structure taken along line C-C in Fig. 7 (the cross-sectional structure in the gate length direction), the impurity region 50a (corresponding to the impurity region 50a in Fig. 8A) is formed on both sides of the gate electrode 15 in the upper part of the fin-type semiconductor region 13b. The impurity regions 50a are formed away from the gate electrode 15 by the protruding portions 15a of the present invention. When such a fin-type semiconductor region 13b is subjected to the annealing process, impurities in the impurity regions 50a shown in Fig. 8C diffuse in a wide range to form extension regions 17 as shown in Fig. 9C. Although not shown in the figure, in this annealing process, impurities in the impurity regions 50bl, 50br (see Figs. 8A and 8C) on both side of the fin-type semiconductor region 13b also diffuse into the middle of the fin-type semiconductor region 13b. As a result, the extension regions 17 are formed entirely in the height direction of the fin-type semiconductor region 13b. Moreover, since the impurity regions 50a are formed away from the gate electrode 15 by the protruding portions 15a of the present invention. The impurities in the impurity regions 50a can thus be prevented from diffusing into the region under the gate electrode 15 (excluding the protruding portions 15a) in the annealing process. In other words, the distance between the source-side and drain-side extension regions 17 can be prevented from being reduced. Degradation in characteristics such as generation of a leakage current can be prevented even if the fin-type semiconductor region 13b has a reduced length in the gate width direction.

Hereinafter, a semiconductor device and a manufacturing method thereof according to a second example embodiment of the present invention will be described with reference to the figures.

Figs. 11A through 11E are diagrams showing a structure of a semiconductor device according to the second example embodiment of the present invention, and more specifically, a semiconductor device having fin-type FETs. Fig. 11A is a plan view, Fig. 11B is a cross-sectional view taken along line A-A in Fig. 11A, Fig. 11C is a cross-sectional view taken along line B-B in Fig. 11A, Fig. 11D is a cross-sectional view taken along line C-C in Fig. 11A, and Fig. 11E is a cross-sectional view taken along line D-D in Fig. 11A. Note that the same components as those of the first example embodiment of Figs. 1A through 1E are denoted with the same reference numerals and characters, and overlapping description will be omitted.

The fin-type FET of the second example embodiment is different from that of the first example embodiment in that, as shown in Figs. 11A through 11E, the protruding portions 15a of the gate electrode 15 of the first example embodiment are replaced with impurity blocking portions 30 made of a material other than the gate electrode material, such as an insulating material. In other words, the gate electrode 15 of the present example embodiment has a uniform gate length in the gate width direction. Note that no impurity blocking portion 30 is formed between the fin-type semiconductor regions 13a through 13d. The impurity blocking portions 30 have a length of about 18 nm in the gate width direction, which is smaller than the length "a" (about 22 nm) of the fin-type semiconductor regions 13a through 13d in the gate width direction. The gate electrode 15 has a gate length of about 38 nm, while the impurity blocking portions 30 have a protruding length of about 5 nm in the gate length direction. The impurity blocking portions 30 have a thickness of about 60 nm which is the same as the thickness of the gate electrode 15.

Note that no gate insulating film 14au through 14du is formed under the impurity blocking portions 30 on the upper surfaces of the fin-type semiconductor regions 13a through 13d. The insulating sidewall spacers 16 are formed also on the side surfaces of the impurity blocking portions 30.

In the example embodiment described above, the impurity blocking portions 30 are formed on both sides of the gate electrode 15 on the upper surfaces of the fin-type semiconductor regions 13a through 13d. Impurity regions formed in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d in the doping process can thus be separated from the gate electrode 15. As a result, impurities in the impurity regions can be prevented from diffusing into a region under the gate electrode during annealing. In other words, the distance between source-side and drain-side extension regions 17 can be prevented from being reduced in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d due to the intensive diffusion to the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d in the annealing process. Accordingly, the distance between the source-side and drain-side extension regions 17 becomes the same in the middle regions of the upper parts of the fin-type semiconductor regions 13a through 13d and in the upper corners and both sides of the fin-type semiconductor regions 13a through 13d. As a result, degradation in characteristics such as generation of a leakage current can be prevented even when the fin-type semiconductor regions 13a through 13d have a reduced length in the gate width direction.

In the present example embodiment, the gate length of the gate electrode 15 is set to 45 nm or less, and the fin-type semiconductor regions 13a through 13d have a height larger than their length in the gate width direction. The above effect of preventing degradation in characteristics becomes significant especially in the case where a three-dimensional device such as a fin-type FET is reduced in dimensions by using such a gate electrode 15 and such fin-type semiconductor regions 13a through 13d.

In the present example embodiment, the step of depositing a material of the impurity blocking portions 30 and the step of patterning this material are added as compared to the first example embodiment. In this case, however, degradation in characteristics caused by providing the protruding portions 15a of the gate electrode 15 as in the first example embodiment can be prevented.

In the present example embodiment, the impurity blocking portion 30 may be removed after forming the impurity region (the extension regions 17 and the source/drain regions 27).

The disclosure of Japanese Patent Application No. 2008-140909 filed May 29, 2008 including specification, drawings, and claims is incorporated herein by reference in its entirety.