Title:
FLASH MEMORY IN WHICH DRAIN VOLTAGE-USE AND GATE VOLTAGE-USE REGULATORS OF MEMORY CELL ARE SHARED
Document Type and Number:
WIPO Patent Application WO/2011/111144
Kind Code:
A1
Abstract:
In a semiconductor storage device, inputs of first and second switches (202 and 203) are connected to the output of a regulator (201), the output of the first switch (202) is connected to a path for supplying drain voltage to a memory cell (207) at a time of a first mode, and the output of the second switch (203) is connected to a path for supplying gate voltage to the memory cell (207) at a time of a second mode. Furthermore, a fourth switch (204) is provided parallel to the second switch (203). The output side of the fourth switch (204) is connected to the output side of the second switch (203) and supplies the gate voltage to the memory cell (207) at the time of the first mode. Therefore, the two regulators that are the drain voltage-use regulator of the memory cell and the gate voltage-use regulator of the memory cell are combined as one regulator.
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Inventors:
MOCHIDA, Reiji (())
持田礼司 (())
MARUYAMA, Takafumi (())
持田礼司 (())
MARUYAMA, Takafumi (())
Application Number:
JP2010/007402
Publication Date:
September 15, 2011
Filing Date:
December 21, 2010
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
MOCHIDA, Reiji (())
持田礼司 (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
MOCHIDA, Reiji (())
持田礼司 (())
International Classes:
G11C16/06
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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Claims: