FLAT PANEL DISPLAY WITH A BARRIER BETWEEN THE FRAME AND PIXEL

Field of the Invention

[0001] This application is generally related to the field of displays and more particularly to flat panel displays using nanotubes and Thin Film Transistor (TFT) technology.

Background of the Invention

[0002] Flat panel display (FPD) technology is one of the fastest growing display technologies in the world, with a potential to surpass and replace Cathode Ray Tubes (CRTs) in the foreseeable future. As a result of this growth, a large variety of FPDs exist, which range from very small virtual reality eye tools to large hang-on-the-wall television displays.

[0003] It is desirable to provide a display device that may be operated in a nanotube configuration, and that exhibits a uniform, enhanced and adjustable brightness with good electric field isolation between pixels. Such a device would be particularly useful as a FPD, such as a low voltage nanotube display (LVND), incorporating a nanotube-based electron emission system, a pixel control system, and phosphor based pixels, with or without memory.

Summary of the Invention

[0004] A flat panel display comprising: a plurality of electrically addressable pixels; a conductive control frame surrounding each pixel; and an insulator barrier interposed between the conductive frame and the pixels to prevent electrical leakage between the frame and the pixel.

[0005] In one embodiment of the invention each pixel in the matrix is surrounded by an insulator interposed between the conductive frame and the pixels. The insulator is in the form of a barrier having a parallelepiped centrally removed to surround a pixel by a wall the height of which is a distance above the plane of the pixel.

Brief Description of the Drawings

[0006] It is to be understood that the accompanying drawings are solely for purposes of illustrating the concepts of the invention and are not drawn to scale.

The embodiments shown in the accompanying drawings, and described in the accompanying detailed description, are to be used as illustrative embodiments and should not be construed as the only manner of practicing the invention. Also, the same reference numerals, possibly supplemented with reference characters where appropriate, have been used to identify similar elements.

[0007] Figure 1 illustrates an exemplary display device according to an aspect of the present invention.

[0008] Figure 2 illustrates a control frame around each pixel and having a fixed voltage according to an aspect of the present invention.

[0009] Figure 2A illustrates a control frame according to another aspect of the present invention.

[00010] Figure 3 illustrates a circuit for driving the control frame of Figure 2 according to an aspect of the present invention.

[00011] Figure 4a illustrates a top view of a barrier interposed between a pixel and the control frame according to another aspect of the present invention.

[00012] Figure 4b illustrates a side view of the barrier shown in Figure 4a interposed between a pixel and the control frame according to an aspect of the present invention.

Detailed Description of the Invention

[00013] It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity, many other elements found in typical FPD systems and methods of making and using the same. Those of ordinary skill in the art may recognize that other elements and/or steps are desirable and/or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein.

[00014] Before embarking on a more detailed discussion, it is noted that passive matrix displays and active matrix displays are FPDs that are used extensively in various display devices, such as laptop and notebook computers, for example. In a passive matrix display, there is a matrix of solid-state elements in which each element or pixel is selected by applying a potential voltage to a corresponding row and column line that forms the matrix. In an active matrix display, each pixel is further controlled by at least one transistor and a capacitor that is also selected by applying a potential to a corresponding row and column line. Part of the invention lies in the recognition that a TFT-based display device with a control frame disposed thereon exhibits enhanced performance and effects useful for display

devices. Electron emission sources may be used with such a frame to form a cold cathode configuration, such as one including edge emitters and/or nanotube emitters.

[00015] According to an aspect of the present invention, a pixel matrix control system having a control frame around each pixel associated with a thin film transistor (TFT) circuit of a display device is used to provide a display characterized as having a good uniformity, adjustable brightness, and a good electric field isolation between pixels, regardless of the type of electron source used. For purposes of completeness, a TFT is a type of field effect transistor made by depositing thin films for the metallic contacts, semiconductor active layer, and dielectric layer. TFT's are widely used in liquid crystal display (LCD) FPDs.

[00016] The control frame surrounds the pixel. The TFT is disposed in an inactive area between the pixels (e.g. on an insulating substrate over the respective columns and rows). The control frame can accommodate carbon nanotube electron emission structures, and be suitable for operation at low voltages, such as voltages of less than around 40 volts. In an exemplary configuration, the device operates as a thin LVND.

[00017] According to an aspect of the present invention the electron emitting structures take the form of nanostructures, such as carbon nanotubes. The diameter of a nanotube is typically on the order of a few nanometers. According to an aspect of the present invention, single-wall carbon nanotubes (SWNTs) and/or multiple wall carbon nanotubes (MWNTs) may be used.

[00018] According to an aspect of the present invention, the control frame includes a plurality of conductors, typically arranged in a matrix having parallel horizontal conductors and parallel vertical conductors. Each pixel is bounded by the

intersection of vertical and horizontal conductors, such that the conductors surround the corresponding pixels to the right, left, top, and bottom in a matrix fashion. One or more conductive pads are electrically connected to the control frame. The control frame may be fabricated of a metal including, for example, chrome, molybdenum, aluminum, and/or combinations thereof.

[00019] According to an aspect of the present invention, the control frame can be formed using standard lithography, deposition and etching techniques. [00020] In one exemplary configuration, conductors parallel to columns and rows are electrically connected together, and a voltage is applied thereto. In another exemplary configuration, conductors parallel to columns are electrically connected together, and have a voltage applied thereto. Conductors parallel to the rows are also connected together, with a voltage applied thereto. In yet another exemplary configuration, a voltage is only applied to one of the parallel rows or columns of conductors.

[00021] According to an aspect of the present invention, a vacuum FPD incorporating a TFT circuit may be provided. Associated with each pixel element is a TFT circuit that is used to selectively address that pixel element in the display. In one configuration the TFT circuit includes first and second active devices electrically cascaded, and a capacitor coupled to an output of the first device and an input of the second device.

[00022] Referring now to the figures, Figure 1 illustrates a schematic cross- sectional view of a TFT anode based FPD 100 according to an aspect of the present invention. In the exemplary embodiment, display 100 is composed of an assembly 110 that includes an anode and that employs TFT circuitry to control the attraction of electrons, and a control frame structure 120 disposed on anode passivation layer

130. The control frame substantially surrounds each of the pixel elements, and in one configuration supports electron emitting nantoubes. In the illustrated embodiment, the pixel metal 140 operates as the anode, which attracts electrons emitted by the frame supported emitters.

[00023] Assembly 110 includes a plurality of conductive pads 140 fabricated in a matrix of substantially parallel rows and columns on a substrate 150 using conventional fabrication methods. Substrate 150 may be formed of a transparent material, such as glass, or a flexible material (such as a plastic with no internal outgassing) but may be opaque. Substrate 170, which serves to confine the FPD housing in an evacuated environment may also be made of a transparent (or at least translucent) material, such as glass or flexible material, but alternatively may be opaque. Conductive pads 140 may be composed of a transparent conductive material, such as ITO (Indium Titanium Oxide) or a non-transparent conductor such as Chrome (Cr), MoIy Chrome (MoCr) or aluminum.

[00024] Deposited on each conductive pad 140 is phosphor layer 180. Each phosphor layer(s) 180 is selected from materials that emit light 190 of a specific color, wavelength, or range of wavelengths. In a conventional RGB display, phosphor layer 180 is selected from materials that produce red light, green light or blue light when struck by electrons. In the illustrated embodiment, light (i.e. photons) is emitted in the direction of substrate 170 for viewing. If the pixel metal is of a transparent (or translucent) material (such as ITO) rather than opaque, light emissions 190 would be transmitted in both the directions of substrates 150 and 170 (rather than being reflected via the pixel metal to substrate 170 only, for example). [00025] Incorporated in the TFT circuit are conductive pixel column and row addressing lines associated with each of the corresponding conductive pads 140.

The pixel row and column addressing lines may be substantially perpendicular to one another. Such a matrix organization of conductive pads and phosphor layers allows for X-Y addressing of each of the individual pixel elements in the display as will be understood by those possessing an ordinary skill in the pertinent arts. [00026] Associated with each conductive pad 140/phosphor layer 180 is a TFT circuit 200 that operates to apply an operating voltage to the associated conductive pad 140/phosphor layer 180 pixel element. TFT circuit 200 operates to apply either a first voltage to bias an associated pixel element to maintain it in an "off ¹ state or a second voltage to bias the associated pixel element to maintain it in an "on" state, or any intermediate state. In this illustrated case, conductive pad 140 is inhibited from attracting electrons when in an "off ¹ state, and attracts electrons when in an "on" or any intermediate state.

[00027] TFT circuitry 200 biasing conductive pad 140 provides for the dual functions of addressing pixel elements and maintaining the pixel elements in a condition to attract electrons for a desired time period, i.e., time-frame or sub-periods of time-frame.

[00028] Referring now also to Fig. 2, there is shown a plan view of a control frame 220 suitable for use as control frame 120 of Fig. 1. Control frame 220 includes a plurality of conductors arranged in a rectangular matrix having parallel vertical conductive lines 230 and parallel horizontal conductive lines 240, respectively. Each pixel 250 (e.g., pad 140 and phosphor 180 of Fig. 1 ) is bounded by vertical and horizontal conductors or lines 230, 240, such that the conductors substantially surround each pixel 250 to the right, left, top, and bottom. One or more conductive pads 260 electrically connect conductive frame 220 to a conventional power source. In the illustrated embodiment of Fig. 2, four conductive pads 260 are

coupled to the conductive lines 230, 240 of frame 220. In an exemplary embodiment, each pad 260 is around 100 x 200 micrometers (microns) in size. FIG. 2a shows another exemplary configuration of a control frame structure similar to that of FIG. 2 (wherein like reference numerals are used to indicate like parts), but wherein two of the pads 260 of FIG. 2 are replaced by a single conductive bar or bus 260'. The conductive bar 260' is coupled to each of the parallel horizontal conductive lines 240 _a , 240 _b , 240 _c ,..., 240 _n at corresponding positions 260 _a , 260 _b ,

260 c 260 n along the bar. In the illustrated configuration, the row lines are substantially identical to one another and interconnect to the bar at uniform spacings along the length of the bar. This configuration provides for an equipotential frame configuration with minimal voltage drops as a function of frame position. [00029] In the illustrated embodiment of FIG. 2, control frame 220 (or 220') is formed as a metal layer above the final passivation layer (e.g., 130, Fig. 1 ). Pads 260 and metal lines that provide the control frame structure 220 remain free from passivation in the illustrated embodiment of FIG. 2. In an exemplary configuration, the control frame metal layer has a thickness of less than about 1 micron (μm), and a width on the order of about 16-19 microns, although other thicknesses and widths may be used depending on particular design criteria. [00030] Referring to Fig. 4a and FIG. 4b, a conductive control frame 430 surrounds a barrier insulating layer 450. Layer 450 abuts pixel 250 at each inner boundary edge 440 of the barrier layer to prevent electrical short circuits between the frame 430 and the pixel 250. This barrier layer 450, as seen, is disposed between the pixel and conductive frame. In one embodiment of the present invention the barrier insulating layer or frame 450 assumes essentially the same general shape as the control frame with a central area devoid of insulating material

and necessary to expose the phosphor material of the pixel so that it can be energized to emit light. The central area is shown as a rectangular or square configuration as is the barrier insulating layer 450. The configuration corresponds to the geometric shape of the frame 430. However, other geometric shapes are suitable as long as there is a proper insulative barrier layer or frame operative to prevent electrical shorts or leakage between the conductive control frame 430 and the pixel 250. While the conductive control frame 430 is shown as rectangular or square in shape the insulative barrier frame (450) about the pixel can be of another shape as long as it surrounds the pixel 250 and provides a suitable opening to expose the pixel phosphor. Typically the barrier insulation frame is 8 microns wide by 10 microns high.

[00031] Referring now to FIG. 1 , FIG. 4a and FIG. 4b, the insulating barrier layer 450 is formed from a negative photoresist coating layer, such as a 10 μm thick layer of a photoresist, spun over the assembly 110 (FIG. 1 ). In the embodiment shown in FIG 4b, the layer dimensions are of a height X equal to about 10 μm, and a width of about 8 μm wide. The resist layer may derive from a SU-8 photoresist product (SU-8 is a commercial negative-tone photoresist supplied from MicroChem Corp. of Newton, Mass.). SU-8 resists have high functionality, high optical transparency and are sensitive to near UV radiation. SU-8 (formulated in GBL) (gamma butyl rolacetone solvent) and SU-8 2000 (formulated in cyclopentanone) are chemically amplified; epoxy based negative resists. They can be used to provide thickness of 1 μm to 200 μm. A process for establishing a photoresist is as follows. First, a layer of SU-8 (e.g. 10 μm thick layer) is applied using a spin coat process. The layer is pre-baked at 65 ⁰ C for one minute and then at 95 ⁰ C for ten minutes. The pre-baked layer is then exposed to UV radiation for about one minute through an

appropriate mask. After exposure, the layer is baked by ramping the layer from 65°C to 95 ⁰ C during a one minute interval and then maintaining the temperature at 95 ⁰ C for about three minutes. The baked layer is then allowed to cool to ambient temperature and then developed by heating to between 18O ⁰ C and 200 ⁰ C for between 12 to 15 minutes to crosslink. In this manner, the developed layer is inert and does not outgas.

[00032] Other types of photoresists are commercially available from other sources and are well known. See also U.S. Patent No. 4,882,245 entitled "Photoresist Composition and Printed Circuit Boards and Packages Made Therewith" issued on Nov. 21 , 1989 to J. D. Gerlone and assigned to IBM. The patent shows uses of SU-8 as well as typical compositions. Mask images may be formed by contact-proximity or projection printing to establish the pattern over the area to be exposed to create the insulator. These photoresists are capable of high aspect ratios and upon exposure to UV light create substantially straight sidewalls 460. The SU-8 layer may be exposed through an appropriate mask to yield cross-linked SU-8 regions and non-cross-linked regions in forming a thick filmed insulation. As will be understood by those possessing an ordinary skill in the pertinent art, the positioning of the insulator region is dependent upon patterned coating. In an exemplary configuration, the insulator has a thickness of about 10 microns and width of about 8 microns although other thicknesses and widths may be used depending on particular design criteria.

[00033] It is to be understood that the conductive control frame 430 of FIG. 4 or 220 of FIG. 2 surrounding each pixel 250 may contain nanotubes which will be used as the control source of electrons to activate the phosphor coating on the pixels. In operation, a negative voltage applied to the conductive control frame 220 (FIG. 2)

relative to the pixel provides the necessary threshold voltage required to create a field necessary to cause the nanotubes to start emitting electrons. As the voltage on the pixel 250 increases, as a function of the amplitude of the data to be displayed, the nanotubes emit electrons. The emitted electrons follow the field lines and strike the phosphor causing the phosphor to emit light. The light is emitted as electrons associated with the phosphor molecules which were dislodged from their orbit around the nucleus, by the electrons emitted by the nanotubes, return to their correct position.

[00034] According to an aspect of the present invention, nanostructures are provided upon control frame of 220. The nanostructures may take the form of carbon nanotubes, for example. The nanostructures may take the form of SWNTs or MWNTs. The nanostructures may be applied to the control frame using any conventional methodology, such as spraying, growth, electrophoresis, or printing, for example.

[00035] While the vertical line conductors 230 and horizontal line conductors 240 frame each pixel 250 above the plane of the pixels 250 in the illustrated embodiment (see, e.g., Fig. 2), other configurations are contemplated, such as where the conductors are disposed in the same plane as the pixels. Further yet, conductors 230, 240 may be connected in a number of configurations. For example, in one configuration, all horizontal and vertical conductors are joined together as shown in Figure 2 and a voltage is applied to the entire control frame configuration. In another configuration, all horizontal conductors 240 are joined and separately all vertical conductors 230 are joined. In this connection configuration the horizontal conductors 240 and vertical conductors 230 are not electrically interconnected. Thus, a voltage may be applied to the horizontal conductor array, and a separate

voltage may be applied to the vertical conductor array. Other configurations are also contemplated, including for example, a configuration of all horizontal conductors only, or a configuration of all vertical conductors only. For example, the control frame may include only metal lines parallel to the columns or only metal lines parallel to the rows.

[00036] Regardless of the particulars, a voltage (V _T N) equal to (V _P IXEL(I _O W) - (VTHN)) may be applied to the frame via pads 260, where (V _T HN) represents the nanostructure emitting threshold and VPIXELø _OW) represents the minimum pixel voltage. This voltage may serve to keep the frame supported nanostructures to just below the emitting threshold when the pixel voltage is in it's "OFF" state. This permits the pixel voltage to transition from the "OFF" state to the "ON" state and all voltages in between to cause changes in brightness (Gray Scale). [00037] The anode (pixel) voltage (V _P | _X EL) of each pixel determines the brightness or color intensity of that pixel. By positively biasing the pixel voltage (VPIXEL) relative to the voltage of the frame, the voltage on that pixel is increased beyond the emitting threshold of the nanotubes (V _THN ), such that the frame supported nanostructures in the region around a biased pixel are caused to emit electrons, which are then attracted to the positively biased pixel. In other words, when the voltage applied to the pixel (Vpιχ _E ι_) relative to the voltage applied to the control frame nanostructures (VTN), exceeds the emission threshold voltage (VTHN), electrons are emitted from the nanostructures. The electrons emitted from the nanostructures move to the anode (phosphor), thereby causing the phosphor to emit light, VPIXEL ≥ VTN ⁺ V _TH N- The wavelength of the emitted light depends upon the phosphor. The electron flow to the anode (i.e. pixel current) is a function of the pixel voltage, thereby producing an illumination, which is proportional to the amplitude of

column data, when the voltage signal applied to the pixel is proportional to the amplitude of the data.

[00038] According to an aspect of the present invention, control of one or more of the TFTs associated with the display device of the present invention may be accomplished using the circuit 300 of Fig. 3. Circuit 300 includes first and second transistors 310, 330 and capacitor 320 electrically interconnect with a pixel, e.g., pad 140, Fig. 1.

[00039] In general, the voltage used to select the row (V _Row ) is equal to the fully "on" voltage of the column (Vc) . The row voltage in this case causes the pass transistor 310 to conduct. The resistance of pass transistor 310, capacitor 320 and the write time of each selected pixel row determines the voltage at the gate of transistor 330, as compared to Vc. Using a voltage V _Row higher than the fully "on" voltage (Vc) increases the conduction of transistor 310, reducing its resistance and resulting in an increase in pixel voltage (Vpjχ _θ ι) and enhanced brightness. Thus, the selection voltage for the row may be higher than the highest column voltage, thereby causing transistor 310 to turn on heavily, thereby reducing the associated resistance and providing a greater voltage on the gate of transistor 330. VANODE is the power supply voltage, and may be on the order of about 40V. In such a configuration, VpixELLow may be on the order of around 6-12 V.

[00040] While there has been shown, described, and pointed out fundamental novel features of the present invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the apparatus described, in the form and details of the devices disclosed, and in their operation, may be made by those skilled in the art without departing from the spirit of the present invention. For example, the control frame described previously may be

used with any display which uses electrons generated by any source or charged particles to form an image, such as an LVND, Electrophoretic, or VFD display. As discussed above, it is also understood that the present invention may be applied to flexible displays in order to form an image thereon.

[00041] It is expressly intended that all combinations of those elements that perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated.