FLIP-CHIP SEMICONDUCTOR PACKAGES AND METHODS FOR THEIR PRODUCTION

The invention relates to semiconductor packages including a semiconductor chip mounted by a flip-chip technique and methods to assemble the semiconductor packages . In particular, the invention relates to the problem of the overflowing of underfill material onto undesired portions of the package .

In semiconductor packages which include semiconductor chips mounted by a flip-chip technique, the volume or cavity between the active surface of the chip and upper surface of the substrate is normally filled by an underfill material which typi- cally comprises an epoxy. The underfill material covers the flip-chip contacts, which are typically solder balls, to protect the electrical contacts from environmental damage . The underfill material typically spreads around the side faces of the chip forming so-called fillets .

The problem of the undesired overflow or spread of the underfill material is well-known and causes many problems in the manufacturing process of flip-chip semiconductor packages . This leads to higher production losses and increased manufac- turing costs . Undesired over-spill of the underfill material onto the rear surface of the chip has been found to be a particular problem for semiconductor packages which include thinner semiconductor chips .

Over-spill of the underfill material onto the rear side of the semiconductor chip can result in inaccurate cutting during the singulation of the package . Contamination of the rear side of

the chip by the underfill material can also cause problems in stacked semiconductor packages as the upper chip cannot be reliably stacked as the rear surface of the lower chip is uneven due to the spilt underfill material . The excessive spreading of the underfill material around the chip over the surface of the substrate can cover further contact areas which cannot then be used. The package must in these cases be discarded.

Various approaches have been tried to reduce this problem. US 6, 614 , 122 discloses an apparatus in which the substrate includes a series of trenches and dams positioned around the chip in order to hinder the spreading of the underfill material . This method has the disadvantage of being expensive as complex additional structures have to be provided in the sub- strate . Also, valuable space on the substrate is taken up by these structures which is disadvantageous as either the size of the package is increased or the packing density of the chips on the substrate is reduced.

US 6, 455 , 933 discloses a method in which barriers positioned at the side walls of the chip are used in order to try to control the spread of the underfill material . This method is also expensive since the complexity of the substrate as well as the production process is increased.

An obj ect of the invention is, therefore, to provide semiconductor packages and methods for producing the packages in which the undesired spread and over-spill of the underfill material is reduced and which avoids the disadvantages of the known methods .

This obj ect is achieved by the subj ect matter of the independent claims . Further improvements arise from the subj ect matter of the dependent claims .

The invention provides a semiconductor chip which has an active surface with integrated circuit structures and chip contact pads which enable the integrated circuit structures of the chip to be accessed. The chip contact pads are disposed on the active surface in a flip-chip arrangement and are, there- fore, arranged in rows and columns , a typical arrangement includes three columns of chip contact pads disposed towards the periphery of each of the sides of the active surface of the chip .

The semiconductor chip also has a passive surface with no integrated circuit structures . The active surface and passive surface lie in essentially parallel planes . In this context , essentially parallel is used to include deviations from an exactly parallel caused by the manufacturing process . The semi- conductor chip also has side faces located between and adj oining the active and passive surfaces . The semiconductor chip of the invention is characterised in that the active surface of the chip is laterally smaller than the passive surface of the chip .

Therefore, the semiconductor chip according to the invention has at least one side face in which the whole of the side face lies in a plane which is not perpendicular to either the active or passive surface . Therefore, the passive surface pro- vides an over-hanging portion with respect to the edge formed between the active surface and the side face . The passive surface, therefore, protrudes laterally outwards on at least one

side of the semiconductor chip with respect to the edge of the active surface . The side face has a non-straight or non- perpendicular profile .

The semiconductor chip according to the invention, therefore, provides a means by which the flow of the underfill material can be controlled and the over-spill of the material on to the passive rear side of the chip hindered. The over-hanging or protruding portion provides a guide which hinders the movement of the underfill material upwards and guides the underfill material laterally outwards . The semiconductor chip when mounted by a flip-chip technique on a rewiring substrate can, therefore, be underfilled more reliably than semiconductor chips in which the active surface is of essentially the same size as the passive surface and in which the side faces lie in a plane essentially perpendicular to the active surface .

Additionally, since the flow of the underfill material is better controlled and over-spill prevented, the amount of under- fill material applied to the package can be reduced as it is not necessary to over-compensate for the possible undesired over-spill . This in turn further reduces the likelihood of over-spill .

Preferably, at least one side face of the semiconductor chip has a step shape . This is advantageously formed by providing a cutout in the side face of the chip with a square or rectangular cross-section . The cutout is provided in the edge of the chip between the active surface and side face . This provides a inward step in the side face from the active surface and an overhanging portion which proj ects laterally from the passive

surface . The protruding portion forming the step, therefore, has an approximately square or rectangular cross-section.

The provision of the step reliably prevents the over-spill of the underfill material and the protruding portion hinders the upward movement of the underfill material and guides the material laterally outwards .

Preferably, the step has a step width of approximately 10 μm to approximately 12.5 μm (micron) . This reliably improves the control of the underfill material without reducing the mechanical strength of the chip . Also, the packing density of the chips in the wafer is not adversely affected as the size of the saw streets or singulation trenches positioned between adj acent device positions in the wafer is not disadvanta- geously increased.

Alternatively, at least a portion of one side face lies in a plane inclined at an angle to the active surface . Preferably, the portion of the side face adj oining the active surface is inclined at an angle to the active surface . The side face, therefore, lies at an angle of greater than 90 ° to the active surface . This provides an outwardly inclining side face adj acent to the active surface which is able to hinder the over- spill of the underfill material on to the passive rear surface .

Alternatively, the whole of least one side face lies in a plane inclined at an angle to the active surface and lies in a plane inclined at an angle of greater than 90 ° to the active surface . This provides an edge with an internal angle of more

than 90 ° . This enables a simplified manufacturing process as the inclined side face can be made in a single step .

Preferably, at least a portion of at least one side face lies in a plane inclined at an angle of between approximately 120 ° and approximately 150 ° to the active surface . Approximately in this case includes small variations in the angle caused by normal manufacturing processes . These angles of the side face provide a good guide for the underfill material and reliably prevent over-spill of the material .

More preferably, all of the side faces of the semiconductor chip have the same form. For example, if the chip is laterally square or rectangular, the four side faces include a step of approximately the same dimensions or at least a portion of the four side faces is inclined at an angle to the active surface . This has the advantage of simplifying the manufacturing process and providing a chip in which the flow of the underfill material is controlled or guided equally around the periphery of the chip . This further hinders the over-spill of the material onto the passive rear surface .

Alternatively, each pair of two opposing sides has the same form but adj acent side faces have a different form. For exam- pie, two opposing side faces may include a step and the second pair of opposing side faces lie in an inclined plane . This enables the side faces lying in parallel to be manufactured in the same step which reduces the complexity of the process, but also enables differences in the substrate layout, for example, to be accommodated. Differences in the substrate layout or direction of the flow of the underfill may be advantageous accommodated by this arrangement .

The invention also relates to a semiconductor package including a semiconductor chip, according to one of the embodiments of the invention previously described, in which the active surface of the chip is laterally smaller than the passive surface . The package also includes a first substrate with a first plurality of inner contact pads on its upper surface . If the semiconductor chip is mounted to the first substrate by a flip-chip technique then the lateral arrangement of the inner contact areas corresponds to, and essentially matches , the arrangement of the chip contact pads .

Preferably, the first substrate also includes a rewiring structure including conductor tracks and vias which electri- cally connect the inner contact pads to outer contact areas disposed on the bottom surface of the rewiring substrate . This type of substrate allows the arrangement of the inner contact areas to be different to that of the outer contact areas and, in the case of the flip-chip package enables a fan-out of the contact areas .

The semiconductor chip according to one of the embodiments of the invention already described is , in the context of the semiconductor packages, denoted as a first semiconductor chip .

The first semiconductor chip is mounted on the substrate by flip chip contacts located between the chip contact pads and inner contact areas of the first substrate . The volume or cavity between the active surface of the first semiconductor chip and the upper surface of the substrate is largely filled with underfill material . Largely in this case is used to include

any small voids or air bubbles caused by incomplete filling of the space .

Since the first semiconductor chip has an active surface which is laterally smaller than the passive surface, the underfill material can be reliably applied to the package . The flow of the underfill material is guided and controlled by the side faces so as to hinder the undesired over-spill of the material .

In a further embodiment of the invention, the semiconductor package further includes a second semiconductor chip . The first and second semiconductor chips form a stacked package . The second semiconductor chip is laterally smaller than the first semiconductor chip and is located on the passive rear surface of the first semiconductor chip . The passive surface of the second chip is , preferably, mounted on the passive surface of the first chip by epoxy adhesive or known die attach materials . The second semiconductor chip is electrically con- nected to the substrate by bond wires .

This semiconductor package, therefore, includes a second substrate which also includes a second plurality of inner contact areas located towards the periphery of its upper surface in addition to a first plurality of inner contact areas which, in this embodiment, have a flip chip arrangement and are located towards the lateral centre of the upper surface of the second substrate . The second semiconductor chip is electrically connected to the second plurality of inner contact areas . The substrate also includes a respective rewiring structure for the second plurality of inner contact areas .

Since the flow of the underfill of the first semiconductor chip is better controlled so that the rear surface of the chip is not contaminated by underfill material, the second upper semiconductor chip can be more reliably mounted on the passive surface of the first chip .

The invention also relates to a third embodiment of a semiconductor package . This semiconductor package also includes two semiconductor chips but in this case the first semiconductor chip, which has an active surface which is smaller than the passive surface, is mounted on a third semiconductor chip .

The third semiconductor package includes a third substrate with a plurality of inner contact pads located at the periph- ery of its upper surface . A third semiconductor chip has an active surface with chip contact pads positioned towards the periphery of the active surface and a passive surface . The third semiconductor chip is mounted on the upper surface of the third substrate by its rear passive surface and electri- cally connected to the inner contact areas of the substrate by bond wires .

The third semiconductor chip is laterally larger than the first semiconductor chip so that the first semiconductor chip is located on the active surface of the third semiconductor chip to form the stack and is positioned between the chip contact areas on the active surface of the chip .

The volume or cavity formed between the active surface of the first semiconductor chip and the active surface of the third semiconductor chip is largely filled with underfill material .

This semiconductor package has the advantage that since the first semiconductor chip can be reliably underfilled using less underfill material, spreading of the material onto the bond wire which surround the first chip is prevented. This increases the reliability of the stacking process and, therefore, reduces the number of defective packages manufactured.

The semiconductor chips are typically encapsulated in mold ma- terial to protect the chips and the electrical connections from environmental and mechanical damage .

The invention also relates to methods to produce a semiconductor chip with an active surface which is laterally smaller than the passive surface and to methods to assemble semiconductor packages including this semiconductor chip .

A method to produce a semiconductor chip includes the steps of providing a semiconductor wafer including a plurality of pack- age or device positions arranged in rows and columns forming a grid. Each package position includes a first semiconductor chip with an active surface and chip contact pads disposed on the active surface in a flip chip arrangement . Typically saw streets are positioned between adj acent device positions . A sawing tape is attached to the rear passive side of the wafer .

The first semiconductor chips are separated from the wafer by a sawing process in which the cut is made from the active surface of the wafer . According to the invention, a semiconductor chip with an active surface which is laterally smaller than the passive surface is formed as a result of the sawing process .

The sawing process is extremely advantageous as it is relatively quick and well-known so that the existing process line can be used with only a minimum amount of modification to fab- ricate the semiconductor chip of the invention . This significantly reduces the start-up costs .

A sawing process is also extremely flexible as a wide variety of forms for the sides faces of the semiconductor chip can be provided simply by changing the shape of the saw blade . This further reduces manufacturing costs . Additionally, the use of sawing prevents contamination of the active surface as chemicals are not used, as would be used if an etching process was used to singulate the chips from the wafer for example .

Normally, the sawing process would take place for all of the rows or columns of chips in one direction of the wafer by making a series of parallel cuts in the approximate centre of each of the singulation trenches . Then, either the wafer or blade is rotated by 90 ° and all of the remaining rows or columns of chips singulated in the same way. This enables all of the chips in the wafer to be separated in an efficient and cost effective manner .

In a first embodiment of the invention, the chip is separated from the wafer by a first sawing step using a first saw blade and a second sawing step using a second saw blade . The first cut only partially separates the chip from the wafer and the second cut penetrates the width of the wafer singulating the chip .

The width of cut of the first saw blade is different to the width of the cut of the second saw blade . This results in the semiconductor chip being formed with at least one side face having a step shape . If the semiconductor chip is separated from the wafer by cutting from the active surface then the cut produced by the first saw blade is wider than that of the second saw blade . This provides a semiconductor chip in which the active surface is laterally smaller than the passive surface and in which the side face includes a step or step form.

Preferably, the first and second saw blades are essentially straight sided blades which produce an essentially straight sided cut . Essentially, in this case includes small deviations from an exact straight cut caused by the normal manufacturing processes .

Preferably, the cut of the first saw blade has a width of between approximately 40 μm to approximately 45 μm and the cut of the second saw blade has a width of between approximately 20 μm to approximately 25 μm. The step formed in the side face of the semiconductor chip, therefore, has a step width of approximately 10 μm to 12.5 μm. This provides a sufficient step in the side face to prevent the undesired over-spill of the underfill material without necessitating a reduction in the packing density of the chips in the wafer .

Alternatively, the semiconductor chip is separated from the wafer by a first sawing step and a second sawing step in which first sawing step being performed with a profile saw . The profile saw has a third saw blade with a V-shaped cross- section. Therefore, at least a portion of one side face of two adj acent semiconductor chips is formed which lies in a

plane at an inclined angle to the active surface . The angle of the third blade correspondes to the desired angle of inclination of the side face to the active surface . The solid angle of the third saw blade is , therefore, preferably, be- tween approximately 30 ° and approximately 60 ° .

The use of a profile saw with a saw blade having a V-shaped cross-section advantageously allows the singulation of the semiconductor wafer from the wafer with a side face at the desired angle of inclination to the active surface .

If only a portion of the side face is desired to have an inclined angle, then a first partial cut is made with the profile saw to form a trench with a V-shaped cross-section . A second cut is made with a saw blade having an essentially straight sided blade to singulate the chip from the wafer .

Alternatively the semiconductor chip is separated from the wafer by a single sawing step using a profile saw having a third saw blade . The third saw blade has a V-shaped cross- section and at least one side face of the semiconductor chip is formed which lies in a plane at an inclined angle to the active surface . Preferably, the portion of at least one side face or the whole side face lies in a plane at an angle of approximately 120 ° to approximately 150 ° to the active surface .

The invention also relates to methods to assemble semiconductor packages which include the semiconductor chip according to one of the embodiments of the invention already described. A method to produce a semiconductor package including the steps of providing a substrate including a plurality of inner con-

tact areas on its upper surface . The substrate, preferably, also includes a rewiring structure and the inner contact areas are disposed on the upper surface with a lateral arrangement which corresponds to the lateral arrangement of the chip con- tact pads .

A first semiconductor chip having an active surface which is laterally smaller than the passive surface is provided . The semiconductor chip is mounted on and electrically connected to the substrate by flip-chip contacts located between the chip contact pads and inner contact areas of the substrate . Typically a solder reflow process is used.

The volume or cavity between the active surface of the first semiconductor chip and the upper surface of the substrate is then largely filled with underfill material .

If an encapsulated package is desired, the chip and upper surface of the substrate are embedded in a plastic mold material using processes known in the art .

Therefore, the semiconductor package according to the invention can be assembled using known techniques with only a minimal change to the process line to accommodate the first semi- conductor chip . Thus a higher proportion of correctly functioning packages is provided without a large increase in production costs .

Preferably, the underfill material is dispensed by a dispens- ing tip having an angled tip, the tip being angled to more accurately dispense the underfill material adj acent to the upper surface of the substrate . This allows the more reliable under-

filling of the cavity and further prevents over-spilling of the underfill material onto the passive rear surface of the chip .

The invention also relates to methods of assembling semiconductor packages including two stacked semiconductor chips which include the first semiconductor chip having an active surface which is laterally smaller than the passive surface . The method includes the following additional steps . Firstly, an additional plurality of second contact areas are provided towards the periphery of the upper surface of the first substrate to provide a second substrate .

A second semiconductor chip having an active surface with chip contact pads and a passive surface is provided. The second semiconductor chip is laterally smaller than the passive surface of the first semiconductor chip .

The second semiconductor chip is positioned on and attached to the passive rear surface of the semiconductor chip and electrically connected to the substrate by bond wires between the chip contact pads and the second contact areas .

Alternatively, a method to produce a semiconductor package in which the first semiconductor chip is mounted on a third semiconductor chip has the following steps .

A third substrate is provided which has a plurality of inner contact pads located at the periphery of its upper surface . A third semiconductor chip including an active surface with chip contact pads and a passive surface is provided and mounted on the upper surface of the substrate by its rear passive sur-

face . The third semiconductor chip is electrically connected to the substrate by bond wires between the chip contact pads and inner contact pads on the substrate .

The first semiconductor chip including flip-chip contacts, as previously described, is mounted on the active surface of the third semiconductor chip with its active surface facing the active surface of the third semiconductor chip . The volume or cavity between the active surface of the first semiconductor chip and the active surface of the third semiconductor chip is largely filled with underfill material covering the flip-chip contacts . The side faces of the first semiconductor chip control the spread of the underfill material .

The semiconductor chip, according to the invention, which has a smaller footprint at the active surface of the die or chip minimises the underfill spread out around the chip . Therefore, it is possible to further reduce the size of the semiconductor package . This is a particular advantage for a semiconductor package with stacked semiconductor chips since, as the amount of underfill spread out around the chip is reduced, the distance between the side faces of the upper semiconductor chip to the contact pads and bond wires of the lower chip can be reduced.

Also, since the rear surface of the lower semiconductor chip in the stack remains uncontaminated by underfill material, the upper chip of the stack can be more reliably mounted. The known problems associated with the lack of adhesion between the adhesive material used to mounted the upper ship with the spilt underfill material is avoided. Also the problems associated with non-planar stacking of the upper chip and the re-

suiting unreliable production of the electrical connections by the bond wires are avoided.

The invention, therefore, provides a package in which the un- derfill material overflow or overspill problem is controlled by the design of the package . Therefore, it is possible to avoid the problems associated with the dispensing of the underfill material .

Conventionally, the flow of the underfill material is controlled by adjusting the dispensing tip distance, a diameter of the dispensing tip and the volume of the dispensing paste and/or the viscosity of the underfill material . The flow of the underfill material and consequently the undesired over- spill or spread of the underfill material is difficult to control solely by these adj ustments . Therefore, the semiconductor chip, according to the invention, and the semiconductor packages in which it is used provide a more reliable assembly process which results in fewer defective packages which have to be discarded.

The invention will now be described with reference to the diagrams .

Figure 1 shows a semiconductor package according to a first embodiment of the invention,

Figure 2 shows a semiconductor package including two stacked semiconductor chips according to a second embodiment of the invention, and

Figure 3 illustrates a semiconductor package including two stacked semiconductor chips according to a third embodiment of the invention .

Figures 4 to 7 show the singulation of a semiconductor chip from a wafer in which a step is formed in the side faces of the chip .

Figure 4 shows a cross-sectional view of a portion of a wafer including a plurality of device positions,

Figure 5 illustrates the partial singulation of the chips from the wafer of figure 4 ,

Figure 6 shows the singulation of the chips of figure 5 from the wafer, and

Figure 7 shows a semiconductor chip of Figure 6 indicating the dimensions of the step in the side faces .

Figure 8 illustrates the dimensions of the two saw cuts used in the singulation process of figures 4 to 7 ,

Figure 9 shows the singulation of semiconductor chips accord- ing to a second embodiment of the method of the invention,

Figure 10 shows the partial singulation of semiconductor chips according to a third embodiment of the method of the invention, and

Figure 11 shows the singulation of the chips of figure 10 from the wafer .

Figure 1 shows a semiconductor package 1 including a semicon- ductor chip 2 mounted on a rewiring substrate 3 according to a first embodiment of the invention . The semiconductor chip 2 has an active surface 4 and a passive surface 5. The active surface 4 and passive surface 5 lie in essentially parallel planes . The active surface 4 includes a plurality of integrated circuit devices , which are not shown in the figure, and a plurality of chip contact pads 6 which provide the electrical connection to the integrated circuit devices . In this embodiment of the invention, the four side faces 7 of the semiconductor chip 2 include a step 8 along their length . The step is formed in the edges formed between the active surface 4 and side faces 7.

In the cross-sectional view of Figure 1 , the side faces 7 , therefore, include a rectangular cutout 9 in the active surface 4 of the semiconductor chip 2 and a rectangular protruding portion 10 , the upper surface of which is co-planar with the passive surface 5 of the semiconductor chip 2. The protruding portion 10 provides an over hang . The step 8 is char- acterised by a step width a and a step height b . This is more clearly seen in Figure 7. The semiconductor chip 2, therefore, has an active surface 4 which is laterally smaller than the passive surface 5.

The semiconductor chip 2 is mounted on a rewiring substrate 3. The body of the rewiring substrate 3 comprises an electrically insulating material such as BT or FR4 and has an upper surface

11 with a plurality of inner contact areas 12. The inner contact areas 12 are positioned towards the lateral centre of the upper surface 11 of the rewiring substrate 3 and have a lateral arrangement which corresponds to the lateral arrangement of the chip contact pads 6.

The semiconductor chip 2 is mounted on, and electrically connected to, the substrate 3 by flip chip contacts 13 comprising microscopic solder balls . The flip-chip contacts 13 are dis- posed between the chip contact pads 6 and inner contact areas 12.

The inner contact areas 12 are electrically connected by electrically conducting conductor tracks 14 and vias 15 to outer contact pads 16 which are located on the bottom surface of the substrate 3. This provides the rewiring structure of the substrate 3. Macroscopic solder balls 17 are mounted on the external contact areas 16 and enable the package 1 to be mounted on an external substrate such as a printed circuit board which is not shown in the figure .

The upper surface 11 of the rewiring substrate 3 is covered by a solder resist layer 18 which leaves the inner contact areas

12 uncovered by the solder resist layer 18. The solder resist layer 18 prevents the solder balls 13 from spreading outside of the contact areas 12 during the solder reflow process .

A cavity 19 is formed between the active surfa ^' ce 4 of the semiconductor chip 2 and the upper surface 11 of the rewiring substrate 3. The cavity or volume 19 is filled by an underfill material 20 which comprises an epoxy resin including filler particles . The underfill material 20 also fills the cutout 8

in the side faces 7 of the semiconductor chip . The cutouts 8 and protruding portions 10 of the side faces 7 hinder the overspill of the underfill material 20 onto the passive rear surface 5 of the semiconductor chip 2.

The underfill material 20 is advantageously dispensed using a dispensing needle 21 which has an angled tip 22. The tip 22 has an angle which allows the underfill material 20 to be dispensed at a shallow angle to the upper surface 11 of the re- wiring substrate 3. This further reduces the possibility of over-spill of the underfill material . The semiconductor package 1 is typically then encapsulated in a mold material which is not shown in the figure for clarity .

Figure 2 shows a semiconductor package 23 according to a second embodiment of the invention . A semiconductor package 23 includes two stacked semiconductor chips . In all of the figures , features which are essentially the same are denoted by the same reference number and are not necessarily described again .

In this embodiment of the invention, the package 23 includes a rewiring substrate 54 which further includes a second plurality of inner contact areas 25 which are positioned on the up- per surface 11 and towards the periphery of rewiring substrate 54. The second plurality of inner contact areas 25 , therefore, lie laterally outside of the first plurality of contact areas 12. The second plurality of inner contact areas 25 enable the upper semiconductor chip 26 of the stack to be electrically connected to the rewiring substrate 54.

The lower chip in the stack 27 is similar to that of the semiconductor chip 2 of the first embodiment and is mounted by flip chip contacts 13 to the first plurality of inner contact areas 12 positioned towards the lateral centre of the sub- strate 54.

The semiconductor chip 27 is distinguished from that illustrated in Figure 1 in that one of the side faces 28 is inclined at an angle c° to the active surface 4 of the semicon- ductor chip 27 and does not include a step . In this embodiment of the invention, the side face 28 is inclined at an angle of approximately 120 ° to the active surface 4. As in the first embodiment of figure 1, the cavity 19 formed between the active surface 4 and upper surface 11 of the substrate 3 is filled with underfill material 20.

The second upper semiconductor chip 26 has an active surface 29 with integrated circuit devices and a plurality of chip contact pads 31 which are arranged towards the periphery of the active surface . The semiconductor chip 26 is mounted by its rear surface 30 to the passive rear surface 5 of the lower semiconductor chip 27 by an adhesive layer 32. In this embodiment, the upper semiconductor chip 26 is laterally smaller than the active 4 and passive 5 surfaces of the lower semicon- ductor chip 27. The upper semiconductor chip 26 can be of an equal size to the lower semiconductor chip 27 if an adhesive tape is used to mounted the upper semiconductor chip 26 to the lower semiconductor chip 27 rather than the adhesive paste 32.

The upper semiconductor chip 26 is electrically connected to the substrate 54 by bond wires 33 between the chip contact pads 31 and second plurality of inner contact areas 25. The

upper semiconductor chip 26, the lower semiconductor chip 27 , the bond wires 33 and upper surface 11 of the substrate 54 are encapsulated in a mold material 34.

Figure 3 illustrates a semiconductor package 35 including two stacked semiconductor chips according to a third embodiment of the invention . The semiconductor package 35 includes a third substrate 36 which has only a second plurality of inner contact areas 25 located on its upper surface towards the periph- ery of the upper surface . The second plurality of contact areas 31 are electrically connected by conductor tracks 14 and vias 15 to outer contract areas 16. The semiconductor package 35 includes a semiconductor chip 53 which has an active surface 29 with chip contact pads 31 located towards the periph- ery . The side faces of the semiconductor chip 53 lie essentially perpendicularly to the active surface 29 and passive surface 30 of the semiconductor chip 53. The semiconductor chip 53 is a third type of semiconductor chip .

In the semiconductor package 35 , the semiconductor chip 53 is mounted to the upper surface of the substrate 36 by its passive rear surface 30 by die attach material 32. The semiconductor chip 53 is electrically connected to the third substrate 36 by bond wires 33 between the chip contact pads 31 and second inner contact areas 25. The semiconductor chip 53 is the lower semiconductor chip in the stack of semiconductor package 35.

The semiconductor chip 2 , which is essentially the same as the semiconductor chip 2 shown in figure 1, is mounted by flip chip contacts 13 on the central portion of the upper active surface 29 of the semiconductor chip 53. The semiconductor

chip 2 is the upper semiconductor chip in the stack of semiconductor package 35. Semiconductor chip 2 is , therefore, laterally smaller than the distance between the semiconductor 53. The cavity 19 formed between the active surface 4 of the semi- conductor chip 2 and the active surface 29 of the semiconductor chip 26 is filled with underfill material 20.

The package encapsulation is not shown in figure 3 for clarity .

Figures 4 to 7 illustrate the separation or singulation of the semiconductor chips from a wafer according to a first embodiment of the method of the invention .

Figure 4 shows a wafer 37 which includes a plurality of device positions 38 which are arranged in rows and columns . The device divisions 38 are separated from the adj acent positions by singulation trenches or saw streets 39, the approximate lateral centre of which is denoted by the lines 40. The singula- tion trenches 39 have a square grid arrangement . The passive rear surface of the wafer 37 is attached to an adhesive sawing tape 41. The flip chip contacts 13 are attached to the chip contact areas 6 on the active surface of the semiconductor chips 2 at the wafer stage .

Figure 5 shows the partial singulation of the semiconductor chips 2 from the wafer 37 by a first saw blade 42. The first saw blade 42 produces a cut 43 with essentially straight sides or walls . The saw blade 42 partially separates adjacent the semiconductor chips 2 along the approximate lateral centre of the singulation trench 39. The first partial cut 43 has a width BIT and a depth BIa . The dimensions of the cuts are ex-

plained later in more detail with reference to Figure 8 and Table 1.

In this embodiment of the invention, the trench formed by the first cut 43 has a base which lies in a plane essentially perpendicular to the side walls of the cut 43. The outward lying portions of this base will form the essentially horizontal tread of the step 8. The tread of the step 8 lies in an essentially parallel plane with respect to the active surface 4 and passive surface 5.

Figure 6 shows the singulation of the semiconductor chips 2 from the wafer 37 in a second step . A second saw blade 44 , which also produces a cut with essentially straight side faces , is used to form a cut with a width of B2T . The width of the second cut 45 of the second saw blade 44 being laterally smaller than the width of the first cut 43 of the first saw blade 42. The second saw blade 44 singulates the semiconductor chips 2 in approximately the lateral centre of the singulation trench 39 along the line denoted by the numeral 40.

As can be seen more clearly in figure 7 , this method produces a semiconductor chip 2 in which the side faces 7 have a step 8. The width of the step 8 is denoted by a and the height of the step is denoted by b . For example, for a singulation trench with a width of around 90 μm, the first blade width is 40 μm to 45 μm and the second blade width 20 μm to 25 μm. This produces a step with a step or tread width of 10 μm to 12.5 μm. The depth b depends on the thickness of the wafer and lies typically in the range 10 μm to 150 μm.

Figure 8 shows a more detailed view of the cuts made in the wafer 37 by the first saw blade 42 and second saw blade 44. Examples of the width and depth of the cuts for wafers of different thickness are given in Table 1. In Table 1, the follow- ing initials stand for the following dimensions . WT is Wafer Thickness , SSW is Saw Street Width, BIT is Blade 1 thickness , BlE is Blade 1 Exposure, BlRE is Blade 1 Remaining Exposure, BIa is Blade 1 Cut Depth, B2T is Blade 2 thickness , B2E is Blade 2 Exposure, B2RE is Blade 2 Remaining Exposure, BH is Bump Height, T is wafer sawing exposure tolerance, TCD is Tape Cut Depth . All the values are given in microns or micrometres .

As can be seen from Table 1, the following relationships apply. BlRE = BlE - BIa - BH -T and B2RE = B2E-WT - TCD- BH -T . Therefore, for a wafer of thickness 300 μm, BlRE = 1200 - 150 -90-50 = 910 μm and B2RE = 750 - 300 - 50 - 90 - 50 = 260 μm.

Figure 9 illustrates a second method according to the invention of separating or singulating in the semiconductor chips 2 from the wafer 37. In the second method, a profile saw is used which has a saw blade 46 with a V-shaped cross-section . The saw blade 46 produces a cut 47 with a V-shaped cross-section in the approximate lateral centre of the saw streets 39 denoted by the dashed line 40. Each adj acent semiconductor chip 2 is formed with a side face 28 inclined at an angle c° to the active surface 4. As the cut is made from and into the active surface of the wafer, the active surface 4 of each semiconductor chip 2 is , therefore, laterally smaller than the passive surface 5. In the second method, the chips 2 are separated from the wafer 37 by the use of a single saw cut .

Figures 10 and 11 show a third method of singulating the semiconductor chips 2 from the wafer 37 according to the invention .

Figure 10 shows the partial singulation of the semiconductor chips two from the wafer 37 using a fourth saw blade 48. The saw blade 48 is also a profile saw blade having an approximately V-cross-section . In the third method of the invention a cut formed a trench of channel with a V-shaped cross-section 49 is formed in approximately the centre of the singulation trench 39 in the active surface of the wafer 37.

In the second sawing step of the third singulation method, a saw blade 44 which produces a cut with approximately straight sides is used to a separate the semiconductor chips 2 from the wafer 37. The second saw blade 44 is aligned to produce a cut in the approximate centre of the singulation trenches 39 , at the lateral centre or apex of the V-shaped channel 46.

The third method according to the invention produces a semiconductor chip 2 with side faces 50 in which a portion 51 is inclined at an angle to the active surface 4 of the semiconductor chip 2. The remaining portion 52 of the side wall 50 , which was formed by the second cut, is therefore approximately perpendicular to the passive rear surface of the semiconductor chip 2.

After all of the semiconductor chips have been separated or singulated from the wafer 37 by any one of the method accord- ing to the invention, the semiconductor chips 2 are used in the assembly of semiconductor packages using known assembly methods .

In a first method, not illustrated in the diagrams , a semiconductor chip 2 is mounted by a flip-chip technique on a substrate 3. The solder of the flip-chip contacts 13 is reflowed to mechanically attach and electrically connect the chip 2 to the substrate 3. The cavity 19 formed between the active surface 4 of the chip 2 and the upper surface of the substrate 3 is essentially filled by underfill material 20. Depending on the material used for the underfill material, an appropriate curing treatment is given . The chip 2 and upper surface of the substrate 3 are then encapsulated by mold material . A known molding process is used.

For a stacked semiconductor package 23, a second semiconductor chip 26 is mounted on the passive surface 5 of the first semiconductor chip by adhesive 32. The second chip 26 is then electrically connected to the substrate by bond wires 33.

Alternatively, the second semiconductor chip 26 is mounted on a substrate 36 by its passive rear surface and electrically connected to the substrate by bond wires 33. The semiconductor chip 2 is then mounted by a flip-chip technique on the active surface 29 of the second semiconductor chip 26. The cavity 19 formed between the active surfaces 4 and 29 of the two chips 2 , 26 is then filled by underfill material 20.

The stacked semiconductor chips 2, 26 and their electrical connections 33 are then encapsulated in mold material 34.

Reference numbers

1 first semiconductor package 28 inclined side face

2 semiconductor chip 29 active surface

3 first rewiring substrate 30 passive surface

4 active surface 31 chip contact pad

5 passive surface 32 adhesive

6 chip contact pad 33 bond wire

7 side face 34 mold material

8 step 35 third semiconductor package

9 cutout 36 third substrate

10 projecting portion 37 wafer

11 upper surface 38 device position

12 first inner contact area 39 singulation trench

13 solder ball 40 centre of singulation

14 conductor track trench

15 via 41 sawing tape

16 outer contact area 42 first saw blade

17 solder ball 43 first cut

18 Solder resist 44 second saw blade

19 cavity 45 second cut

20 underfill material 46 third saw blade

21 dispensing needle 47 V-shaped cut

22 angled tip 48 fourth saw blade

23 second semiconductor pack49 V-shaped notch age 50 side face

24 crack stop 51 inclined portion of side

25 second inner contact area wall

26 second semiconductor chip 52 straight portion of side

27 semiconductor chip wall

53 third semiconductor chip

54 second substrate