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Patent Searching and Data


Title:
FLIP-FLOP, SHIFT REGISTER, DISPLAY DRIVE CIRCUIT, DISPLAY APPARATUS, AND DISPLAY PANEL
Document Type and Number:
WIPO Patent Application WO/2010/146756
Kind Code:
A1
Abstract:
Disclosed is a flip-flop provided with a first CMOS circuit in which the gate terminals and drain terminals of a P channel first transistor and an N channel second transistor are connected, a second CMOS circuit in which the gate terminals and drain terminals of a P channel third transistor and an N channel fourth transistor are connected, a plurality of input terminals, and first and second output terminals, wherein the gate side of the first CMOS circuit and the drain side of the second CMOS circuit are connected to the first output terminal, the gate side of the second CMOS circuit and the drain side of the first CMOS circuit are connected to the second output terminal, and the first to fourth transistors each include an input transistor the source terminal of which is connected to one of the plurality of input terminals. According to this configuration, the flip-flop can be made smaller.

Inventors:
MURAKAMI, Yuhichiroh (())
村上祐一郎 (())
FURUTA, Shige (())
古田成 (())
SASAKI, Yasushi (())
Application Number:
JP2010/002196
Publication Date:
December 23, 2010
Filing Date:
March 26, 2010
Export Citation:
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Assignee:
SHARP KABUSHIKI KAISHA (22-22, Nagaike-cho Abeno-ku, Osaka-sh, Osaka 22, 〒5458522, JP)
シャープ株式会社 (〒22 大阪府大阪市阿倍野区長池町22番22号 Osaka, 〒5458522, JP)
MURAKAMI, Yuhichiroh (())
村上祐一郎 (())
FURUTA, Shige (())
古田成 (())
International Classes:
H03K3/356; G02F1/133; G09G3/20; G11C19/00; G11C19/28; H03K17/00; H03K17/687; H03K23/00; G09G3/36
Foreign References:
JPS6160008A
JPH02266609A
Other References:
See also references of EP 2445108A4
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (Daiwa Minamimorimachi Building, 2-6 Tenjinbashi 2-chome Kita, Kita-ku, Osaka-sh, Osaka 41, 〒5300041, JP)
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