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Title:
FLIP FLOP, SHIFT REGISTER, DRIVER CIRCUIT, AND DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2012/029876
Kind Code:
A1
Abstract:
This flip flop is provided with: an input and an output terminal; a first and a second control signal terminal; a first output unit which includes a bootstrap capacitor and is connected to the first control signal terminal and the output terminal; a second output unit which is connected to the first output unit and the output terminal; a first input unit which is connected to the input terminal and which charges the bootstrap capacitor; a discharge unit which discharges the bootstrap capacitor; a second input unit which is connected to the input terminal and is connected to the second output unit; a re-set unit which is connected to the second control signal terminal and which controls the discharge unit and the second output unit; a first initiation unit which controls the first output unit; a second initiation unit which controls the first input unit; and a third initiation unit which controls the discharge unit and the second output unit. Due to this configuration, it is possible to have a shift register which is capable of completely ON operation regardless of a clock signal.

Inventors:
SASAKI YASUSHI
MURAKAMI YUHICHIROH
YAMAMOTO ETSUO
Application Number:
PCT/JP2011/069827
Publication Date:
March 08, 2012
Filing Date:
August 31, 2011
Export Citation:
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Assignee:
SHARP KK (JP)
SASAKI YASUSHI
MURAKAMI YUHICHIROH
YAMAMOTO ETSUO
International Classes:
H03K3/356; G02F1/133; G09G3/20; G09G3/36; G11C19/00; G11C19/28; H03K17/687; H03K19/0175
Domestic Patent References:
WO2009034749A12009-03-19
Foreign References:
JP2001273785A2001-10-05
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (JP)
Patent business corporation Hara [Kenzo] international patent firm (JP)
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Claims: