BACKGROUND

[0001] A printing device may eject a print substance on print media. For example, a printing device may deposit a printing fluid, such as ink, on the print media. In some examples, the printing device may include a fluidic die to deposit the print substance on the print media. In other examples, a printing device may be used for bio-medical applications, such as to perform tests on fluids, or additive manufacturing, such as 3D printing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various examples will be described below by referring to the following figures.

[0003] FIG. 1 illustrates an example of a printing device having a number of components;

[0004] FIG. 2 is an example of clock signal generation based on actuation data;

[0005] FIG. 3 is a block diagram illustrating an example of a fluidic die; and

[0006] FIG. 4 is a flow diagram illustrating an example method for generating a clock signal for a fluidic die.

[0007] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and/or implementations in accordance with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

DETAILED DESCRIPTION

[0008] Printing devices may deposit a print substance (referred to herein as printing fluid) on print media. In some examples, the printing device may include a fluid ejection device that deposits printing fluid. A printing device may include a fluidic die (also referred to as a printhead die) that includes fluidic actuators (also referred to as nozzles) to transport printing fluid.

[0009] In some examples, the print substance may include printing agents or colorants. The printing device may apply the print substance to a substrate. A substrate is a superset of print media, such as plain paper, and can include any suitable object or materials to which a print substance from a printing device is applied including materials, such as powdered build materials, for forming three- dimensional articles. In addition, in some examples, a printing device may print on various media such as inanimate objects, skin, books, wood, plastic, metal, concrete, wallpaper, or other materials. Print substances, including printing agents and colorants, can include liquid inks, or other suitable marking material that may or may not be mixed with fusing agents, detailing agents, or other materials and can be applied to the substrate.

[0010] In other examples, the printing device may be used in life-science applications (e.g., lab-on-chip fluidic designs), bio-printing, printed manufacturing features and sensors for additive manufacturing applications. These applications may use a print substance other than ink or toner.

[0011] In some cases, a fluidic die may include a number of bond pads to receive signal from other components of the printing device. However, bond pad space may be at a premium in designs for fluidic dies. Elimination of even one or two bond pads can help shrink die size, provide die space for other circuitry, reduce materials cost or improve manufacturing yield. It should be noted that unbonded pads are not constrained to the same location/size as bonded pads and may be included in the design of a fluidic die without the same silicon costs as bonded pads.

[0012] Furthermore, a free-running clock with its interconnect between the printing device and the fluidic die is a source of electrical noise (referred to as electromagnetic (EM) emissions). In some approaches, the effects of EM emissions from a free-running clock may be mitigated through costly and complex solutions. For example, EM emissions may be addressed by shielding, expensive cabling, or spectrum spreading. Additionally, EM emissions effects may not be fully identified until late in the design cycle of a printing device when a full representative product is available for testing. Eliminating a free-running clock reduces EM emissions.

[0013] As an alternative to an external free-running clock signal, an embedded clock signal for the fluidic die is described. An on-die phase-locked loop (PLL) circuit may be synchronized by the actuation data received at the fluidic die. As used herein, actuation data refers to data that is transmitted to the fluidic die for the fluidic actuators. The actuation data may also be referred to as print data. In some examples, the actuation data may apply to a single actuation instance where a number of fluidic actuators are activated. The actuation data differs from other configuration data that is received at the fluidic die. Configuration data may be persistent data written to configuration registers on the fluidic die.

[0014] By generating the clock signal on the fluidic die based on the actuation data, a dedicated clock signal pad (or a pair of pads if the clock signal is a differential signal) may be eliminated. It should be noted that a non- bondable clock pad may be retained for testing purposes while maintaining the space savings associated with the removal of the external clock signal pad. Embedding a clock signal in the actuation data path may reduce costs by eliminating a dedicated clock signal pad between the printing device (e.g., print controller) and fluidic die. Eliminating the external clock may also increase electromagnetic (EM) compatibility, may reduce EM emissions and electrical noise, and may enhance power and thermal performance of the printing device. Circuit topologies and protocols to generate an embedded clock signal, reduce EM emissions, and provide data integrity are described herein.

[0015] FIG. 1 illustrates an example of a printing device 102 having a number of components. The printing device 102 may include a print controller 104 and a fluidic die 106. Examples of printing devices 102 include printers, copiers, fax machines, multifunction devices including additional scanning, copying, and finishing functions, all-in-one devices, pad printers to print images on three dimensional objects, and three-dimensional printers (additive manufacturing devices).

[0016] Printing device 102 refers to a combination of hardware through which fluids and/or electric signals may propagate and instructions to implement printing operations. The electric signals may include actuation data 110. The fluids may include marking fluids, such as inks, and biological fluids, such as blood, by way of example. In one example case, the fluidic die 106 may be capable of delivering printing fluids to fluidic actuators for ejection onto a substrate or build material. In some examples, the printing device 102 may include a number of fluidic dies 106, which may operate in concert to form objects, text, and/or images on a target material.

[0017] In another implementation, the printing device 102 may be used for diagnostic tests on biological fluids. For instance, the fluidic die 106 may comprise a diagnostic test device into which fluids, such as blood, may be introduced for testing. In this case, the fluidic die 106 may refer to a replaceable component, such as after each test, to enable successive tests with reduced amounts of waste and/or cost.

[0018] In yet another implementation, the printing device 102 may be a 3D printing device. In this case, the fluidic die 106 may refer to a component to be used in a 3D printing device. For example, the fluidic die 106 may deliver fusing and/or detailing agents for forming 3D objects.

[0019] As used herein, the fluidic die 106 refers to a die in the context of integrated circuits, which includes a number of structural features and components to form functional circuitry and fluidic elements. For instance, in one implementation, a substrate such as silicon may be used as a base upon which structural features, such as integrated circuit elements (e.g., resistors, capacitors, transistors, etc.) may be formed through processes such as photolithographic processes and other like build-up or machining processes. The fluidic die 106 includes a number of fluidic channels and wire traces, which are used for the propagation of fluids and electric signals, respectively. The fluidic channels and wire traces may also be formed through processes such as photolithographic process and other like build-up or machining processes.

[0020] The fluidic die 106 may include a phase-locked loop (PLL) circuit 112 that generates a clock signal 114. The PLL circuit 112 may be synchronized by actuation data 110 received on an actuation data channel 108 to generate the clock signal 114. For example, the PLL circuit 112 may perform clock recovery using transitions in the actuation data 110. Therefore, the clock signal 114 generated by the PLL circuit 112 synchronizes to the actuation data 110 without an external clock signal being sent to the fluidic die 106.

[0021] The actuation data 110 may be data that is transmitted to the fluidic die 106 for use in actuating fluidic actuators (not shown). The actuation data 110 may also be referred to as print data. In some examples, the actuation data 110 may apply to a single actuation instance where a number of fluidic actuators are activated.

[0022] In some examples, the PLL circuit 112 may synchronize its phase on the rising edge of the actuation data 110, thereby producing the clock signal 114 with the phase set correctly. The PLL circuit 112 may free run between rising edges of actuation data 110. In other examples, synchronization of the PLL circuit 112 may be on the falling edge of the actuation data 110, or both edges of the actuation data 110.

[0023] As used herein, an “edge” refers to a transition in the state of the actuation data 110. For example, a rising edge occurs when the actuation data 110 goes from low (e.g., “OFF,” low voltage, bit value “0”, etc.) to high (e.g., “ON”, high voltage, bit value Ί”, etc.). Conversely, a falling edge occurs when the actuation data 110 goes from high to low. An example of clock signal generation based on the actuation data 110 is described in FIG. 2. [0024] In some examples, the PLL circuit 112 may include a clock frequency capture range that limits the frequency of the clock signal 114 to frequencies within the clock frequency capture range. The use of the clock frequency capture range may ensure that the PLL circuit 112 does not lock on to a frequency that is double or half the frequency of the actuation data 110, for example.

[0025] The actuation data 110 may be received at the fluidic die 106 on an actuation data channel 108. In some examples, the actuation data channel 108 may be a communication link to communicate the actuation data 110 from a print controller 104 to the fluidic die 106. In some examples, the actuation data channel 108 may be implemented as a single conductive component (e.g., metallic, metalloid, conductive non-metals, etc.) or a number of electrically conductive components (e.g., as a bus) through which the actuation data 110 is transmitted.

[0026] The print controller 104 may include a combination of hardware and executable instructions, such as instructions to eject print fluids. For instance, the print controller 104 may include a number of integrated circuits (ICs) that may be accessed by firmware (FW) and/or software (SW) in order to execute instructions. Examples of the print controller 104 may include, for instance, field- programmable gate arrays (FPGAs), general purpose processing units, application-specific integrated circuits (ASICs), and the like, without limitation. [0027] In some examples, the actuation data channel 108 may be a high speed channel for communicating actuation data 110 at a high rate of speed. This may be contrasted with a configuration channel (not shown) for communicating configuration data (e.g., firing energy values, temperature control values, setpoints, sensor settings) to the fluidic die 106. The configuration channel may communicate data at a lower rate of speed than the actuation data channel 108.

[0028] The PLL circuit 112 may generate a free running clock, but its frequency continues to be synchronized (i.e., adjusted) with each transition of the actuation data 110. In an example, each positive-going edge that occurs in the data stream on the actuation data channel 108 may cause the frequency of the PLL circuit 112 to be modulated so that its output (the regenerated clock signal 114) is aligned properly with the data stream. If the data transition happens too far ahead of the transition of the PLL circuit 112, then the frequency of the generated clock signal 114 will be adjusted up. Likewise, if the data transition happens too far after the transition of the PLL circuit 112, then the frequency of the generated clock signal 114 will be adjusted down.

[0029] Using an embedded clock signal 114 for the actuation data 110 where the on-die PLL circuit 112 is synchronized by the actuation data 110 allows for reductions in EM emissions and electrical noise. The embedded clock signal 114 may also provide for signal integrity monitoring. Circuit topologies and data protocols for data integrity and EM emission reduction are described herein. [0030] The print controller 104 may send the actuation data 110 on the actuation data channel 108 with a protocol to assist the PLL circuit 112 in synchronizing the clock signal 114 to the actuation data 110. The protocol may ensure that the actuation data 110 includes a number of bit state transitions to enable the PLL circuit to synchronize the generated clock signal with the actuation data. For example, the actuation data 110 may be encoded using encoding (e.g., Manchester encoding, or other techniques) so that transitions of a maximum period are guaranteed. This actuation data encoding may ensure that the PLL circuit 112 does not get out of sync with the data stream on the actuation data channel 108.

[0031] In other examples, the protocol may include inverting bit states of the actuation data 110 that includes a threshold number of static-data packets. As used herein, “static-data packets” are data packets that are predominately one value (e.g., a high percentage of Ts or 0’s). This may occur in high density or low density prints.

[0032] In some cases, PLL-embedded clock protocols may rely upon a certain number of switching states in the data stream. If the values in the actuation data 110 are static (e.g., a high percentage of Ts or 0’s) for a period of time, then the PLL circuit 112 may not be able to synchronize with the actuation data 110. In other words, if a packet of actuation data 110 is comprised of very high- or low-duty cycle data (e.g., a high percentage of Ts or 0’s), then the number of transitions in data used to synchronize the clock signal 114 may be prohibitively infrequent. The threshold value may be a certain percentage of bits or a number of bits in the actuation data 110 that are the same value (e.g., “1” or “0”).

[0033] To address the scenario of static-data packets, the print controller 104 may assess the packet(s) before sending the actuation data 110. The print controller 104 may use a protocol for the actuation data 110 where the protocol alternates between a number of bits of the actuation data in a standard bit state and a number of bits of the actuation data in an inverted bit state. As used herein, in the standard bit state, a “1” means a “1”, and a “0” means a “0.” In the inverted bit state, a “1” means a “0”, and a “0” means a “1.” The fluidic die 106 may be informed of the encoding used for the inverted bit states.

[0034] In another approach, the protocol may include inversion banks. In this approach, for every N bits of a packet, the protocol will alternate between the standard bit state and the inverted bit state.

[0035] The print controller 104 may select a protocol for encoding the inverted bit state and may convey to the protocol to the fluidic die 106 before sending the encoded actuation data 110. This protocol will ensure that, for the specific actuation data 110 being sent, a number of transitions in the incoming actuation data channel 108 are present so that the clock signal 114 recovered by the PLL circuit 112 is properly synchronized.

[0036] In some examples, the fluidic die 106 may include a circuit 116 to assess or validate the integrity of the received actuation data 110 synchronized with the generated clock signal 114. In PLL-based recovered-clock systems, the system may ensure that the clock signal 114 is being properly synchronized. In some examples, the data integrity circuit 116 may monitor the actuation data 110 to ensure that the actuation data 110 includes a threshold number of synchronization edges for the PLL circuit 112. For example, the data integrity circuit 116 may determine whether the synchronization edges are sent at a minimum frequency. The data integrity circuit 116 may generate a fault in response to determining that the actuation data 110 does not include synchronization edges sent at the minimum frequency. The fault may be communicated back to the print controller 104, which may respond by retransmitting the actuation data 110 with a threshold number of synchronization edges for the PLL circuit 112.

[0037] In another approach, the data integrity circuit 116 may count a number of clock edges in the clock signal 114 during actuation data transmission. The data integrity circuit 116 may compare the counted clock edges to an expected number of clock edges to ensure that the counted number matches an expected number of clock edges. If the counted clock edges do not match the expected number, then the data integrity circuit 116 may send a fault to the print controller 104. An example of data integrity circuits to validate the integrity of the received actuation data 110 is described in FIG. 3.

[0038] In some examples, the PLL circuit 112 may generate the clock signal 114 while the actuation data channel 108 is idle to reduce electromagnetic emissions of the actuation data channel 108. Free-running clock print systems emit EM noise even when there is no need for a clock or no need for a precise clock. Transmissions on the actuation data channel 108 may cease while the actuation data channel 108 is idle. Stopping transmission on the actuation data channel 108 between packets may result in EM emission reductions. For example, in between actuation data packets, the actuation data channel 108 may be left idle to reduce (or eliminate) EM emissions from the actuation data channel 108 during those times.

[0039] With an idle actuation data channel 108, the PLL circuit 112 will be operating in an open-loop clock recovery mode. Between data packets and activating fluidic actuators, systems on the fluidic die 106 that use the clock signal 114 may not be sensitive to a precise clock. Therefore, the PLL circuit 112 may be allowed to operate open loop. For example, systems on the fluidic die 106 that use a free-running clock (e.g., autonomous thermal control) may not have the same precision in clock timing as data packet parsing blocks. In this case, the PLL circuit 112 can continue to generate an open-loop clock signal 114 without feedback from the actuation data 110 while the actuation data channel 108 is idle. In some examples, the PLL circuit 112 may be implemented such that the open-loop clock signal 114 stays within defined frequency limits while in open-loop clock recovery mode.

[0040] The use of idle times to reduce emissions produced by the actuation data channel 108 results in the recovered clock not being synchronized. In some examples, if the actuation data channel 108 is idle and a packet transmission in imminent, the packet for the actuation data 110 may be preceded by a synchronization header (also referred to as a “wind-up header”). A synchronization header preceding data packets allows for the recovered clock signal 114 to be resynchronized before data packets are sent. In an approach, the synchronization header may include a number of edges on the actuation data channel 108 to re-synchronize the PLL circuit 112 before the first bit of the data packet is received by the fluidic die 106. Therefore, the fluidic die 106 may receive the synchronization header on the actuation data channel 108 before transmission of actuation data 110. The PLL circuit 112 may synchronize with the synchronization header before receiving the actuation data 110.

[0041] In some examples, the actuation data channel 108 may be used to send synchronization pulses to recover the clock signal 114, even if data packets are not being sent on the actuation data channel 108. With no free- running clock provided to the fluidic die 106, a configuration channel that relies on a clock based on the master clock of the printing device 102, cannot be synchronized. In this case, the actuation data channel 108 may be used to synchronize the PLL-generated clock signal 114 without sending actuation data 110. The fluidic die 106 may receive synchronization pulses on the actuation data channel 108 when actuation data 110 is not sent. The synchronization pulses may be changes in the voltage level (e.g., high or low) of the actuation data channel 108 that change with a frequency of the actuation data clock. The PLL circuit 112 may generate the clock signal 114 based on the synchronization pulses.

[0042] In some examples, the fluidic die 106 may include a configuration channel that is separate from the actuation data channel 108. The configuration channel may be a slower-speed, single-ended data channel for setting up configuration registers on the fluidic die 106. Communication on the configuration channel, while operating at a lower frequency than the actuation data channel 108, may be based on a divided down version of the clock signal 114.

[0043] For a PLL-based print system with an embedded clock, there will often be times where configuration operations may be executed, but actuation data 110 is not being sent. In these cases, the actuation data channel 108 may be activated sufficiently such that the clock signal 114 is properly recovered and synchronized for the configuration operation. Edges of the actuation data channel 108 may be manipulated such that the emission spectrum is spread out to below a maximum. Edges of the actuation data channel 108 may be manipulated such that a start bit sequence indicating the start of an actuation data packet is not recognized by the fluidic die 106.

[0044] FIG. 2 is an example of clock signal generation based on actuation data 210. The clock signal 214 may be generated by a PLL circuit of a fluidic die, as described in FIG. 1.

[0045] In this example, the actuation data 210 includes a packet 222 with eight bits 224. In other examples, packets 222 of actuation data 210 may include other numbers of bits 224. In this example, a bit 224 may be either a high value (e.g., a “1 ”) or a low value (e.g., a “0”).

[0046] In some cases, the actuation data 210 may include static data packets 222 that are predominately one value (e.g., a high percentage of Ts or 0’s). In this example, the actuation data 210 is a static series of 1 ’s.

[0047] As described above, PLL-embedded clock protocols may rely upon a certain number of switching states in the data stream. If the values in the actuation data 210 are static for a period of time, then the PLL circuit may not be able to synchronize with the actuation data 210. In this case, the clock signal 214 may drift from the frequency of the actuation data 210.

[0048] A protocol may be used to encode the actuation data 210 in a manner where transitions are introduced in encoded data 220 to provide the PLL circuit an opportunity to synchronize with the actuation data 210. The protocol alternates between a number of bits 224 of the actuation data 210 in a standard bit state 225 and a number of bits 224 of the actuation data 210 in an inverted bit state 226.

[0049] In this example, for bits 224 in the encoded data 220 in the standard bit state 225, “1” means a “1”, and a “0” means a “0.” For bits 224 in the encoded data 220 in the inverted bit state 226 a “1” means a “0”, and a “0” means a “1

[0050] The inversion of the bit states in the encoded data 220 provides synchronization edges 228, 229 for the PLL circuit to synchronize the clock signal 214. For example, the PLL circuit may synchronize to a falling synchronization edge 228, a rising synchronization edge 229, or both.

[0051] FIG. 3 is a block diagram illustrating an example of a fluidic die 306. In this example, the fluidic die 306 may include circuits to validate the integrity of received actuation data 310 that is synchronized with a clock signal 314 generated by a PLL circuit 312.

[0052] In this example, the fluidic die 306 may include a data pad 334 to receive actuation data 310. The data pad 334 may be coupled to an actuation data channel. The PLL circuit 312 may include a transition monitor 330 to monitor the actuation data 310 to ensure that the actuation data 310 includes a threshold number of synchronization edges for the PLL circuit 312. In some examples, the transition monitor 330 may count the number of synchronization edges included in the actuation data 310. The transition monitor 330 may determine whether the actuation data 310 includes a threshold number of synchronization edges within a certain period. For example, the transition monitor 330 may determine whether the synchronization edges are sent at a minimum frequency.

[0053] The transition monitor 330 may generate a fault in response to determining that the actuation data 310 does not include synchronization edges sent at the minimum frequency. Therefore, the transition monitor 330 may generate a fault if a prohibitively long time transpires between receipt of synchronization edges on the actuation data channel.

[0054] The fluidic die 306 may also include a data parser 332. The data parser 332 may receive the actuation data 310 and the recovered clock signal 314 to convert the serial input data stream to a parallel data stream of parsed actuation data 336 for the fluidic actuator control logic 338. The fluidic actuator control logic 338 may control the fluidic actuators in response to the actuation data 310.

[0055] The data parser 332 may count the number of received clock edges it receives during an actuation data packet transmission to ensure that the number is as expected. For example, if the PLL circuit 312 is not properly synchronizing the clock signal 314 and the clock period drifted on the high end, the number of recovered clock edges would diminish. Therefore, the data parser 332 may count the number of clock edges in the clock signal 314 during an actuation data transmission. The data parser 332 may compare the counted clock edges to an expected number of clock edges to ensure that the counted number matches an expected number of clock edges. If the counted clock edges do not match the expected number, then the data parser 332 may generate a fault.

[0056] FIG. 4 is a flow diagram illustrating an example method 400 for generating a clock signal 114 for a fluidic die 106. The method 400 may be implemented by a fluidic die 106.

[0057] The fluidic die 106 may generate 402 a clock signal 114 with a phase- locked loop (PLL) circuit 112 based on actuation data 110 received on an actuation data channel 108. For example, the PLL circuit 112 may recover the clock signal 114 from the actuation data 110. For example, the PLL circuit 112 may use synchronization edges within the actuation data 110 to synchronize the generated clock signal 114 to the actuation data 110. The fluidic die 106 may generate 402 the clock signal 114 without an external clock signal being sent to the fluidic die 106.

[0058] The fluidic die 106 may generate 404 the clock signal 114 with the PLL circuit 112 while the actuation data channel 108 is idle to reduce electromagnetic emissions of the actuation data channel 108. In some examples, transmissions on the actuation data channel 108 cease while the actuation data channel 108 is idle. In other examples, transmission of actuation data 110 ceases while the actuation data channel 108 is idle but synchronization pulses may occur. The PLL circuit 112 may generate an open-loop clock signal 114 without feedback while the actuation data channel 108 is idle. In this case, the clock signal 114 may lose synchronization with the actuation data 110. However, the PLL circuit 112 may be implemented to stay within defined frequency limits while in open-loop clock recovery.

[0059] In some examples, the fluidic die 106 may receive a synchronization header on the actuation data channel 108 before transmission of actuation data 110. For instance, if the actuation data channel 108 is idle and a packet transmission in imminent, the packet for the actuation data 110 may be preceded by a synchronization header. The PLL circuit 112 may be synchronized with the synchronization header before receiving actuation data 110.

[0060] In some examples, the fluidic die 106 may receive synchronization pulses on the actuation data channel 108 when actuation data 110 is not sent. The synchronization pulses may be changes in the voltage level (e.g., high or low) of the actuation data channel 108 that change with a frequency of the actuation data clock. However, in this case, actuation data 110 may not be sent on the actuation data channel 108. The PLL circuit 112 may generate the clock signal 114 based on the synchronization pulses.

[0061] It should be noted that while various examples of systems and methods are described herein, the disclosure should not be limited to the examples. Variations of the examples described herein may be implemented within the scope of the disclosure. For example, functions, aspects, or elements of the examples described herein may be omitted or combined.