Technical field

[0001] The present invention is related to electrical converters comprising a flying capacitor circuit. The present invention is particularly related to flying capacitor converters in which the voltage of the flying capacitor(s) is/are actively controlled.

Background art

[0002] Electric Vehicles (EVs) are preferably charged with a DC fastcharging station. To allow charging independent of the available charger infrastructure, in addition, EVs are also equipped with an On-Board Charger (OBC), which ideally allows to charge the battery both from the single-phase and three-phase AC grid. For a singlephase rectifier system operating at unity power factor, the grid input power p _ac is defined as: with the AC input voltage u _ac , the AC input current i _ac and the mains frequency f _ac . The above equation (1) shows that the grid input power contains a twice mains frequency 2f _ac input power pulsation. Hence, the converter system is required to comprise low frequency energy storage elements. In the most simple case, a large DC-link capacitor buffers the pulsating input power, where the required capacitance value Cdc depends on the eligible low-frequency peak-to-peak DC-link capacitor voltage ripple AU, the mains frequency f _ac and the system power given by the following equation:

Electrolytic capacitors are the preferred technology for the DC-link capacitors due to the high capacitance density and low cost, which comes at the cost of limited lifetime. Furthermore, the electrolytic DC-link capacitors of an OBC capture a substantial fraction of the converter volume. This is particularly critical for mobile applications as the available EV range might be reduced by bulky and heavy converter components, which also add cost to the overall system.

[0003] US 2011/0261591 describes an electrical converter for single-phase and three-phase operation, comprising a three-phase rectifier. One rectifier bridge leg is provided with a switch providing connection to a capacitor which together with an inductor provides a power pulsation buffer (PPB) in single-phase operation. However, such system requires additional power components and increased system complexity for operating the power pulsation buffer.

[0004] Akiyoshi Omomo, et al. Loss analysis of t-type NPC inverter with active power decoupling capability operated in discontinuous current mode, in Proc, of the IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA Asia), pages 1-4, 2019 describe a t-type single-phase converter (i.e., with a split DC-link capacitor) where the upper and lower DC-link capacitor voltages are cycled by using the redundant switching states in order to buffer the pulsating input power. The total DC-link voltage (given by the sum of upper and lower DC-link voltage) remains constant.

[0005] Flying capacitor (FC) multi-level bridge-legs are known. Regina

Ramos, et al. Control design of a single-phase inverter operating with multiple modulation strategies and variable switching frequency, IEEE Transactions on Power Electronics, 36(2):2407-2419, 2021 describe a single-phase FC converter where the FC acts as a power pulsation buffer. The complete single-phase grid power pulsation is covered completely by the FC by means of a complex, varying switching frequency control strategy utilizing the high-frequency inductor current. Up to 32 different control modes occur within one mains period. In contrast to a traditional FC converter, the FC average voltage value is not equal to half the DC-link voltage, but is located slightly below the DC-link voltage. One disadvantage of this converter is the extremely complicated control strategy, as well as the asymmetric semiconductor blocking voltage stresses.

Summary

[0006] It is an object of the present disclosure to provide an electrical converter capable of buffering the pulsating single-phase power, which implements a simpler control strategy. It is an object of the present disclosure to provide such an electrical converter which does not require additional power components, and which even allows to reduce the total capacitance in the electrical converter.

[0007] It is an object of the present disclosure to provide an electrical converter capable of buffering the pulsating single-phase power, which has a longer service life, reduced complexity and/or which is more economical.

[0008] It is therefore provided an electrical converter as set out in the appended claims. An electrical converter according to the present disclosure comprises a DC link, a control unit and a first flying capacitor circuit. The first flying capacitor circuit comprises at least one flying capacitor, a switch node, possibly connected to an inductor, a first switch pair and a second switch pair. The DC link comprises an upper DC node (positive DC rail) and a lower DC node (negative DC rail). The first flying capacitor circuit is advantageously configured as a bridge-leg. It comprises a first switch pair configured to provide a connection between the upper DC node and an upper terminal of the flying capacitor, and between the lower DC node and a lower terminal of the flying capacitor. The second switch pair is configured to provide a connection between the switch node and the upper and lower flying capacitor terminals. The control unit is configured to operate the first and the second switch pairs to convert power between the switch node and the DC link.

[0009] According to an aspect of the present disclosure, the control unit is implemented with an operating mode. In the operating mode, the control unit is configured to determine a (variable) voltage reference for the flying capacitor based on a power imbalance between the switch node and the DC link, advantageously based on an instantaneous or local (e.g. averaged over a switching frequency period) power imbalance between the switch node and the DC link. The control unit is configured to adjust the voltage of the flying capacitor based on the (variable) voltage reference. In particular, the control unit is configured to adjust the voltage reference for the flying capacitor at least once, preferably multiple times within one half of a mains period. By so doing, the (local averaged) power of the flying capacitor is controlled, and the flying capacitor can be effectively utilized as a power pulsation buffer.

[0010] Advantageously, the control unit is configured to operate the first and second switch pairs to change a state of the flying capacitor. These states can be a discharging state, in which the flying capacitor is discharged (a voltage across the flying capacitor is decreased), a charging state in which the flying capacitor is charged (a voltage across the flying capacitor is increased) and a state in which the flying capacitor is maintained at a constant voltage. Multiple state changes advantageously occur within a single switching frequency period. Advantageously, the control unit is configured to adjust a duration of the discharging state and/or the charging state, advantageously within a period, or even half a period, of a fundamental voltage waveform (as applied at the switch node). This is advantageously performed by adapting a duty cycle of the first and/or second switch pairs.

[0011] The present disclosure therefore provides a simple and straightforward flying capacitor power control scheme in which the redundant converter switching states are utilized to control the flying capacitor power flow. The electrical converter of the present disclosure allows to obviate the need for additional power components, hence making the electrical converter very attractive for cost sensitive applications.

[0012] According to an aspect, solely the low-frequency switch node current (inductor current) and the redundant FC bridge-leg switching states are utilized to buffer the pulsating single-phase power, enabling a simple control circuit realization. Aspects of the present disclosure allow to buffer at least part of the single-phase power pulsation.

[0013] Different possibilities to determine the voltage reference of the flying capacitor in the operating mode can be contemplated. In a first embodiment, the control unit is configured to adapt the voltage reference dynamically, e.g. to derive the voltage reference from a power balance calculation. In particular, the power balance calculation results in a voltage reference having a dynamics that follows a power pulsation at the AC side (e.g. at twice the fundamental AC voltage frequency) and/or the DC side. Advantageously, the voltage reference is adapted or varied with a fundamental frequency equal to the AC side or DC side power pulsation frequency (e.g. twice the fundamental AC voltage frequency). In a second embodiment, the control unit is configured to select the voltage reference out of at least an upper voltage reference and a lower voltage reference to control the power (flow) of the flying capacitor, in a bangbang type of control. This solution has the advantage of a very simple control strategy, thereby reducing complexity of the control unit. The upper voltage reference and the lower voltage reference can be predetermined (fixed) values, e.g. determined by design of the electrical converter. In particular, the control unit can comprise a memory storing the upper and lower voltage references, or use analog comparator circuits to derive the voltage references. Alternatively, the upper and/or lower voltage references can be determined dynamically. Advantageously, in the operating mode, the control unit is configured to control the power of the flying capacitor comprising determining a voltage reference for controlling a voltage of the flying capacitor by toggling between (at least) the upper voltage reference and the lower voltage reference, in particular based on a power pulsation at the AC side (e.g. at twice the fundamental AC voltage frequency) and/or the DC side. In a third embodiment, the control unit can be configured to select additional voltage reference values, e.g., between the upper and lower voltage reference. [0014] The voltage reference according to aspects of the present disclosure can be configured to vary in a wide range. Advantageously, the control unit can be configured to select/determine the voltage reference such that an average voltage of the flying capacitor is approximately close to a balanced voltage Vbaianced of the flying capacitor. The balanced voltage can be expressed as Vbaianced = Ude I (n-1) with Ude being the DC-link voltage and n the number of voltage levels of the flying capacitor circuit (i.e. n-2 flying capacitors).

[0015] Advantageously, a voltage error signal for a voltage of the flying capacitor is determined from the voltage reference. Advantageously, individual duty cycles for the first and second switch pairs are determined based on the voltage error signal.

[0016] According to a further aspect of the present disclosure, there is provided a battery charging system, or an electric motor drive system, incorporating the electrical converter as described herein.

[0017] A method of operating an electrical converter according to the present disclosure is provided herein.

Brief description of the figures

[0018] Aspects of the invention will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0019] Figure 1 represents a single-phase AC to DC converter;

[0020] Figure 2 represents a single-phase rectifier system with flying capacitor circuit, wherein the voltage waveforms resulting from conventional operation are shown as a function of time t;

[0021] Figure 3 represents a single-phase rectifier system with flying capacitor circuit, wherein the voltage waveforms resulting from an operating mode according to the present disclosure are shown as a function of time t;

[0022] Figure 4 represents pulse width modulation (PWM) carrier waveforms and duty cycles for the switch pairs of the flying capacitor circuit according to the present disclosure;

[0023] Figure 5A represents a block diagram of a control unit for operating the rectifier system of Fig. 3 wherein the flying capacitor voltage is actively controlled for utilizing the flying capacitor as a power pulsation buffer; Figure 5B represents the block diagram of Fig. 5A, in which feedforward compensation is added to the inductor current control block;

[0024] Figure 6 represents a four-level flying capacitor circuit formed of a single flying capacitor bridge-leg, which can be utilized in converters of the present disclosure;

[0025] Figure 7 represents an n-level flying capacitor circuit formed of a single flying capacitor bridge-leg, which can be utilized in converters of the present disclosure;

[0026] Figure 8A represents a three-phase AC to DC converter comprising a first converter stage with three three-level flying capacitor bridge-legs and a second converter stage comprising a pair of secondary DC/DC converters connected in Input- Series Output-Parallel; [0027] Figure 8B represents the converter of Fig. 8A connected to a singlephase grid, wherein two out of the three flying capacitor bridge-legs are operated and the secondary DC/DC converters are connected in Input-Parallel Output-Parallel;

[0028] Figure 9A represents simulation results of converter waveforms over one fundamental period of 20 ms for the converter of Fig. 2 under conventional operation - without active flying capacitor voltage control according to the present disclosure; the bottom graph represents the DC-link voltage with enlarged Y-axis to show the voltage ripple of twice the fundamental frequency;

[0029] Figure 9B represents simulation results of converter waveforms over one fundamental period of 20 ms for the converter of Fig. 3 utilizing the active flying capacitor voltage control scheme according to the present disclosure for power pulsation buffering in the flying capacitor; the bottom graph represents the DC-link voltage with enlarged Y-axis to show the voltage ripple;

[0030] Figure 10 represents a block diagram of a battery charging system comprising an electrical converter according to aspects of the present disclosure.

Detailed Description

[0031] Referring to Figure 1 , a single-phase AC to DC converter 10 can be configured for unidirectional or bidirectional power transfer, i.e. capable of operating as a rectifier, an inverter, or both. The converter 10 comprises an AC side 12 with AC nodes g and N and a DC-link 11 with DC nodes DC+ (positive DC rail) and DC- (negative DC rail). The DC-link 11 comprises a DC-link capacitor 111 connected between the DC nodes DC+ and DC-. The converter 10 is configured to convert electrical power between the AC side 12 and the DC-link 11. As described above, when the converter 10 is operated with unity power factor, be it in rectifier or inverter mode, the AC power will be pulsating with twice the mains frequency. In a rectifier system, the power pulsation typically appears at the DC-link as a twice-mains frequency voltage variation.

[0032] Referring to Figure 2, one embodiment of converter 10 for use as a single-phase rectifier, is arranged as a flying capacitor converter. The converter comprises a full-bridge rectifier 121 arranged at the AC side 12 and connected to the AC nodes g and N. Full-bridge rectifier 121 can be arranged as a diode bridge, as shown in the example of Fig. 2. The upper output node q of bridge rectifier 121 , connected to the cathode side of the diodes, is connected to a switch node s of a flying capacitor circuit 13 through an inductor L. The lower output node r of bridge rectifier 121 , connected to the anode side of the diodes, is (equipotentially) connected to the negative DC rail and node DC-. Bridge rectifier 121 can alternatively be provided with bidirectional switches (e.g. MOSFETs) instead of diodes. [0033] Flying capacitor circuit 13 is arranged as a flying capacitor bridge leg and comprises a flying capacitor (FC) CFC and two switch pairs Ti, T’i and T2, T’2. Each switch T1, T’1 and T2, T’2 can be formed of an actively operated semiconductor switch, particularly a metal oxide semiconductor field effect transistor (MOSFET) and a diode arranged in antiparallel with the MOSFET. The switches of the first switch pair T1, T’1 connect the positive and negative terminals of the FC to the positive and negative DC rail, respectively. The switches of the second switch pair T2, T’2 connect the respective positive and negative terminals of the FC to the switch node s. The switches of each of the first and second switch pairs are generally operated in a complementary manner, as is well-known in the art, i.e. when one switch is closed, the other one is open and vice versa.

[0034] In a conventional operation, the voltage of the FC CFC is controlled at a constant value by appropriate operation of the two switch pairs T1, T’1 and T2, T’2 (through pulse width modulation). This is also referred to as natural voltage balancing of the FC. In case of a three-level FC circuit as is the case for the FC circuit 13, the voltage of the FC is kept at half the DC-link voltage value. The bridge rectifier 121 generates a pulsating rectified AC voltage |u _ac | between nodes q and r. The rectified single-phase AC voltage is converted by the flying capacitor circuit 13 into a DC voltage Ude at the DC-link 11. A pulsation at twice the mains AC frequency shows up in the DC-link voltage Ude. The resulting waveforms are qualitatively shown in Fig. 2.

[0035] Referring now to Fig. 3, according to aspects of the present disclosure, the conventional FC power control scheme is replaced with a simple and straightforward FC power control scheme. This control scheme is based on the utilization of redundant switching states of the FC circuit switch pairs and allows to control the FC power flow, so that the flying capacitor can be effectively utilized as a power pulsation buffer. The power control scheme of the present disclosure advantageously does not require additional power components, hence reducing manufacturing costs.

[0036] Advantageously, the converter topology of Fig. 3 can be identical to the topology of Fig. 2, except for the control scheme of the switch pairs T1 , T’1 and T2, T’2. According to the present disclosure, the FC voltage UFC is controlled to fluctuate within each half mains period to create a power pulsation buffer. This FC voltage fluctuation is implemented so as to reduce the power pulsation on the DC-link resulting in a lower DC-link voltage variation, as shown qualitatively in the voltage waveforms of Fig. 3. Reducing the power pulsation on the DC-link is especially beneficial as the expected lifetime of an electrolytic capacitor depends both on temperature and current stress and therefore the lifetime can be extended by employing operating modes of the present disclosure. Alternatively, the DC-link capacitor 111 can be decreased while maintaining a constant DC-link voltage fluctuation. It will be convenient to note that increasing the allowed FC voltage variation comes at a cost of only a higher blocking voltage requirements for the semiconductor switches, still obtaining a more economical converter. It is alternatively possible to combine both design options.

[0037] Referring to Fig. 4, a control scheme of the present disclosure allows to actively control the voltage of the flying capacitor CFC SO as to utilize the FC as a power pulsation buffer. For the case of a three-level FC circuit 13, two 180° phase- shifted Pulse Width Modulation (PWM) carriers can and can are generated, similar to the case of natural voltage balancing of the FC. More in general, for a n-level FC bridgeleg, n-1 triangular carrier waveforms which are phase-shifted by 3607(n-7) are generated. Instead of operating both switch pairs Ti, T’i and T2, T’2 with a same duty cycle d, individual duty cycles di and d2 are defined for the switch pairs T1, T’1 and T2, T’2 respectively. With these individual duty cycles for the two switch pairs, it becomes possible to change the (relative) duration of charging and/or discharging states of the flying capacitor within a switching period, and hence to adjust the FC voltage.

[0038] Advantageously, the duty cycles di and d2 are derived from the duty cycle d and a correction duty cycle d _cor via the relationship:

The duty cycle d can be determined by a control scheme for the inductor current i _ac as will be described. This advantageously allows to utilize the two redundant switching states of the FC bridge-leg to charge or discharge the FC with the low-frequency inductor current i _ac .

[0039] The net charge balance of the flying capacitor within one switching period T _s = l/f _s is defined as:

^QFC d _coriac T _s . (4)

From equation (4) it results that during the AC current zero crossing, no reference tracking can be enforced and to assure valid duty cycles di, d2 e [0; 1], the correction duty cycle d _cor has to be limited if d is close to zero or unity.

[0040] The FC power flow pre averaged over one switching period is defined by:

PFC d _coriac u _FC , (5)

The FC power flow is utilized to redirect the pulsating single-phase grid input power p _ac to the FC and thereby reduce the power pulsation on the DC-link. In theory, an FC power controller can be supplied with a reference equal to the difference between the input p _ac and the constant output (DC) power reference P _ou t. However, as described in relation to Eq. (4), the FC power flow cannot be fully regulated within a mains period. According to the present disclosure, therefore, the instantaneous input-output power discrepancy is overcompensated, at least in a few intervals.

[0041] Referring to Figs. 5A-B, a control unit 14 comprises at least one operating mode configured to determine duty cycles di and d2 for operating the flying capacitor circuit switch pairs Ti, T’i and T2, T’2 through PWM to actively control the flying capacitor voltage, and hence, as seen from Eq. (5), the power flow of the flying capacitor. The schemes shown in Figs. 5A-B apply to rectifier mode operation, although the scheme can readily be adapted for inverter mode operation. Control unit 14 comprises a FC power control block 141 configured to determine the correction duty cycle d _cor . Control unit 14 further comprises a control block 140 configured to determine the duty cycle d.

[0042] Control block 140 can be implemented as is known in the art of power factor correction (PFC) rectifier control to determine a duty cycle d. Advantageously, control block 140 comprises a cascaded arrangement of a DC voltage control block 142 and an inductor current control block 143. DC voltage control block 142 is configured to determine as an output, a reference value i* _ac for the inductor current i _ac , which is supplied as input to the inductor current control block 143, which in turn is configured to determine the duty cycle d as an output.

[0043] DC voltage control block 142 has a first input which is supplied with a voltage reference value U*d _C for the DC-link voltage Ude and a second input which is supplied with a measured (actual) DC-link voltage Ude. DC voltage control block 142 is configured to determine an error signal for the DC-link voltage. Advantageously, a DC- link capacitor current reference i*cdc is determined from the error signal, particularly through proportional and/or integral control. A third input of DC voltage control block 142 is supplied with a measured DC output current id _C . DC voltage control block 142 is configured to determine the inductor current reference i* _ac for the current in inductor L based on the error signal and the third input. One possible implementation is shown in Fig. 5A, where an input conductance reference G* is determined by dividing an instantaneous AC input power reference P* calculated as (i*cdc + ide) Ude with 0.5(7^ . The inductor current reference i* _ac can be obtained by multiplying G* with the rectified mains single-phase voltage |u _ac |.

[0044] Inductor current control block 143 hence comprises a first input supplied with the inductor current reference i* _ac and a second input supplied with a measured or instantaneous inductor current i _ac . An inductor current error signal is determined from the first and second inputs. Advantageously, a voltage reference U*L for inductor L is determined from the inductor current error signal, such as through proportional and/or integral control. An AC voltage error signal is determined by subtracting U*L from the rectified mains voltage |u _ac | . The duty cycle d can be determined by dividing the AC voltage error signal with the DC-link voltage Ude.

[0045] The FC power control block 141 comprises an FC voltage reference control block 144 configured to determine a voltage reference U*FC of the flying capacitor. According to an aspect of the present disclosure, the FC voltage reference control block 144 is implemented with an upper FC voltage reference upc.max and a lower FC voltage reference upc.min for the flying capacitor CFC. If the FC circuit 13 comprises more than one FC, each flying capacitor can have their proper upper and lower voltage references. The upper and lower voltage references UFc.max and UFc.min can be fixed, predetermined values implemented in the control unit 14, e.g. stored in dedicated memory. Alternatively, the upper and lower voltage references upc.max and UFc.min can be variable, e.g. based on the DC-link voltage Ude or the output power Pd _C . The upper and lower voltage references can be selected within minimum and maximum tolerable FC voltage values, wherein UFc.min > 0 V and upc.max < Ude. Allowing a larger FC voltage variation, e.g. between the upper and lower voltage references UFc.max and UFc.min to buffer the pulsating input power, can require semiconductor switches with elevated voltage rating compared to operation with constant FC voltages. In addition, the upper and lower voltage references UFc.max and UFc.min can be adjusted when the converter operates at a power that deviates from nominal power, e.g. by scaling based on the ratio between the actual power and the nominal power.

[0046] FC voltage reference control block 144 is configured to select the voltage reference U*FC from the upper and lower voltage reference values [ ^u Fc,min> ^u Fc,max] which advantageously form a binary set of reference values from which the FC voltage reference U*FC is selected. To select which one of the upper and lower voltage reference is used as instantaneous voltage reference U*FC, account is taken of the instantaneous power imbalance between the AC (input) power p _ac and the DC (output) power P _ou t. The instantaneous power imbalance is compared with a threshold power Pth. In particular, when the instantaneous power imbalance is higher than or equal to the threshold power Pth, the upper voltage reference UFc.max is selected as U*FC. In the other case, the lower voltage reference UFc.min is selected as U*FC. By appropriately selecting the threshold power Pth, the average FC voltage can be controlled to a desired value, e.g. to half the DC-link voltage value for a three-level FC circuit such as the FC circuit 13 shown in Fig. 3. The FC voltage reference control block 144 can be configured to adjust the threshold power Pth, e.g. dynamically. In some examples, the threshold power Pth is determined dynamically such that the average value of the flying capacitor voltage UFC is regulated to the balanced voltage of the flying capacitor, e.g. U*d _C 1 2 for the three-level flying capacitor circuit 13. This can be obtained by integral or proportional integral control of P _t h based on an error of UFC, e.g. through an l-controller or Pl-controller. [0047] Due to the occurring power pulsation on the AC side and/or the DC side of the converter 10, U*FC will alternate between UFc.max and UFc.min twice per period of the mains (AC) voltage. In one alternative implementation, the control scheme of Fig. 5A is utilized during selected intervals of a mains voltage period, while in other intervals of the mains voltage period, a duty cycle d is utilized for operating the switch pairs Ti , T’i and T2, T’2, e.g. as determined by control block 140. Yet alternatively, it is possible to determine U*FC as a scaled value (e.g. proportional to) of the instantaneous power imbalance p _ac - Pout.

[0048] Based on the selected/determined FC voltage reference U*FC, FC power control block 141 is configured to determine a correction duty cycle d _cor in a FC voltage regulator block 145. Advantageously, the correction duty cycle d _cor is determined based on equation (4). The FC voltage regulator block 145 comprises the measured FC voltage UFC as an input. A voltage error signal is determined by subtracting UFC from U*FC. An FC current reference i*pc can be determined from the voltage error signal, such as by proportional and/or integral control. Dividing by twice the inductor current i _ac executes equation (4) to determine the correction duty cycle d _cor . The correction duty cycle d _cor is then passed to a limiter to ensure valid duty cycles di, d2 e [0; 1], Finally, control block 145 is configured to determine the duty cycles di and d2 from d _cor and the duty cycle d supplied by control block 140 via equation (3).

[0049] Referring to Fig. 5B, the bandwidth required for the inductor current control block 143 can be greatly reduced by adding a feedforward compensation u _cor in block 143. The feedforward term u _cor can be determined based on the correction duty cycle dcor and a voltage deviation of the actual FC voltage UFC from the balanced voltage Vb _aian ced of the flying capacitor. The balanced voltage is obtained through natural voltage balancing and can be expressed as: with U*dc being the DC-link voltage reference and n the number of voltage levels (n-2 flying capacitors). When n = 3 (i.e. one flying capacitor as in Fig. 3), Vb _aian ced = 0.5 U*d _C .

[0050] Referring to Fig. 6, when the FC circuit 23 comprises more than three levels, and hence a plurality of cascaded flying capacitors CFCI, CFC2, the duty cycles of the additional switch pair(s) T3, T’3 can be obtained by implementing upper and lower voltage reference values UFc.max and UFc.min and/or voltage reference U*FC for each additional flying capacitor CFC2 and determining a correction duty cycle from it. By way of example, the control unit 14 will comprise an FC power control block 141 for each flying capacitor CFCI, CFC2 and determine correction duty cycles d _cor i, d _cor 2 respectively. The duty cycles di, d2 and da of switch pairs Ti, T’i, T2, T’2 and T3, T’3 respectively can be obtained via the relationship: d ₂ = d + dcori ; d ₃ = d - d _cori + d _cor 2 ; di = d - d _cor 2.

[0051] More generally, it can be stated that for an n-level FC circuit 33 as shown in Fig. 7 comprising n-2 cascaded FCs C CI - Cpcn-2: d ₂ = d + dcor ; da ^— d dcor,1 "*■ dcor,2 ; dj = d - dcor,i-2 + dcor,i-i for 4 < i < n-1 ; di — d dcor,n-2 , wherein d _cor ,i represents the correction duty cycle determined for FC C CI, e.g. based on a reference voltage U* CI of C CI which can be determined based on (binary) upper and lower voltage references for C CI as described above.

[0052] It is alternatively possible to utilize some but not all the flying capacitors as a power pulsation buffer. Since the correction duty cycle of a specific flying capacitor is determined based on a flying capacitor voltage reference U* C to achieve active flying capacitor voltage balancing, the correction duty cycle of a flying capacitor not participating in power pulsation buffering can be determined based on a constant flying capacitor voltage reference to maintain the flying capacitor voltage balanced, e.g. as determined based on Eq. (6).

[0053] The FC circuits and related control scheme according to aspects of the present disclosure can be utilized in any suitable converter topology. Hence applications are not limited to the converter topology of Fig. 3. Referring to Fig. 3, the diode full-bridge can e.g. be omitted if the converter comprises a second FC bridge-leg. [0054] Another useful topology is the converter 40 depicted in Figs. 8A-B, allowing operation both when connected to the three-phase and to the single-phase grid. Converter 40 comprises three FC bridge-legs 431 , 432, 433, and each can have the topology as any of the FC circuits 13, 23, 33 described above. The three FC bridge-legs 431-433 have their DC nodes connected to the respective upper and lower DC rails DC+, DC- of the DC-link 11. The converter 40 further comprises two secondary DC/DC converters 451 , 452, which can be isolated DC/DC converters providing isolation for e.g. safety reasons.

[0055] In three-phase operation as shown in Fig. 8A, each FC bridge-leg

431-433 has its switch node s connected to a respective phase a, b, c of the three-phase grid. The grid input power is typically constant in three-phase operation, and the control units (not shown) for each of the FC bridge-legs can operate under a normal operating mode as known in the art, without utilizing the control block 141 for active FC voltage control. Alternatively, active FC voltage control can be performed by supplying block 145 with a constant FC voltage reference corresponding to balanced FC voltages (e.g. Eq. (6)). For a boost-type system, a large DC-link voltage is required with U _dc > u _ac with u _ac the magnitude of the three-phase mains voltage. In such cases, Udc = 800 V is a typical voltage level allowing to utilize 600 V Gallium Nitride (GaN) MOSFETs, which can be also employed in the two isolated DC/DC converters 451 , 452, which are arranged in Input-Series-Output-Parallel (ISOP) configuration.

[0056] In single-phase operation, as shown in Fig. 8B, only two of the three

FC bridge-legs 431 , 433 are connected to the line and neutral terminals of the singlephase grid a, N respectively. The third FC bride-leg 432 is disconnected and is not operated. The grid input power is now pulsating with twice the mains frequency. Since the minimum DC-link voltage criterion is relaxed to U _dc > u _ac , e.g. Udc = 400 V approximately a factor two lower compared to three-phase operation. The control units for either one or both FC-bridge-legs 431 , 433 can be operated according to the control scheme described in relation to Fig. 5 (control unit 14). As a result, the FC voltage UFC is cycled in a wide range. By so doing, the FC bridge-legs can be designed with reduced required DC-link capacitor value, and/or the power pulsation at the DC-link 11 is reduced compared to operation with constant FC voltages. By reconfiguring the isolated DC/DC converters to Input-Parallel-Output-Parallel (IPOP), the voltage and current stresses of the DC/DC isolation remain equal to three-phase operation.

[0057] To design the converter system for minimal total capacitance, the upper and lower voltage references upc.max and upc.min can be determined according to an iterative procedure as follows. Firstly, the initial DC-link capacitance value Cdc for a defined AV is selected according to equation (2), i.e., for conventional operation (e.g. with constant flying capacitor voltages). Secondly, a simulation is performed for a very large FC capacitance value CFC. In this case, a maximum energy will be buffered in the FC, which is constrained by the limits in duty cycle and the time-varying AC current i _ac . As a result, a simulated DC-link voltage variation (ripple) V _Sjm < AV is obtained. Based on the simulated DC-link voltage variation AV _Sjm the DC-link capacitor value is reduced to C _dc = C _dc V _sim / V. Subsequently, the FC capacitance value CFC is reduced iteratively, until UFC = UFc.min and UFC = UFc.max is reached within one mains period. By so doing, advantageously, the FC energy storage is maximally utilized while the resulting DC-link voltage variation is not impacted by the reduced FC value. Further reducing the FC value beyond this point would result in a reduced energy buffering capability and a DC-link capacitance Cdc would need to be increased again to comply with the voltage ripple criterion AV.

[0058] The control scheme of the present disclosure was tested through simulations. Fig. 9A represents a comparative simulation of the converter waveforms for the converter of Fig. 2 without employing the control block 141 for correcting the duty cycles. Results are shown for an output power of 3.3 kW, grid voltage of 230 V _rm s and Ude = 400 V. The peak-to-peak DC-link voltage ripple V _Sjm shown in the bottom graph of Fig. 9A was 20 V and the DC-link capacitor capacitance Cdc was 1300 pF. The voltage at the switch node s is represented by u _s .

[0059] Fig. 9B represents simulation of the converter of Fig. 3 fully utilizing the control scheme of Fig. 5 for same input and output conditions as Fig. 9A. It can be seen that the FC voltage varies in a wide range of upc.min = 20 V to upc.max = 380 V. P _t h was adjusted dynamically through a slow l-regulator controlling the value of UFC to Udc/2. The steady-state value of Pth resulted to be 920 W. Despite the large FC voltage variation, a sinusoidal input current i _ac could still be maintained. The DC-link voltage variation AV within one mains period is again equal to 20 V. However, in Fig. 9B, the DC- link capacitance Cdc was only 867 pF, which is 33% smaller compared to Fig. 9A. The capacitance of the FC CFC was set to 90 pF and was determined iteratively according to the procedure set out above. Hence, the overall capacitance can be reduced by 26%.

[0060] Further comparative simulations were performed for the same converter of Fig. 2 (without employing the control block 141 for correcting the duty cycles), for an output power of 3.3 kW, grid voltage of 230 V _rm s and Ude = 400 V like the previous simulation example, but now with DC-link capacitor capacitances of 660 pF and 440 pF, resulting in a peak-to-peak DC-link voltage ripple of 40 V and 60 V, respectively. The same simulations were repeated on the converter of Fig. 3, now fully utilizing the control scheme of Fig. 5 to reduce the total capacitance in the system while maintaining a same peak-to-peak DC-link voltage ripple of 40 V and 60 V, respectively. The flying capacitor capacitance was maintained at 90 pF. These simulations resulted in DC-link capacitor capacitances of 435 pF and 293 pF, respectively, resulting in total capacitance savings of 20% and 13%, respectively, compared to the converter of Fig. 2.

[0061] Referring to FIG. 10, a battery charging system 700 comprises a power supply unit 704. The power supply unit 704 is coupled on one side to the AC grid through terminals a, b, c, and on the other side (at terminals P’, N’) to an interface 702, e.g. comprising a switch device, which allows to connect the power supply unit 704 to a battery 703. It will be convenient to note that alternatively, the power supply unit can be configured as a single-phase AC/DC converter. The power supply unit 704 comprises the electrical converter 40 (or a single-phase converter 10) as described hereinabove. Power supply unit 704 can comprise a DC-DC converter stage 701. The power supply unit 704, e.g. the converter stage 701 , can comprise a pair of coils which are inductively coupled through air (not shown), such as in the case of wireless power transfer. Alternatively, the DC-DC converter stage 701 can comprise or consist of one or more isolated DC-DC converters, e.g. the DC/DC converters 451 , 452 shown in Fig. 8A. In some cases, the interface 702 can comprise a plug and socket, e.g. in wired power transfer. Alternatively, the plug and socket can be provided at the input (e.g., at nodes a, b, c).

[0062] Aspects of the present invention are set out in the following alphanumerically ordered clauses.

A1. Electrical converter, comprising: a DC link (11), a control unit (14) and a first flying capacitor circuit (13), wherein the first flying capacitor circuit comprises a flying capacitor (CFC), a switch node (s), a first switch pair (Ti, Ti’) and a second switch pair (T2, T2’), wherein the DC link comprises an upper DC node (DC+) and a lower DC node (DC-), wherein the first switch pair (Ti, Ti’) is arranged between the upper DC node and an upper terminal of the flying capacitor, and between the lower DC node and a lower terminal of the flying capacitor, wherein the second switch pair (T2, T2’) is arranged between the switch node (s) and the upper and lower terminals of the flying capacitor, wherein the control unit (14) is configured to operate the first and second switch pairs to convert power between the switch node (s) and the DC link (11), characterised in that the control unit comprises an operating mode, the operating mode being configured to determine a voltage reference (U*FC, UFC,max, UFC, min ) for a voltage of the flying capacitor based on an instantaneous power imbalance between the switch node (s) and the DC link (11) and to control a power of the flying capacitor (CFC) based on the voltage reference.

A2. Electrical converter of clause A1 , wherein the operating mode of the control unit is configured to adjust the voltage reference within each half period of a fundamental voltage waveform applied at the switch node (s).

A3. Electrical converter of clause A1 or A2, wherein the operating mode of the control unit is configured to determine the voltage reference so as to at least partially charge the flying capacitor and to at least partially discharge the flying capacitor within half a period of a fundamental voltage waveform applied at the switch node (s). A4. Electrical converter of any one of the preceding clauses, wherein the operating mode is configured to determine a first duty cycle (di) for the first switch pair and a second duty cycle (d2) for the second switch pair based on an error signal determined from the voltage reference (U*FC) of the voltage of the flying capacitor and an actual voltage of the flying capacitor, preferably the first duty cycle being different from the second duty cycle.

A5. Electrical converter of any one of the preceding clauses, wherein the operating mode is configured to: determine a common duty cycle (d) based on a first voltage error signal of a voltage of the DC link and/or a first current error signal of a current of the switch node, determine a correction duty cycle (d _cor ) based on a second voltage error signal of a voltage (UFC) of the flying capacitor, the second voltage error signal being based on the determined voltage reference, and determine the first duty cycle (di) for the first switch pair and the second duty cycle (di) for the second switch pair based on the correction duty cycle (d _cor ) and the common duty cycle (d).

A6. Electrical converter of any one of the preceding clauses, wherein the operating mode is configured to select the voltage reference (U*FC) from at least one of an upper voltage reference (uFc.max) and a lower voltage reference (upc.min).

A7. Electrical converter of clause A6, wherein the control unit is implemented with a power imbalance threshold (P _t h) and a compare logic configured to select between at least the upper voltage reference (UFc.max) and the lower voltage reference (uFc.min) as the voltage reference (U*FC) based on a comparison of the instantaneous power imbalance with the power imbalance threshold.

A8. Electrical converter of clause A6 or A7, wherein the operating mode is configured to determine the voltage reference (U*FC) of the voltage of the flying capacitor comprising toggling between at least the upper voltage reference (UFc.max) and the lower voltage reference (UFc.min).

A9. Electrical converter of clause A8, wherein the operating mode is configured to toggle between the upper voltage reference (UFc.max) and the lower voltage reference (UFc.min) at least twice within a period of a fundamental voltage waveform.

A10. Electrical converter of any one of the clauses A6 to A9, wherein the upper voltage reference (UFc.max) and the lower voltage reference (UFc.min) are fixed reference values within at least one half of a period of a fundamental voltage waveform.

A11. Electrical converter of any one of the clauses A6 to A10, wherein the upper voltage reference (upc.max) is between half a voltage of the DC-link and a voltage smaller than a voltage of the DC-link and the lower voltage reference (upc.min) is between 0V and half a voltage of the DC-link, wherein the upper voltage reference (upc.max) is larger than the lower voltage reference (upc.min).

A12. Electrical converter of any one of the preceding clauses, wherein the flying capacitor circuit comprises at least one further flying capacitor (CFC2) cascaded between the upper DC node (DC+) and the lower DC node (DC-), and a further switch pair (T3, T’3) for each of the at least one further flying capacitor, wherein the further switch pair is arranged between an upper terminal of the corresponding further flying capacitor and the switch node, and between a lower terminal of the corresponding further flying capacitor and the switch node, wherein the first, second and further switch pairs are connected in series between the upper DC node (DC+) and the lower DC node (DC-).

A13. Electrical converter of clause A12, wherein the operating mode is further configured to determine a further voltage reference (U*FC, UFC, max, UFC, min) for the at least one further flying capacitor (CFC2) based on the instantaneous power imbalance between the switch node (s) and the DC link (11) and to control a power of the at least one further flying capacitor (CFC2) based on the further voltage reference.

A14. Electrical converter of clause A13, wherein the operating mode is configured to select the further voltage reference (U*FC) from one of a further upper voltage reference (uFc.max) and a further lower voltage reference (uFc.min) for the at least one further flying capacitor.

A15. Electrical converter of any one of the preceding clauses, comprising an inductor (L) connected to the switch node (s), wherein the inductor is configured to define a current (i _ac ) at the switch node (s).

A16. Electrical converter of any one of the preceding clauses, comprising a further converter stage (121) configured to convert between an AC signal at a first side (g, N) of the further converter stage and a rectified signal of the AC signal at a second side (q, r) of the further converter stage, wherein the second side is coupled to the switch node (s) through an inductor (L).

A17. Electrical converter of any one of the preceding clauses, further comprising an inductor (L), wherein the inductor comprises opposite first and second terminals, wherein the second terminal of the inductor is connected to the switch node (s) and wherein the electrical converter is configured to convert between a full wave or half wave rectified single phase AC voltage applied at the first terminal of the inductor and a DC voltage of the DC-link (11).

A18. Electrical converter (40) of any one of the preceding clauses, comprising at least two further flying capacitor circuits (431 , 432, 433), wherein the first flying capacitor circuit and the at least two further flying capacitor circuits are connected to the DC link (11) in parallel, and wherein the control unit (14) is configured to operate according to a first mode of operation, in which the first flying capacitor circuit and the at least two further flying capacitor circuits are operated to convert between three-phase AC power and DC power, and according to a second mode of operation, in which the first flying capacitor circuit and at least one of the further flying capacitor circuits are operated to convert between single phase AC power and DC power.

A19. Electrical converter of any one of the preceding clauses, wherein the control unit is configured to operate switches of at least one of the first switch pair, the second switch pair and optionally the further switch pair in a complementary mode.

A20. Battery charging system, comprising a power supply, the power supply comprising the electrical converter of any one of the preceding clauses.

A21. Electric motor drive system, comprising a power supply, the power supply comprising the electrical converter of any one of the clauses A1 to A19.

A22. Method of operating an electrical converter, wherein the electrical converter comprises a DC link (11) and a first flying capacitor circuit (13), wherein the first flying capacitor circuit comprises a flying capacitor (CFC), a switch node (s), a first switch pair (Ti, Ti’) and a second switch pair (T2, T2’), wherein the DC link comprises an upper DC node (DC+) and a lower DC node (DC-), wherein the first switch pair (Ti, Ti’) is arranged between the upper DC node and an upper terminal of the flying capacitor, and between the lower DC node and a lower terminal of the flying capacitor, wherein the second switch pair (T2, T2’) is arranged between the switch node (s) and the upper and lower terminals of the flying capacitor, the method comprising: operating the first and second switch pairs to convert power between the switch node (s) and the DC link (11), determining a power imbalance between the switch node (s) and the DC link (11), determining a voltage reference (U*FC, UFC, max, UFC, min ) for a voltage of the flying capacitor based on the power imbalance, and controlling a voltage of the flying capacitor (CFC) based on the voltage reference.

A23. Method of clause A22, wherein determining the voltage reference comprises selecting the voltage reference (U*FC) from at least one of an upper voltage reference (upcmax) and a lower voltage reference (uFCmin) .

A24. Method of clause A22 or A23, comprising determining a first duty cycle (di) for the first switch pair and a second duty cycle (di) for the second switch pair based on a flying capacitor voltage error signal between the voltage reference (U*FC) and an actual voltage of the flying capacitor, and operating the first switch pair with the first duty cycle and operating the second switch pair with the second duty cycle.

A25. Method of clause A24, comprising: determining a common duty cycle (d) based on a first voltage error signal of a voltage of the DC link and/or a first current error signal of a current of the switch node, determining a correction duty cycle (d _cor ) based on the flying capacitor voltage error signal, and determining the first duty cycle (di) and the second duty cycle (di) based on the correction duty cycle (d _cor ) and the common duty cycle (d).